TW201539687A - 半導體結構及其形成方法 - Google Patents
半導體結構及其形成方法 Download PDFInfo
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- TW201539687A TW201539687A TW103145404A TW103145404A TW201539687A TW 201539687 A TW201539687 A TW 201539687A TW 103145404 A TW103145404 A TW 103145404A TW 103145404 A TW103145404 A TW 103145404A TW 201539687 A TW201539687 A TW 201539687A
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- seed layer
- semiconductor structure
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Abstract
在實施例中提供一種半導體結構及其形成方法。半導體結構包括第一基板及金屬墊形成在第一基板上。半導體結構還包括晶種層形成在金屬墊上及導體柱形成在晶種層上。此外,晶種層具有側壁及底表面,且晶種層的側壁及底表面之間的角度介於約20度至約90度。
Description
半導體裝置應用於各種電子裝置,例如個人電腦、手機、數位相機等各式電子儀器。半導體裝置的形成通常包括在半導體基板上依序沉積絕緣層或介電層、導電層及半導體層的材料,並利用微影圖案化各種材料層,以在其上形成電路零件及元件。
提升電腦表現的方法之一為提高電路的積體程度。此係藉由在給定晶片上微型化或縮小裝置尺寸。現代積體電路係以大量主動裝置做成,如電晶體及電容。這些裝置一開始彼此隔離,但之後彼此內連線以形成功能線路。典型的內連線結構包括水平內連線,如金屬線(線路),以及垂直內連線,如通孔及接觸插塞。內連線逐漸增加而決定了效能的限制及現代積體電路的密度。在內連線結構之上,可形成接合墊並暴露於各晶片的表面。藉由接合墊作為電性連接,以將晶片連接至封裝基板或另一晶粒。
然而,雖然現行接合墊大致滿足其需要,但隨著裝置持續縮小,它們並非在所有層面都完全令人滿意。
根據以下的詳細說明並配合所附圖式做完整揭露。應注意的是,根據本產業的一般作業,圖示並未必按照比
例繪製。事實上,可能任意的放大或縮小元件的尺寸,以做清楚的說明。
第1A至1F圖顯示在一些實施例中形成半導體結構100a的各階段剖面圖。
第2圖為在一些實施例中第1E圖所示半導體結構的一部分的放大圖。
第3A圖為在一些實施例中具有晶種層的半導體結構的剖面圖。
第3B圖為在一些實施例中在第3A圖所示半導體結構的一部分的放大圖。
第4圖為在一些實施例中具有晶種層的半導體結構的剖面圖。
第5A及5B圖為在一些實施例中包括如第1F圖所示之晶種層的半導體封裝體的剖面圖。
以下的揭露內容提供許多不同的實施例或範例以實施本案的不同特徵。以下的揭露內容敘述各個構件及其排列方式的特定範例,以簡化說明。當然,這些特定的範例並非用以限定。例如,若是本揭露書敘述了一第一特徵形成於一第二特徵之上或上方,即表示其可能包含上述第一特徵與上述第二特徵是直接接觸的實施例,亦可能包含了有附加特徵形成於上述第一特徵與上述第二特徵之間,而使上述第一特徵與第二特徵可能未直接接觸的實施例。另外,以下揭露書不同範例可能重複使用相同的參考符號及/或標記。這些重複係為了簡化與
清晰的目的,並非用以限定所討論的不同實施例及/或結構之間有特定的關係。
此外,其與空間相關用詞。例如“在...下方”、“下方”、“較低的”、“上方”、“較高的”及類似的用詞,係為了便於描述圖示中一個元件或特徵與另一個(些)元件或特徵之間的關係。除了在圖式中繪示的方位外,這些空間相關用詞意欲包含使用中或操作中的裝置之不同方位。裝置可能被轉向不同方位(旋轉90度或其他方位),則在此使用的空間相關詞也可依此相同解釋。
在本揭露一些實施例中提供半導體結構的形成方法的實施例。半導體結構可包括晶種層及導體柱形成在晶種層上。第1A至1F圖顯示在一些實施例中形成半導體結構100a的各階段剖面圖。
參照第1A圖,在一些實施例中提供基板102。基板102可為半導體晶片。基板102可包括應用於積體電路製造中的多種半導體基板的一種,且積體電路可形成在基板102之中或之上。基板102可為矽基板。基板102或者可為或可額外包括元素半導體材料(elementary semiconductor materials)、化合物半導體材料(compound semiconductor materials)、及/或合金半導體材料(alloy semiconductor materials)。元素半導體材料例如可為結晶矽(crystal silicon)、多晶矽(polycrystalline silicon)、非晶矽(amorphous silicon)、鍺、及/或鑽石,但並非以此為限。化合物半導體材料例如可為碳化矽(silicon carbide)、砷化鎵(gallium arsenic)、磷化鎵(gallium phosphide)、磷化銦(indium
phosphide)、砷化銦(indium arsenide)、及/或銻化銦(indium arnimonide),但並非以此為限。合金半導體材料例如可為矽鍺(SiGe)、鎵砷磷(GaAsP)、鋁銦砷(AlInAs)、鋁鎵砷(AlGaAs)、鎵銦砷(GaInAs)、鎵銦磷(GaInP)、及/或鎵銦砷磷(GaInAsP),但並非以此為限。
此外,基板102可更包括複數個隔離元件,例如淺溝槽隔離元件或矽的局部氧化(locao oxidation of silicon;LOCOS)元件。隔離元件隔離在基板之中及/或之上的多種微電子元件(microelectronic elements)。在基板102中所形成的微電子元件例如為電晶體,如金氧半場效電晶體(MOSFETs)、互補式金氧半(CMOS)電晶體、雙極性接面電晶體(bipolar junction transistor;BJTs)、高壓電晶體、高頻電晶體、P-通道及/或N-通道場效電晶體(PFETs/NFETs)、電阻、二極體、電容、電感、熔線及/或其他適用的元件,但並非以此為限。
可進行多種製程以形成多種微電子元件,包括一或多種沉積、蝕刻、佈植、光微影、回火及其他適合的製程,但並非以此為限。微電子元件可內連線而形成積體電路裝置,包括邏輯裝置、記憶體裝置(如SRAM)、無線頻率(RF)裝置、輸入/輸出裝置、晶片上系統(system-on-chip)裝置或其他適用的裝置。
此外,基板102可更包括內連線結構覆蓋在積體電路上。內連線結構可包括層間介電層及金屬層結構覆蓋積體電路。在金屬層結構中的層間介電層可包括低介電常數介電材料、未摻雜矽玻璃、氮化矽、氮氧化矽、或其他一般使用的材
料。在金屬層結構中的金屬線可利用銅、銅合金或其他適當的導電材料形成。
在一些實施例中,在基板102上形成金屬墊104,如的1A圖所示。在一些實施例中,以導體材料形成金屬墊104,如鋁、銅、鎢、銅鋁合金、銀或其他適合的導體材料。金屬墊104的形成可利用化學氣相沉積、物理氣相沉積或其他適合的技術。此外,金屬墊104可為基板102中導電線路的一部份,且可用以提供電性連接,其上可形成凸塊結構,使外部電性連結更為容易。
在一些實施例中,在基板102上形成保護層103,保護層103具有開口,以暴露金屬墊104的一部份,如第1A圖所示。可利用介電材料形成保護層103,例如氮化矽、氮氧化矽、氧化矽、或未摻雜矽玻璃(USG)。保護層103的形成可利用化學氣相沉積、物理氣相沉積、原子層沉積、高密度電漿化學氣相沉積、金屬有機化學氣相沉積、電漿強化化學氣相沉積、或熱製程如爐管沉積。
此外,在一些實施例中,在保護層103上形成聚合物層105,如第1A圖所示。聚合物層105也暴露出金屬墊104的一部份。形成聚合物層105的材料例如為聚亞醯胺(polyimide)、環氧(epoxy)、苯並環丁烯(benzocyclobutene)、聚苯并噁唑(polybenzoxazole)等,但也可利用其他相對軟、通常為有機的介電材料。聚合物層105的形成可利用化學氣相沉積、物理氣相沉積、或其他適合的技術。應注意的是,雖然第1A圖顯示了保護層103及聚合物層105,保護層103及聚合物層
105的形成為非必要的。因此,在一些實施例中,沒有形成保護層103及聚合物層105。
而後,在一些實施例中,在基板102上形成晶種層(seed layer)106以覆蓋金屬墊104,如第1A圖所示。在一些實施例中,利用導體材料形成晶種層106,例如鈦鎢(TiW)、鈦銅(TiCu)、銅(Cu)、銅鋁(CuAl)、銅鉻(CuCr)、銅銀(CuAg)、銅鎳(CuNi)、銅錫(CuSn)、銅金(CuAu)等。晶種層106的形成可利用物理氣相沉積、濺鍍或其他適合的製程。在一些實施例中,晶種層106具有一厚度介於約0.05μm至約1μm。當晶種層106的厚度太薄時,其導電性可能不夠。相對的,當晶種層106的厚度太大時,形成半導體結構100a的花費可能會增加。
此外,晶種層106的形成可利用單一層或多層。在一些實施例中,晶種層106包括複數個導體層,且至少一層導體層係以鈦鎢(TiW)形成。
在一些實施例中,在晶種層106上形成光阻層108,如第1B圖所示。光阻層108包括開口110在金屬墊104上,使得晶種層106在金屬墊104上的一部份被開口110所暴露。在一些實施例中,在光阻層108中的開口110的形成係藉由使用光罩進行光微影以圖案化光阻層108。
在一些實施例中,在形成光阻層108之後,在光阻層108的開口110中形成凸塊結構112,如第1C圖所示。凸塊結構112包括導體柱(conductive pillar)114形成在金屬墊104上的晶種層106上,以及焊料層116形成在導體柱114上。
更詳細而言,在一些實施例中,在開口110中形成
金屬性材料,以形成導體柱114。在一些實施例中,金屬性材料包括純元素銅、含不可避免的不純物的銅及/或含有微量的元素(如鉭(Ta)、銦(In)、錫(Sn)、鋅(Zn)、錳(Mn)、鉻(Cr)、鈦(Ti)、鍺(Ge)、鍶(Sr)、鉑(Pt)、鎂(Mg)、鋁(Al)、鋯(Zr))的銅合金。
導體柱114的形成可利用濺鍍、印刷、電極電鍍(electroplating)、無電極電鍍(electro-less plating)、電化學沉積(electrochemical deposition)、分子束磊晶(molecular beam epitaxy)、原子層沉積及/或一般使用的化學氣相沉積方法。在一些實施例中,利用電化學電鍍形成導體柱114。
接著,在一些實施例中,在導體柱114上形成焊料層116,如第1C圖所示。在一些實施例中,導體柱114上形成焊料材料,以在開口110中形成焊料層116。在一些實施例中,焊料材料包括錫、銀、銅或前述之組合。在一些實施例中,焊料材料為不含鉛的材料。焊料層116的形成可利用電極電鍍、化學電鍍或其他適合的製程。
在形成凸塊結構112之後,在一些實施例中,移除光阻層108,如第1D圖所示。光阻層108的剝除可藉由利用有機剝除劑(organic strippers)、濕無機剝除劑(氧化型剝除劑)或利用電漿蝕刻儀器進行乾蝕刻。如第1D圖所示,在光阻層108移除後,晶種層106的一部份被暴露出來。
在一些實施例中,對晶種層106未被導體柱114覆蓋的部分進行濕蝕刻製程117,如第1E圖所示。在一些實施例中,濕蝕刻製程117包括利用包括過氧化氫(H2O2)的蝕刻液。
在一些實施例中,在濕蝕刻製程117中所使用的過氧化氫的濃度介於約5wt%至約70wt%。在一些實施例中,進行濕蝕刻製程117的溫度介於約20℃至約80℃。
一般而言,濕蝕刻製程為等向性蝕刻(isotropic etching)製程。因此,在利用濕蝕刻製程移除晶種層未被導體柱覆蓋的部分時,在導體柱下的晶種層的一部份也傾向被移除,而在導體柱下的晶種層的側壁形成凹洞。然而,晶種層的凹洞的形成會在晶種層下方的金屬間介電層(inter-metal dielectric layer)上誘發更多的應力,其係由於在其有相同的晶片彎曲誘發力,但有較小的分配面積。因此,在本揭露的一些實施例中,調整在濕蝕刻製程117中所使用的蝕刻液,使得在導體層114下的晶種層106不會被移除,且在濕蝕刻製程117中,凹洞不會形成在晶種層106的側壁上,如第2圖所示一些實施例。
第2圖為在一些實施例中第1E圖所示半導體結構100a的部分122的放大圖。如第2圖所示,晶種層106具有側壁118及底表面120,且晶種層106的側壁118及底表面120之間的角度θ1介於約20度至約90度。亦即,在導體柱114下的晶種層106並未被濕蝕刻製程117所蝕刻,因此晶種層106具有相對較大的尺寸。故應力被分佈在相對較大的尺寸中,因此在導體柱114下形成在基板102中的金屬間介電層上每單位體積所受到的應力較小。當角度θ1太大時,可能會形成凹洞,且晶種層106上的平均應力增加。當角度θ1太小時,在聚合物層105上遺留下大量的晶種層,在凸塊結構112及形成在鄰近於凸塊結
構112的另一個凸塊結構之間電性短路的風險增加。
在一些實施例中,晶種層106更包括延伸部分124延伸自導體柱114。在一些實施例中,延伸部分124的形狀為三角形。在一些實施例中,三角形的延伸部分124有助於釋放導體柱114的應力,且提升半導體結構100a中應力的分佈。
在一些實施例中,介於側壁118及底表面120之間的角度θ1介於約20度至約85度。在一些實施例中,介於側壁118及底表面120之間的角度θ1介於約20度至約40度。在一些實施例中,介於側壁118及底表面120之間的角度θ1介於約40度至約60度。在一些實施例中,介於側壁118及底表面120之間的角度θ1介於約60度至約80度。
在一些實施例中,延伸部分124具有寬度W1介於約0.05μm至約3μm。晶種層106的延伸部分124的形成可提升在半導體結構100a中應力的分佈。
在進行濕蝕刻製程117之後,在一些實施例中,藉由回流製程回流焊料層116,如第1F圖所示。如第1F圖所示,在進行回流製程之後,焊料層116具有球面的頂表面。
第3A圖為在一些實施例中具有晶種層106’的半導體結構100b的剖面圖。第3B圖為在一些實施例中在第3A圖所示半導體結構100b的部分122’的放大圖。除了半導體結構100b中沒有形成保護層103及聚合物層105之外,具有晶種層106’的半導體結構100b皆類似於第1F圖所示具有晶種層106的半導體結構100a。用以形成半導體結構100b的製程及材料類似於用以形成半導體結構100a的,在此不重複敘述。
更詳細而言,在一些實施例中,在基板102上形成金屬層104,且在金屬層104上形成晶種層106’,如第3A圖所示。而後,在晶種層106’上形成凸塊結構112’,其包括導體柱114及焊料層116。既然在半導體結構100b中沒有形成保護層103及聚合物層105,晶種層106’直接形成在金屬層104上。
如第3B圖所示,晶種層106’也具有側壁118’及底表面120’,且側壁118’及底表面120’之間的角度θ1’相同於或相似於第2圖所示的角度θ1。例如,角度θ1’介於約20度至約90度。
此外,在一些實施例中,晶種層106’也包括延伸部分124’。在一些實施例中,延伸部分124’具有類似於寬度W1的寬度介於約0.05μm至約3μm。此外,形成在金屬層104上的晶種層106’的延伸部分124’可提升半導體結構100b中應力的分佈。
第4圖為在一些實施例中具有晶種層106”的半導體結構100c的剖面圖。除了晶種層106”及凸塊結構112”係形成於聚合物層105的開口中,具有晶種層106”的半導體結構100c類似於第1F圖所示具有晶種層106的半導體結構100a。用以形成半導體結構100c的製程及材料類似於用以形成半導體結構100a的,在此不重複敘述。
更詳細而言,在一些實施例中,在基板102上形成金屬層104,且在基板102上形成保護層103及聚合物層105並覆蓋金屬層104的尾端,如第4圖所示。此外,聚合物層105具有開口,以暴露出金屬層104的一部份,且晶種層106”及凸塊結
構112”形成在開口中而未與保護層103及聚合物層105重疊。
在一些實施例中,凸塊結構112”包括導體柱114及形成在導體柱114上的焊料層116。形成在金屬墊104上且未與保護層103及聚合物層105重疊的晶種層106”也可改善半導體結構100c的應力分佈。
在形成半導體結構(如半導體結構100a、100b、或100c)之後,基板102(例如半導體晶片)可接合至另一基板,如介電基板、封裝基板、印刷電路板(PCB)、中介層(interposer)、晶圓、另一晶片、封裝單元等。例如,實施例可利用晶片對基板接合配置、晶片對晶片接合配置、晶片對晶圓接合配置、晶圓對晶圓接合配置、晶片級封裝、晶圓級封裝等。
第5A圖為在一些實施例中包括如第1F圖所示之晶種層106的半導體封裝體500a的剖面圖。在一些實施例中,形成在基板102上之晶種層106上的凸塊結構112接合至形成在第二基板202上的導體元件204。在一些實施例中,透過焊料層116接合凸塊結構112及導體元件204,例如藉由回流製程。因此,導體元件204的側壁可被焊料層116完全覆蓋,如第5A圖所示。
在一些實施例中,基板102為半導體晶片,基板202為封裝基板。在一些實施例中,導體元件204為金屬導線(metal trace),因此在半導體封裝體300中形成導線上凸塊(bump-on-trace)內連線。
第5B圖顯示在一些實施例中,包括在第1F圖所示之晶種層106的半導體封裝體500b的剖面圖。除了在半導體封裝體500b係以熱壓接合製程接合基板102及基板202之外,半導
體封裝體500b類似於半導體封裝體500a。
更詳細而言,藉由熱壓接合(heat-press-bonding)接合凸塊結構112及導體元件204。因此,焊料層116不會流至導體元件204的側壁。
如前述,在濕蝕刻製程中,若形成於導體柱下的晶種層被蝕刻,晶種層的側壁會形成凹洞。此凹洞可能導致導體柱中的應力集中於相對較小的面積,使得其下的介電層(例如:形成在基板中的極低介電常數介電層)傾向變得裂開或破損。此外,晶種層的有效面積會減小。
因此,在所述許多實施例中的晶種層,如晶種層106、106’及106”,係利用濕蝕刻製程117所形成,其被調整為不會蝕刻導體柱下的晶種層。因此,雖然進行了濕蝕刻製程,但在晶種層的側壁不會形成凹洞。此外,在一些實施例中,自導體柱114的側壁形成延伸部分,例如延伸部分124。因此,晶種層的有效面積增加。此外,在導體柱114中的應力可更平均的釋放至基板102,以避免基板102中的介電層破損或裂開。
一些實施例提供具有晶種層的半導體結構的形成。晶種層設置在金屬墊及導體柱之間。此外,在用來移除多餘的晶種層材料的濕蝕刻製程中,位於導體柱下的晶種層不會被蝕刻。因此,在導體柱下的晶種層的側壁不會形成凹洞。故可提升在半導體結構中應力的分佈。此外,晶種層的有效面積增加。
在一些實施例中,提供一種半導體結構。半導體結構包括第一基板及金屬墊,形成在第一基板上。半導體結構
更包括晶種層,形成在金屬墊上,以及導體柱,形成在晶種層上。此外,晶種層具有側壁及底表面,且晶種層的側壁及底表面之間的角度介於約20度至約90度。
在一些實施例中,提供一種半導體結構。半導體結構包括第一基板及金屬墊,形成在第一基板上。半導體結構更包括晶種層,形成在金屬墊上及導體柱,形成在晶種層上。半導體結構更包括焊料層,形成在導體柱上。此外,晶種層具有一延伸部分延伸自導體柱。
在一些實施例中,提供一種半導體結構的形成方法。半導體結構的形成方法包括在第一基板上形成金屬墊,及在第一基板上形成晶種層以覆蓋金屬墊。半導體結構的形成方法更包括在晶種層上形成導體柱及在導體柱上形成焊料層。半導體結構的形成方法更包括利用一濕蝕刻製程移除該晶種層的一部份,且該濕蝕刻製程包括利用包括過氧化氫(H2O2)的一蝕刻液。
前述內文概述了許多實施例的特徵,使本技術領域中具有通常知識者可以從各個方面更佳地了解本揭露。本技術領域中具有通常知識者應可理解,且可輕易地以本揭露為基礎來設計或修飾其他製程及結構,並以此達到相同的目的及/或達到與在此介紹的實施例等相同之優點。本技術領域中具有通常知識者也應了解這些相等的結構並未背離本揭露的發明精神與範圍。在不背離本揭露的發明精神與範圍之前提下,可對本揭露進行各種改變、置換或修改。
Claims (20)
- 一種半導體結構,包括一第一基板;一金屬墊,形成在該第一基板上;一晶種層,形成在該金屬墊上;以及一導體柱,形成在該晶種層上,其中該晶種層具有一側壁及一底表面,且該晶種層的該側壁及該底表面之間的一角度介於約20度至約90度。
- 如申請專利範圍第1項所述之半導體結構,其中該晶種層的該側壁延伸自該導體柱而形成該晶種層的一延伸部分。
- 如申請專利範圍第2項所述之半導體結構,其中該延伸部分的形狀為三角形。
- 如申請專利範圍第2項所述之半導體結構,其中該晶種層的該延伸部分具有一寬度介於約0.05μm至約3μm。
- 如申請專利範圍第2項所述之半導體結構,其中該景種層的該側壁及該底表面之間的一角度介於約20度至約85度。
- 如申請專利範圍第1項所述之半導體結構,其中該晶種層具有一厚度介於約0.05μm至約1μm。
- 如申請專利範圍第1項所述之半導體結構,其中該晶種層係以一導體材料形成,包括鈦鎢(TiW)、鈦銅(TiCu)、銅(Cu)、銅鋁(CuAl)、銅鉻(CuCr)、銅銀(CuAg)、銅鎳(CuNi)、銅錫(CuSn)、銅金(CuAu)、或前述之組合。
- 如申請專利範圍第1項所述之半導體結構,更包括:一焊料層,形成在該導體柱上;以及 一導體結構,形成在一第二基板上,其中該焊料層接合至該導體結構以組裝該第一基板及該第二基板。
- 如申請專利範圍第8項所述之半導體結構,其中該導體結構為一導線結構。
- 一種半導體結構,包括:一第一基板;一金屬墊,形成在該第一基板上;一晶種層,形成在該金屬墊上;一導體柱,形成在該晶種層上;以及一焊料層,形成在該導體柱上,其中該晶種層具有一延伸部分延伸自該導體柱。
- 如申請專利範圍第10項所述之半導體結構,其中該晶種層的該延伸部分具有一寬度介於約0.05μm至約3μm。
- 如申請專利範圍第10項所述之半導體結構,其中該延伸部分的形狀為三角形。
- 如申請專利範圍第10項所述之半導體結構,其中該延伸部分具有一側壁及一底表面,且該晶種層的該延伸部分的該側壁及該底表面之間的角度介於約20度至約85度。
- 如申請專利範圍第10項所述之半導體結構,更包括:一導體結構,形成在一第二基板上,其中該焊料層接合至該導體結構以組裝該第一基板及該第二基板。
- 一種半導體結構的形成方法,包括: 在一第一基板上形成一金屬墊;在該第一基板上形成一晶種層以覆蓋該金屬墊;在該晶種層上形成一導體柱及在該導體柱上形成一焊料層;以及利用一濕蝕刻製程移除該晶種層的一部份,其中該濕蝕刻製程包括利用包括過氧化氫(H2O2)的一蝕刻液。
- 如申請專利範圍第15項所述之半導體結構的形成方法,其中該過氧化氫的濃度介於約5wt%至約70wt%。
- 如申請專利範圍第15項所述之半導體結構的形成方法,其中在該濕蝕刻製程之後,該晶種層的剩餘部分具有一側壁及一底表面,且該晶種層的該側壁及該底表面之間的一角度介於約20度至約90度。
- 如申請專利範圍第15項所述之半導體結構的形成方法,其中形成該導體柱及該焊料層更包括:在該金屬墊上形成具有一開口的一光阻層;在該開口中形成一金屬性材料以形成該導體柱;在該開口中填入一焊料材料,以在該導體柱上形成該焊料層;以及移除該光阻層。
- 如申請專利範圍第15項所述之半導體結構的形成方法,更包括:將一導體結構接合至該焊料層上,其中該導體元件係形成在一第二基板上,且藉由該焊料層組裝該第一基板及該第二基板。
- 如申請專利範圍第19項所述之半導體結構的形成方法,其 中該導體結構為一導線結構。
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN111128904A (zh) * | 2018-10-30 | 2020-05-08 | 台湾积体电路制造股份有限公司 | 封装结构、管芯及其制造方法 |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9564410B2 (en) * | 2015-07-08 | 2017-02-07 | Texas Instruments Incorporated | Semiconductor devices having metal bumps with flange |
KR20180041811A (ko) | 2016-10-14 | 2018-04-25 | 삼성전자주식회사 | 반도체 소자 |
KR20210028266A (ko) * | 2018-07-26 | 2021-03-11 | 램 리써치 코포레이션 | 재분배 층 프로세스를 위한 대안적인 통합 |
CN111508919A (zh) * | 2019-01-31 | 2020-08-07 | 联华电子股份有限公司 | 半导体装置及半导体装置的制作方法 |
US11600590B2 (en) * | 2019-03-22 | 2023-03-07 | Advanced Semiconductor Engineering, Inc. | Semiconductor device and semiconductor package |
KR20210024869A (ko) | 2019-08-26 | 2021-03-08 | 삼성전자주식회사 | 반도체 칩 적층 구조, 반도체 패키지 및 이들의 제조 방법 |
US20210210449A1 (en) * | 2020-01-03 | 2021-07-08 | Qualcomm Incorporated | Thermal compression flip chip bump |
Family Cites Families (42)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
BE657708A (zh) * | 1963-12-30 | |||
JPS5120972B1 (zh) * | 1971-05-13 | 1976-06-29 | ||
US4462861A (en) * | 1983-11-14 | 1984-07-31 | Shipley Company Inc. | Etchant with increased etch rate |
US4787958A (en) * | 1987-08-28 | 1988-11-29 | Motorola Inc. | Method of chemically etching TiW and/or TiWN |
US5268072A (en) * | 1992-08-31 | 1993-12-07 | International Business Machines Corporation | Etching processes for avoiding edge stress in semiconductor chip solder bumps |
US5376584A (en) * | 1992-12-31 | 1994-12-27 | International Business Machines Corporation | Process of making pad structure for solder ball limiting metallurgy having reduced edge stress |
US5470787A (en) * | 1994-05-02 | 1995-11-28 | Motorola, Inc. | Semiconductor device solder bump having intrinsic potential for forming an extended eutectic region and method for making and using the same |
US5503286A (en) * | 1994-06-28 | 1996-04-02 | International Business Machines Corporation | Electroplated solder terminal |
JP3296400B2 (ja) * | 1995-02-01 | 2002-06-24 | 東芝マイクロエレクトロニクス株式会社 | 半導体装置、その製造方法およびCu製リード |
JP3415432B2 (ja) * | 1998-03-31 | 2003-06-09 | ティーディーケイ株式会社 | 薄膜磁気ヘッドおよびその製造方法 |
US6436300B2 (en) * | 1998-07-30 | 2002-08-20 | Motorola, Inc. | Method of manufacturing electronic components |
US6258703B1 (en) * | 1999-07-21 | 2001-07-10 | International Business Machines Corporation | Reflow of low melt solder tip C4's |
US6293457B1 (en) * | 2000-06-08 | 2001-09-25 | International Business Machines Corporation | Integrated method for etching of BLM titanium-tungsten alloys for CMOS devices with copper metallization |
US6657707B1 (en) * | 2000-06-28 | 2003-12-02 | Advanced Micro Devices, Inc. | Metallurgical inspection and/or analysis of flip-chip pads and interfaces |
JP3910363B2 (ja) * | 2000-12-28 | 2007-04-25 | 富士通株式会社 | 外部接続端子 |
US6489229B1 (en) * | 2001-09-07 | 2002-12-03 | Motorola, Inc. | Method of forming a semiconductor device having conductive bumps without using gold |
US6528417B1 (en) * | 2001-09-17 | 2003-03-04 | Taiwan Semiconductor Manufacturing Company | Metal patterned structure for SiN surface adhesion enhancement |
TW536766B (en) * | 2002-02-19 | 2003-06-11 | Advanced Semiconductor Eng | Bump process |
US6750133B2 (en) * | 2002-10-24 | 2004-06-15 | Intel Corporation | Selective ball-limiting metallurgy etching processes for fabrication of electroplated tin bumps |
JP4766831B2 (ja) * | 2002-11-26 | 2011-09-07 | 株式会社村田製作所 | 電子部品の製造方法 |
US6927493B2 (en) * | 2003-10-03 | 2005-08-09 | Texas Instruments Incorporated | Sealing and protecting integrated circuit bonding pads |
US20050151268A1 (en) * | 2004-01-08 | 2005-07-14 | Boyd William D. | Wafer-level assembly method for chip-size devices having flipped chips |
WO2005101499A2 (en) * | 2004-04-13 | 2005-10-27 | Unitive International Limited | Methods of forming solder bumps on exposed metal pads and related structures |
US7541275B2 (en) * | 2004-04-21 | 2009-06-02 | Texas Instruments Incorporated | Method for manufacturing an interconnect |
JP4119866B2 (ja) * | 2004-05-12 | 2008-07-16 | 富士通株式会社 | 半導体装置 |
KR100642765B1 (ko) * | 2004-09-15 | 2006-11-10 | 삼성전자주식회사 | 하이브리드 범프를 포함하는 미세전자소자칩, 이의패키지, 이를 포함하는 액정디스플레이장치 및 이러한미세전자소자칩의 제조방법 |
US8143722B2 (en) * | 2006-10-05 | 2012-03-27 | Flipchip International, Llc | Wafer-level interconnect for high mechanical reliability applications |
US7425278B2 (en) * | 2006-11-28 | 2008-09-16 | International Business Machines Corporation | Process of etching a titanium/tungsten surface and etchant used therein |
US8110508B2 (en) * | 2007-11-22 | 2012-02-07 | Samsung Electronics Co., Ltd. | Method of forming a bump structure using an etching composition for an under bump metallurgy layer |
US8610270B2 (en) * | 2010-02-09 | 2013-12-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and semiconductor assembly with lead-free solder |
US8823166B2 (en) * | 2010-08-30 | 2014-09-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Pillar bumps and process for making same |
US8389397B2 (en) * | 2010-09-14 | 2013-03-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for reducing UBM undercut in metal bump structures |
US20120098124A1 (en) * | 2010-10-21 | 2012-04-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device having under-bump metallization (ubm) structure and method of forming the same |
US8962358B2 (en) * | 2011-03-17 | 2015-02-24 | Tsmc Solid State Lighting Ltd. | Double substrate multi-junction light emitting diode array structure |
US8288871B1 (en) * | 2011-04-27 | 2012-10-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Reduced-stress bump-on-trace (BOT) structures |
KR101782503B1 (ko) * | 2011-05-18 | 2017-09-28 | 삼성전자 주식회사 | 솔더 범프 붕괴를 억제하는 반도체 소자의 범프 형성방법 |
US9905524B2 (en) * | 2011-07-29 | 2018-02-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bump structures in semiconductor device and packaging assembly |
US9824923B2 (en) * | 2011-10-17 | 2017-11-21 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming conductive pillar having an expanded base |
US9257385B2 (en) * | 2011-12-07 | 2016-02-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Landing areas of bonding structures |
JP6015239B2 (ja) * | 2012-08-24 | 2016-10-26 | Tdk株式会社 | 端子構造、並びにこれを備える半導体素子及びモジュール基板 |
KR102258660B1 (ko) * | 2013-09-17 | 2021-06-02 | 삼성전자주식회사 | 구리를 함유하는 금속의 식각에 사용되는 액체 조성물 및 이를 이용한 반도체 장치의 제조 방법 |
US9159683B2 (en) * | 2014-02-10 | 2015-10-13 | GlobalFoundries, Inc. | Methods for etching copper during the fabrication of integrated circuits |
-
2014
- 2014-03-13 US US14/208,871 patent/US20150262952A1/en not_active Abandoned
- 2014-12-25 TW TW103145404A patent/TWI625836B/zh active
-
2017
- 2017-10-05 US US15/725,535 patent/US20180033756A1/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN111128904A (zh) * | 2018-10-30 | 2020-05-08 | 台湾积体电路制造股份有限公司 | 封装结构、管芯及其制造方法 |
US10879224B2 (en) | 2018-10-30 | 2020-12-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package structure, die and method of manufacturing the same |
TWI752315B (zh) * | 2018-10-30 | 2022-01-11 | 台灣積體電路製造股份有限公司 | 封裝結構、晶粒及其製造方法 |
Also Published As
Publication number | Publication date |
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TWI625836B (zh) | 2018-06-01 |
US20180033756A1 (en) | 2018-02-01 |
US20150262952A1 (en) | 2015-09-17 |
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