TW201521123A - 半導體封裝件及其製法 - Google Patents

半導體封裝件及其製法 Download PDF

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TW201521123A
TW201521123A TW102143688A TW102143688A TW201521123A TW 201521123 A TW201521123 A TW 201521123A TW 102143688 A TW102143688 A TW 102143688A TW 102143688 A TW102143688 A TW 102143688A TW 201521123 A TW201521123 A TW 201521123A
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dielectric layer
layer
semiconductor package
adhesive member
circuit
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TW102143688A
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TWI503902B (zh
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沈子傑
邱士超
陳嘉成
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矽品精密工業股份有限公司
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Priority to TW102143688A priority Critical patent/TWI503902B/zh
Priority to CN201310682691.3A priority patent/CN104681532B/zh
Priority to US14/143,700 priority patent/US9082723B2/en
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Abstract

一種半導體封裝件及其製法，該半導體封裝件係包括：第一介電層、第一線路層、第二介電層、至少一黏著件、電子元件、第二線路層以及複數個導電盲孔，其中，該第一介電層係具有相對之第一表面與第二表面及貫穿該第一表面與第二表面之介電層開口，且該第一線路層嵌埋於該第一介電層中且外露於該第一表面，於該第一介電層之第二表面上形成有該第二介電層，其填入該介電層開口中，該介電層開口中的該第二介電層中形成有該黏著件，該電子元件設置於該介電層開口中的該黏著件上，且該第二介電層遠離該第一表面之表面上形成有該第二線路層，又於該第二介電層中形成有電性連接該第二線路層與電子元件之該複數導電盲孔。

Description

半導體封裝件及其製法
本發明係關於一種半導體封裝件及其製法，更詳言之，本發明係為一種具有嵌埋式線路之半導體封裝件及其製法。
由於科技日益進步，通訊、網路、及電腦等各式可攜式電子產品及其周邊產品的輕薄短小之趨勢日益重要，且該等電子產品更朝多功能及高性能的方向發展，於半導體製程上則不斷朝向積體化更高的製程演進，且高密度與低成本的封裝結構亦為業者追求的目標。
一般的具有嵌埋式線路之半導體封裝件係於預浸材(prepreg)之表面上以雷射燒灼形成凹槽，然後，於該凹槽中進行電鍍形成線路層。
不過，前述製程中的凹槽只能藉由雷射方式逐一形成，故此製程的成本較高，而且，習知的半導體封裝件係將電子元件設置於基板表面上，而佔據許多線路佈局空間，使線路之佈線較不具有彈性。
因此，如何克服習知技術之種種問題，實為一重要課題。
為解決上述習知技術之種種問題，本發明遂揭露一種半導體封裝件之製法，係包括：於一承載板上形成第一線路層；於該承載板上形成第一介電層，以包覆該第一線路層，令該第一介電層具有面向該承載板的第一表面與其相對之第二表面；形成貫穿該第一表面與第二表面之介電層開口，以外露部分該承載板；於該介電層開口中形成至少一黏著件；於該黏著件上設置電子元件；於該第一介電層及電子元件上形成第二介電層，以包覆該電子元件與黏著件；於該第二介電層中形成複數個電性連接該電子元件的導電盲孔，並於該第二介電層上形成電性連接該導電盲孔的第二線路層；以及移除該承載板。
前述之半導體封裝件之製法中，該黏著件係形成於該第一線路層上或該承載板上。
前述之半導體封裝件之製法中，復包括於該第一線路層與第一介電層上形成具有複數個第一絕緣保護層開孔的第一絕緣保護層，各該第一絕緣保護層開孔外露部分該第一線路層。
前述之半導體封裝件之製法中，復包括於該第二線路層與第二介電層上形成具有複數個第一絕緣保護層開孔的第二絕緣保護層，各該第二絕緣保護層開孔外露部分該第二線路層。
前述之半導體封裝件之製法中，復包括形成貫穿該第一介電層與第二介電層且電性連接該第一線路層與第二線路層的導電通孔。
本發明又提供一種半導體封裝件，係包括：第一介電層，係具有相對之第一表面與第二表面及貫穿該第一表面與第二表面之介電層開口；第一線路層，係嵌埋於該第一介電層中且外露於該 第一表面；第二介電層，係形成於該第一介電層之第二表面上，並填入該介電層開口中；至少一黏著件，係形成於該介電層開口中的第二介電層中，且鄰近該第一表面；電子元件，係設置於該介電層開口中的黏著件上；複數個導電盲孔，係形成於該第二介電層中，且電性連接該電子元件；以及第二線路層，係形成於該第二介電層遠離該第一表面之表面上，且電性連接該導電盲孔。
前述之半導體封裝件中，該黏著件係外露於該第一表面。
前述之半導體封裝件中，該第一線路層復嵌埋並外露於該第二介電層鄰近該第一表面的表面，且該黏著件係形成於該第一線路層上。
前述之半導體封裝件中，復包括第一絕緣保護層，係形成於該第一線路層與第一介電層上，且具有複數個外露部分該第一線路層的第一絕緣保護層開孔。
前述之半導體封裝件中，復包括第二絕緣保護層，係形成於該第二線路層與第二介電層上，且具有複數個外露部分該第二線路層的第二絕緣保護層開孔。
前述之半導體封裝件中，復包括導電通孔，係貫穿該第一介電層與第二介電層，且電性連接該第一線路層與第二線路層。
前述之半導體封裝件及其製法，該電子元件係為被動元件。
前述之半導體封裝件及其製法，該黏著件之材質係為導電膠。
前述之半導體封裝件及其製法，該導電膠係為異方性導電膠。
前述之半導體封裝件及其製法，該黏著件之材質係為不導電膠。
依上所述，本發明先於該承載板上形成第一介電層，且該第 一介電層包覆於該承載板上的第一線路層，再形成介電層開口，並於該介電層開口中形成黏著件，將電子元件設置於該黏著件上，再形成第二介電層於該承載板及該第一介電層上，且該第二介電層填滿該介電層開口，並包覆該黏著件與該電子元件，最後移除該承載板。
反之，習知技術於基板上先以雷射方式逐一燒製線路層凹槽，接著，於該線路層凹槽中進行電鍍製程以形成線路層，故對於整體結構的製程的成本較高，且習知技術會將電子元件設置於基板上，佔據許多線路佈局空間。
因此，本發明可縮小整體半導體封裝件結構之體積，且可更有彈性地佈設線路位置。
10、20‧‧‧承載板
101、201‧‧‧第一線路層
11、21‧‧‧第一介電層
111、211‧‧‧第一表面
112、212‧‧‧第二表面
113、213‧‧‧介電層開口
12、22‧‧‧黏著件
13、23‧‧‧電子元件
14、24‧‧‧第二介電層
141、241‧‧‧第二線路層
15、25‧‧‧導電盲孔
16、26‧‧‧導電通孔
17、27‧‧‧第一絕緣保護層
17a、27a‧‧‧第一絕緣保護層開孔
18、28‧‧‧第二絕緣保護層
18a、28a‧‧‧第二絕緣保護層開孔
第1A至1I圖係為本發明之半導體封裝件及其製法之第一實施例的剖面示意圖；以及第2A至2I圖係為本發明之半導體封裝件及其製法之第二實施例的剖面示意圖。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整， 在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如「上」及「一」等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
第一實施例
以下將配合第1A至1I圖以詳細說明本發明之半導體封裝件及其製法之第一實施例的剖面示意圖。
如第1A圖所示，提供一承載板10。
如第1B圖所示，係接續自第1A圖之製程，於該承載板10上形成第一線路層101。
如第1C圖所示，係接續自第1B圖之製程，於該承載板10上形成第一介電層11，以包覆該第一線路層101，且令該第一介電層11具有面向該承載板10的第一表面111與其相對之第二表面112，而該第一介電層11之材質例如為預浸材(prepreg)。
如第1D圖所示，係接續自第1C圖之製程，形成貫穿該第一表面111與第二表面112的介電層開口113，以外露部分該承載板10與第一線路層101。
如第1E圖所示，係接續自第1D圖之製程，於該介電層開口113中的該第一線路層101上形成至少一黏著件12，此外，該黏著件12之材質係為導電膠，例如異方性導電膠。
如第1F圖所示，係接續自第1E圖之製程，於該黏著件12上設置電子元件13，該電子元件13可為主動元件或被動元件，該被動元件例如為積層陶瓷電容器(Multi-layer Ceramic Capacitor， MLCC)。
如第1G圖所示，係接續自第1F圖之製程，於該第一介電層11及電子元件13上形成第二介電層14，該第二介電層14之材質例如為預浸材(prepreg)，以包覆該電子元件13與該黏著件12，接著，於該第二介電層14中形成複數個電性連接該電子元件13的導電盲孔15，又形成貫穿該第一介電層11與該第二介電層14且電性連接該第一線路層101的導電通孔16，並於該第二介電層14上形成第二線路層141，且該第二線路層141電性連接該導電盲孔15，而第二線路層141亦與該導電通孔16電性連接。
如第1H圖所示，係接續自第1G圖之製程，移除該承載板10。
如第1I圖所示，係接續自第1H圖之製程，於該第一線路層101與第一介電層11上形成具有複數個第一絕緣保護層開孔17a的第一絕緣保護層17，各該第一絕緣保護層開孔17a外露部分該第一線路層101，另外，於該第二線路層141與第二介電層14上形成具有複數個第二絕緣保護層開孔18a的第二絕緣保護層18，各該第二絕緣保護層開孔18a外露部分該第二線路層141。
第二實施例
以下將配合第2A至2I圖以詳細說明本發明之半導體封裝件及其製法之第二實施例的剖面示意圖。
如第2A圖所示，提供一承載板20。
復請參閱第2B圖，係接續自第2A圖之製程，於該承載板20上形成第一線路層201。
復請參閱第2C圖，係接續自第2B圖之製程，形成第一介電層21於該承載板20上，以包覆該第一線路層201，且令該第一介 電層21具有面向該承載板20的第一表面211與其相對之第二表面212。
復請參閱第2D圖，係接續自第2C圖之製程，形成貫穿該第一表面211與第二表面212的介電層開口213，以外露部分該承載板20。
復請參閱第2E圖，係接續自第2D圖之製程，於該介電層開口213中的該承載板20上形成黏著件22，此外，各該黏著件22之材質係為不導電膠。
復請參閱第2F圖，係接續自第2E圖之製程，於該黏著件22上設置電子元件23，而該電子元件23可為主動元件或被動元件，該被動元件例如為積層陶瓷電容器(Multi-layer Ceramic Capacitor，MLCC)。
復請參閱第2G圖，係接續自第2F圖之製程，於該第一介電層21及電子元件23上形成第二介電層24，該第二介電層24之材質例如為預浸材(prepreg)，以包覆該電子元件23與黏著件22，接著，於該第二介電層24中形成複數個電性連接該電子元件23的導電盲孔25，又形成貫穿該第一介電層21與該第二介電層24且電性連接該第一線路層201的導電通孔26，並於該第二介電層24上形成第二線路層241，且該第二介電層24電性連接該導電盲孔25，而第二線路層241亦與該導電通孔26電性連接。
復請參閱第2H圖，係接續自第2G圖之製程，移除該承載板20。
復請參閱第2I圖，係接續自第2H圖之製程，於該第一線路層201與第一介電層21上形成具有複數個第一絕緣保護層開孔 27a的第一絕緣保護層27，各該第一絕緣保護層開孔27a外露部分該第一線路層201，另外，於該第二線路層241與第二介電層24上亦形成具有複數個第二絕緣保護層開孔28a的第二絕緣保護層28，各該第二絕緣保護層開孔28a外露部分該第二線路層241。
本發明復提供一種半導體封裝件，係包括第一介電層11,21、第一線路層101,201、第二介電層14,24、至少一黏著件12,22、電子元件13,23、第二線路層141,241以及複數個導電盲孔15,25，而該第一介電層11,21具有相對之第一表面111,211與第二表面112,212及貫穿該第一表面111,211與第二表面112,212之介電層開口113,213，該第一線路層101,201係嵌埋於該第一介電層11,21中且外露於該第一表面111,211，於該第一介電層11,21之第二表面112,212上係形成有該第二介電層14,24，並且該第二介電層14,24填入該介電層開口113,213中，於該介電層開口113,213中的第二介電層14,24中形成有鄰近該第一表面111,211的各該黏著件12,22。
將該電子元件13,23設置於該介電層開口113,213中的黏著件12,22上，該些導電盲孔15,25形成於該第二介電層14,24中，且電性連接該電子元件13,23，而第二線路層141,241形成於該第二介電層14,24遠離該第一表面111,211之表面上，且電性連接該導電盲孔15,25。此外，本發明復包括有導電通孔16,26，其貫穿該第一介電層11,21與該第二介電層14,24，且電性連接該第一線路層101,201與該第二線路層141,241。
進一步根據前述之半導體封裝件，該黏著件22係外露於該第一表面211，如第2H圖所示，或者，該第一線路101層復嵌埋並 外露於該第二介電層14鄰近該第一表面111的表面，且該黏著件12係形成於該第一線路層101上，如第1H圖所示。
另外，根據前述之半導體封裝件，於該第一線路層101,201與該第一介電層11,21上復形成有第一絕緣保護層17,27，且該第一絕緣保護層17,27具有複數個外露部分該第一線路層101,201的第一絕緣保護層開孔17a,27a，另外，於該第二線路層141,241與該第二介電層14,24上復形成有第二絕緣保護層18,28，且該第二絕緣保護層18,28具有複數個外露部分該第二線路層141,241的第二絕緣保護層開孔18a,28a。
根據前述之半導體封裝件，該電子元件13,23係為被動元件，該被動元件係例如為積層陶瓷電容器(MLCC)，而該黏著件12之材質係為導電膠，該導電膠係為異方性導電膠，如第1H圖所示，或者，該黏著件22之材質係為不導電膠，如第2H圖所示。
綜上所述，本發明之半導體封裝件及其製法係先於該承載板上形成第一線路層與第一介電層，且藉由該第一介電層包覆該第一線路層，之後形成介電層開口，並於該介電層開口中形成黏著件，於該黏著件上設置電子元件，再形成第二介電層於該承載板及該第一介電層上，且該第二介電層填滿該介電層開口，該第二介電層亦包覆該黏著件與該電子元件，最後移除該承載板，以構成嵌埋形式之該第一線路層。因此，本發明無須使用雷射鑽孔技術即可嵌埋線路，故能有效降低成本，且本發明係將電子元件埋設於介電層中，以有效縮小整體體積，且更有較大空間彈性地佈設線路位置。
上述該些實施樣態僅例示性說明本發明之功效，而非用於限 制本發明，任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述該些實施態樣進行修飾與改變。此外，在上述該些實施態樣中之元件的數量僅為例示性說明，亦非用於限制本發明。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
101‧‧‧第一線路層
11‧‧‧第一介電層
113‧‧‧介電層開口
12‧‧‧黏著件
13‧‧‧電子元件
14‧‧‧第二介電層
141‧‧‧第二線路層
15‧‧‧導電盲孔
16‧‧‧導電通孔

Claims (19)

  1. 一種半導體封裝件之製法，係包括：於一承載板上形成第一線路層；於該承載板上形成第一介電層，以包覆該第一線路層，令該第一介電層具有面向該承載板的第一表面與其相對之第二表面；形成貫穿該第一表面與第二表面之介電層開口，以外露部分該承載板；於該介電層開口中形成至少一黏著件；於該黏著件上設置電子元件；於該第一介電層及電子元件上形成第二介電層，以包覆該電子元件與黏著件；於該第二介電層中形成複數個電性連接該電子元件的導電盲孔，並於該第二介電層上形成電性連接該導電盲孔的第二線路層；以及移除該承載板。
  2. 如申請專利範圍第1項所述之半導體封裝件之製法，其中，該黏著件係形成於該第一線路層上或該承載板上。
  3. 如申請專利範圍第1項所述之半導體封裝件之製法，復包括於移除該承載板後，於該第一線路層與第一介電層上形成具有複數個第一絕緣保護層開孔的第一絕緣保護層，各該第一絕緣保護層開孔外露部分該第一線路層。
  4. 如申請專利範圍第1項所述之半導體封裝件之製法，復包括於 該第二線路層與第二介電層上形成具有複數個第二絕緣保護層開孔的第二絕緣保護層，各該第二絕緣保護層開孔外露部分該第二線路層。
  5. 如申請專利範圍第1項所述之半導體封裝件之製法，其中，該電子元件係為被動元件。
  6. 如申請專利範圍第1項所述之半導體封裝件之製法，其中，該黏著件之材質係為導電膠。
  7. 如申請專利範圍第6項所述之半導體封裝件之製法，其中，該導電膠係為異方性導電膠。
  8. 如申請專利範圍第1項所述之半導體封裝件之製法，其中，該黏著件之材質係為不導電膠。
  9. 如申請專利範圍第1項所述之半導體封裝件之製法，復包括形成貫穿該第一介電層與第二介電層且電性連接該第一線路層與第二線路層的導電通孔。
  10. 一種半導體封裝件，係包括：第一介電層，係具有相對之第一表面與第二表面及貫穿該第一表面與第二表面之介電層開口；第一線路層，係嵌埋於該第一介電層中且外露於該第一表面；第二介電層，係形成於該第一介電層之第二表面上，並填入該介電層開口中；至少一黏著件，係形成於鄰近該第一表面之該介電層開口中的第二介電層中；電子元件，係設置於該介電層開口中的黏著件上； 複數個導電盲孔，係形成於該第二介電層中，且電性連接該電子元件；以及第二線路層，係形成於該第二介電層遠離該第一表面之表面上，且電性連接該導電盲孔。
  11. 如申請專利範圍第10項所述之半導體封裝件，其中，該黏著件係外露於該第一表面。
  12. 如申請專利範圍第10項所述之半導體封裝件，其中，該第一線路層復嵌埋並外露於該第二介電層鄰近該第一表面的表面，且該黏著件係形成於該第一線路層上。
  13. 如申請專利範圍第10項所述之半導體封裝件，復包括第一絕緣保護層，係形成於該第一線路層與第一介電層上，且具有複數個外露部分該第一線路層的第一絕緣保護層開孔。
  14. 如申請專利範圍第10項所述之半導體封裝件，復包括第二絕緣保護層，係形成於該第二線路層與第二介電層上，且具有複數個外露部分該第二線路層的第二絕緣保護層開孔。
  15. 如申請專利範圍第10項所述之半導體封裝件，其中，該電子元件係為被動元件。
  16. 如申請專利範圍第10項所述之半導體封裝件，其中，該黏著件之材質係為導電膠。
  17. 如申請專利範圍第16項所述之半導體封裝件，其中，該導電膠係為異方性導電膠。
  18. 如申請專利範圍第10項所述之半導體封裝件，其中，該黏著件之材質係為不導電膠。
  19. 如申請專利範圍第10項所述之半導體封裝件，復包括導電通 孔，係貫穿該第一介電層與第二介電層，且電性連接該第一線路層與第二線路層。
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TWI551207B (zh) * 2014-09-12 2016-09-21 矽品精密工業股份有限公司 基板結構及其製法
TWI614861B (zh) * 2015-01-30 2018-02-11 矽品精密工業股份有限公司 電子封裝結構及其製法
KR101762627B1 (ko) * 2015-11-17 2017-08-14 하나 마이크론(주) 반도체 패키지 및 그 제조 방법
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US6281450B1 (en) * 1997-06-26 2001-08-28 Hitachi Chemical Company, Ltd. Substrate for mounting semiconductor chips
US6285075B1 (en) * 1998-11-02 2001-09-04 Asat, Limited Integrated circuit package with bonding planes on a ceramic ring using an adhesive assembly
EP1990833A3 (en) * 2000-02-25 2010-09-29 Ibiden Co., Ltd. Multilayer printed circuit board and multilayer printed circuit board manufacturing method
CN101098588B (zh) * 2000-02-25 2011-01-26 揖斐电株式会社 多层印刷电路板
TWI407542B (zh) * 2008-06-19 2013-09-01 Unimicron Technology Corp 嵌埋半導體元件之電路板及其製法
US7842541B1 (en) * 2008-09-24 2010-11-30 Amkor Technology, Inc. Ultra thin package and fabrication method
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