TW201511146A - 半導體結構之製法 - Google Patents

半導體結構之製法 Download PDF

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Publication number
TW201511146A
TW201511146A TW102131767A TW102131767A TW201511146A TW 201511146 A TW201511146 A TW 201511146A TW 102131767 A TW102131767 A TW 102131767A TW 102131767 A TW102131767 A TW 102131767A TW 201511146 A TW201511146 A TW 201511146A
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Taiwan
Prior art keywords
interposer
semiconductor structure
semiconductor
bonding layer
fabricating
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TW102131767A
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English (en)
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TWI529825B (zh
Inventor
葉啓東
林畯棠
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矽品精密工業股份有限公司
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Priority to TW102131767A priority Critical patent/TWI529825B/zh
Priority to US14/074,165 priority patent/US9147668B2/en
Publication of TW201511146A publication Critical patent/TW201511146A/zh
Application granted granted Critical
Publication of TWI529825B publication Critical patent/TWI529825B/zh

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Abstract

一種半導體結構之製法，係先設置一中介板於一承載件上，該承載件具有本體與結合於該本體上之結合層，該中介板具有相對之第一側及第二側，且該第一側上具有複數導電元件，該中介板係以其第一側結合於該結合層上，以令該些導電元件僅嵌入該結合層中，之後結合半導體元件於該中介板上，令該半導體元件與該中介板形成為半導體結構。藉由將該些導電元件壓入該結合層中即可，而不需埋入該本體中，故無需於該本體上形成用以收納導電元件之凹部，因而本發明之製法能適用於不同產品規格之中介板。

Description

半導體結構之製法
本發明係有關一種半導體結構，尤指一種具中介板(interposer)之半導體結構之製法。
覆晶技術由於具有縮小晶片封裝面積及縮短訊號傳輸路徑等優點，目前已經廣泛應用於晶片封裝領域，例如晶片尺寸構裝(Chip Scale Package,CSP)、晶片直接貼附封裝(Direct Chip Attached,DCA)以及多晶片模組封裝(Multi -Chip Module,MCM)等型態的封裝模組，均可以利用覆晶技術而達到封裝的目的。
在覆晶封裝製程中，由於晶片與封裝基板之熱膨脹係數的差異甚大，因此晶片外圍的凸塊無法與封裝基板上對應的接點形成良好的接合，使得凸塊可能自封裝基板上剝離。另一方面，隨著積體電路之積集度的增加，由於晶片與封裝基板之間的熱膨脹係數不匹配(mismatch)，其所產生的熱應力(thermal stress)與翹曲(warpage)的現象也日漸嚴重，其結果將導致晶片與封裝基板之間的電性連接可靠度(reliability)下降，並且造成信賴性測試的失敗。
為了解決上述問題，習知提出了採用半導體基材製作中介板的製程，其中由於半導體基材與晶片的材質接近，因此可以有效避免熱膨脹係數不匹配所產生的問題，如第1A圖所示。
於第1A圖之習知半導體封裝件中，係於一封裝基板9與半導體晶片3之間增設一矽中介板(Through Silicon interposer,TSI)2，該矽中介板2具有基板單元20、導電矽穿孔(Through-silicon via,TSV)21及設於該導電矽穿孔21上之線路重佈結構(Redistribution layer,RDL)22，令該線路重佈結構22藉由複數導電元件23電性結合間距較大之封裝基板9之銲墊90，而間距較小之半導體晶片3之電極墊30係藉由複數銲錫凸塊31電性結合該導電矽穿孔21。之後，再形成底膠32包覆該銲錫凸塊31。其中該線路重佈結構(RDL)亦可是電性線路設計需要設置於矽中介板2欲以半導體晶片3之一側(如第1B圖所示之線路重佈結構22’)。
藉由該矽中介板2之設計，半導體封裝件除了避免前述問題外，相較於覆晶式封裝件，其長寬方向之面積可更加縮小。例如，一般覆晶式封裝基板最小之線寬/線距僅能製出12/12μm，而當半導體晶片之電極墊(I/O)數量增加時，以現有覆晶式封裝基板之線寬/線距並無法再縮小，故須加大覆晶式封裝基板之面積以提高佈線密度，才能接置高I/O數之半導體晶片。反觀第1A圖之半導體封裝件，因該矽中介板2可採用半導體製程做出3/3μm以下之線寬/ 線距，故當該半導體晶片3具高I/O數時，該矽中介板2之長寬方向之面積足以連接高I/O數之半導體晶片3，故不需增加該封裝基板9之面積，使該半導體晶片3經由該矽中介板2作為一轉接板而電性連接至該封裝基板9上。
再者，該矽中介板2之細線/寬線距特性而使電性傳輸距離短，故相較於直接覆晶結合至封裝基板之半導體晶片的電性傳輸速度(效率)，設於該矽中介板2上之半導體晶片3的電性傳輸速度(效率)更快(更高)。
目前製作半導體封裝件時，會先將該矽中介板2與該半導體晶片3結合成一半導體結構1，再將該半導體結構1設於該封裝基板9上。然而，因該矽中介板2係由複數基板單元20所組成之整版面，以於該半導體晶片3結合至各該基板單元20後，再經由切單製程形成複數半導體結構1，故當設置該半導體晶片3時容易發生翹曲，而造成該半導體晶片3與該矽中介板2間之電性連接不良。
為了克服上述翹曲之問題，業界遂開發出藉由具有凹部400之承載件4承載中介板之方式，如第1B圖所示。
於第1B圖之製法中，係先將一矽板40蝕刻出複數凹部400，再以旋塗方式將如黏著材之結合層41塗佈於該矽板40上(其中，黏著材可僅形成於該矽板40表面，亦可同時形成於該凹部400中)，使該矽中介板2平貼於該結合層41上，且該矽中介板2之導電元件23收納於該凹部400中，以當該半導體晶片3接置於該矽中介板2之基板單元20時，藉由該結合層41可避免該矽中介板2產生翹 曲，並可防止該半導體晶片3接置時破裂、或該銲錫凸塊31無法全面接置於該矽中介板2上而造成電性連接不良之問題。
惟，前述習知半導體結構1之製法中，該矽中介板2於不同產品規格(如導電元件23之數量不同、各導電元件23間之距離不同)時需製作不同之矽板40，以形成不同尺寸與數量之凹部400，將增加半導體封裝件之生產成本。
再者，製作該些凹部400時，需藉由形成圖案化光阻於該矽板40上，由於光阻之材料相當昂貴，若需製作不同之矽板40，將使用大量之光阻材，亦將增加半導體封裝件之生產成本。
因此，如何克服上述習知技術的種種問題，實已成目前亟欲解決的課題。
鑑於上述習知技術之種種缺失，本發明係提供一種半導體結構之製法，係包括：設置一中介板於一承載件上，其中，該承載件具有本體與結合於該本體上之結合層，該中介板則具有相對之第一側及第二側，且該第一側上具有複數導電元件，俾供該中介板以其第一側結合於該結合層上後，令該些導電元件僅嵌入該結合層中；以及結合半導體元件於該中介板之第二側上，以由該半導體元件與該中介板形成為該半導體結構。
前述之製法中，該中介板係為含矽之板體。例如，該中介板具有複數連通該第一側與第二側之導電穿孔，且該 些導電穿孔係電性連接該導電元件；或者，該中介板之第一側或第二側具有線路重佈結構，且該線路重佈結構係電性連接該些導電穿孔與該些導電元件。
前述之製法中，該導電元件之材質係含有銲錫材料。
前述之製法中，該承載件具有結合於該本體與該結合層之間的離型層，可藉移除該離型層，使該半導體結構及其上之結合層一併由該本體上分離。例如，該中介板具有複數基板單元，以於移除該離型層前進行該中介板之切單製程，而於移除該離型層後，再移除該半導體結構上之結合層，以獲得複數該半導體結構；或者，於移除該離型層後，移除該半導體結構上之結合層，以露出該些導電元件；亦可移除該離型層時，僅移除對應於該中介板處之該離型層，再切割該結合層，使該半導體結構及其上之結合層一併由該本體上分離。
前述移除該離型層之方式係為雷射方式。例如，該雷射方式之雷射光係穿透該本體而移除該離型層；或者，該雷射方式之雷射光係移除對應於該中介板處之該離型層。
另外，前述之製法中，復包括移除該結合層，以分離該本體與該半導體結構。
由上可知，本發明之半導體結構之製法係只需將該中介板之導電元件壓入該結合層中即可，而不需埋入該本體中，故無需於該本體上形成如習知凹部，因而能適用於不同產品規格之中介板，以節省製作半導體封裝件之材料成本及時間。
再者，因無需於該本體上製作凹部時，故無需使用光阻材料，因而能節省製作半導體封裝件之材料成本及時間。
1,7‧‧‧半導體結構
2‧‧‧矽中介板
20,50‧‧‧基板單元
21‧‧‧導電矽穿孔
22,22’,52‧‧‧線路重佈結構
23,53‧‧‧導電元件
3‧‧‧半導體晶片
30‧‧‧電極墊
31,61‧‧‧銲錫凸塊
32,62‧‧‧底膠
4,8‧‧‧承載件
40‧‧‧矽板
400‧‧‧凹部
41,81,81’‧‧‧結合層
5‧‧‧中介板
5a‧‧‧第一側
5b‧‧‧第二側
51‧‧‧導電穿孔
6‧‧‧半導體元件
8’‧‧‧支撐件
80‧‧‧本體
82‧‧‧離型層
9‧‧‧封裝基板
90‧‧‧銲墊
L,S‧‧‧切割路徑
第1A圖係為習知半導體封裝件之剖面示意圖；第1B圖係為習知半導體結構之製法之剖面示意圖；以及第2A至2F圖係本發明之半導體結構之製法的剖面示意圖。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”、“第一”、“第二”及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
第2A至2F圖係為本發明之半導體結構7之製法的剖 面示意圖。
如第2A圖所示，提供一承載件8，該承載件8具有本體80、結合於該本體80上之離型層82與結合於該離型層82上之結合層81。
於本實施例中，該本體係為透光板，如玻璃，且形成該結合層81之材質係為膠材。
再者，該離型層82係為碳化層並以濺鍍方式形成之，且不具黏性。
如第2B圖所示，設置一中介板5於該結合層81上，該中介板5具有相對之第一側5a及第二側5b，且該第一側5a上具有複數導電元件53，該些導電元件53係壓入該結合層81中。
於本實施例中，該中介板5為含矽之板體並具有複數基板單元50。具體地，該中介板5具有複數連通該第一側5a與第二側5b之導電穿孔51，且該些導電穿孔51係電性連接該導電元件53，又於該中介板5之第一側5a或第二側5b可依需求形成一線路重佈結構52，該線路重佈結構係電性連接該些導電穿孔51與該些導電元件53。
再者，該導電元件53之材質係含有銲錫材料，且該導電元件之種類繁多，例如，金屬凸塊、金屬柱、針狀體、球體等，並無特別限制。
如第2C圖所示，結合複數半導體元件6於該中介板5之第二側5b上，令該半導體元件6與該中介板5作為半導體結構7。
於本實施例中，該些半導體元件6係為半導體晶片，且設於該基板單元50上，並藉由複數銲錫凸塊61電性連接該線路重佈結構52與該些導電穿孔51。
再者，藉由液態封裝製程(liquid encapsulation process)，如形成底膠62於該中介板5之第二側5b上，以包覆該些銲錫凸塊61。
如第2D圖所示，沿如第2C圖所示之切割路經S進行切單製程，以形成複數半導體結構7，再結合一支撐件8’於各該半導體結構7之半導體元件6上。
於本實施例中，該支撐件8’係為貼合材以黏貼各該半導體元件6。
如第2E圖所示，移除該離型層82，使該些半導體結構7及其上之結合層81’與支撐件8’一併由該本體80上分離。
於本實施例中，移除該離型層82之方式係為雷射方式。具體地，該雷射方式之雷射光係穿透該本體80而移除該離型層82，較佳地，該雷射方式之雷射光係僅移除對應該中介板5處之該離型層82，再沿如第2E圖所示之切割路徑L以雷射切割該結合層81。
再者，若該承載件8未形成該該離型層82，於移除該本體80時，需用溶劑清除該結合層81，以分離該本體80與該半導體結構7，但因溶劑無法完全滲入該結合層81之中心處，故會導致該本體80與該半導體結構7無法完全分離。因此，本發明之較佳製法係藉由形成該離型層82於該 結合層81與該本體80之間，以先藉由雷射照射燒除該離型層82而分離該本體80與該結合層81，之後再清除該半導體結構7上之結合層81’。
如第2F圖所示，用溶劑移除該結合層81’，以露出該些導電元件53。於後續製程中，可由該支撐件8’上拿取該半導體結構7，將該半導體結構7設於一封裝基板(圖略)上，以製成半導體封裝件。
本發明之製法中，係將該中介板5之導電元件53壓入該結合層81中，故僅需塗佈該結合層81於該本體80上，而無需於該本體80上形成如習知凹部，因而能適用於不同產品規格之中介板5，以節省製作半導體封裝件之材料成本及時間。
再者，因無需於該本體80上製作凹部時，故無需使用光阻材料，因而能節省製作半導體封裝件之材料成本及時間。
又，藉由該離型層82之設計，能先移除該離型層82而分離該本體80與該結合層81，再清除該結合層81’，藉以確保該本體80與該半導體結構7能有效分離。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
5‧‧‧中介板
53‧‧‧導電元件
6‧‧‧半導體元件
7‧‧‧半導體結構
8‧‧‧承載件
8’‧‧‧支撐件
80‧‧‧本體
81,81’‧‧‧結合層
82‧‧‧離型層
L‧‧‧切割路徑

Claims (14)

  1. 一種半導體結構之製法，係包括：設置一中介板於一承載件上，其中，該承載件具有本體與結合於該本體上之結合層，該中介板則具有相對之第一側及第二側，且該第一側上具有複數導電元件，俾供該中介板以其第一側結合於該結合層上後，令該些導電元件僅嵌入該結合層中；以及結合半導體元件於該中介板之第二側上，以由該半導體元件與該中介板形成為該半導體結構。
  2. 如申請專利範圍第1項所述之半導體結構之製法，其中，該中介板係為含矽之板體。
  3. 如申請專利範圍第1項所述之半導體結構之製法，其中，該中介板具有複數連通該第一側與第二側之導電穿孔，且該些導電穿孔係電性連接該導電元件。
  4. 如申請專利範圍第3項所述之半導體結構之製法，其中，該中介板之第一側或第二側具有線路重佈結構，且該線路重佈結構係電性連接該些導電穿孔與該些導電元件。
  5. 如申請專利範圍第1項所述之半導體結構之製法，其中，該導電元件之材質係含有銲錫材料。
  6. 如申請專利範圍第1項所述之半導體結構之製法，其中，該承載件具有結合於該本體與該結合層之間的離型層。
  7. 如申請專利範圍第6項所述之半導體結構之製法，復 包括移除該離型層，使該半導體結構及其上之結合層一併由該本體上分離。
  8. 如申請專利範圍第7項所述之半導體結構之製法，其中，該中介板具有複數基板單元，以於移除該離型層前，進行該中介板之切單製程，而於移除該離型層後，再移除該半導體結構上之結合層，以獲得複數該半導體結構。
  9. 如申請專利範圍第7項所述之半導體結構之製法，復包括於移除該離型層後，移除該半導體結構上之結合層，以露出該些導電元件。
  10. 如申請專利範圍第7項所述之半導體結構之製法，其中，移除該離型層時，僅移除對應於該中介板處之該離型層，再切割該結合層，使該半導體結構及其上之結合層一併由該本體上分離。
  11. 如申請專利範圍第7項所述之半導體結構之製法，其中，移除該離型層之方式係為雷射方式。
  12. 如申請專利範圍第11項所述之半導體結構之製法，其中，該雷射方式之雷射光係穿透該本體而移除該離型層。
  13. 如申請專利範圍第11項所述之半導體結構之製法，其中，該雷射方式之雷射光係移除對應於該中介板處之該離型層。
  14. 如申請專利範圍第1項所述之半導體結構之製法，復包括移除該結合層，以分離該本體與該半導體結構。
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