TW201448050A - 半導體裝置的製造方法 - Google Patents

半導體裝置的製造方法 Download PDF

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TW201448050A
TW201448050A TW103102476A TW103102476A TW201448050A TW 201448050 A TW201448050 A TW 201448050A TW 103102476 A TW103102476 A TW 103102476A TW 103102476 A TW103102476 A TW 103102476A TW 201448050 A TW201448050 A TW 201448050A
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layer
trench
source
region
semiconductor
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TW103102476A
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TWI534910B (zh
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Shoji Mizuno
Katsumi Suzuki
Sachiko Aoi
Yukihiko Watanabe
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Denso Corp
Toyota Motor Co Ltd
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Abstract

半導體裝置的製造方法包括：將第一溝渠形成在漂移層的第一區中，該漂移層具有包括第一區和第二區之表面；在形成該第一溝渠之後，將p型基極層的晶體生長在該漂移層之表面上；以及將n型源極層的晶體生長在該基極層之表面上。該漂移層、該基極層、及該源極層的材料為寬能隙半導體。

Description

半導體裝置的製造方法
本說明書所揭示的技術係相關於使用寬能隙半導體做為材料來製造半導體裝置之方法。
已知諸如碳化矽及氮化鎵等寬能隙半導體做為實現能夠以低耗損在高溫中穩定操作之半導體裝置的材料。然而，使用寬能隙半導體做為材料之半導體裝置具有難以藉由使用離子植入引進高濃度摻雜劑的問題。因此，在日本專利申請案出版號碼2008-118011及日本專利申請案出版號碼2010-258387中，揭示藉由晶體生長來形成p型基極層和n型源極層的技術。
本說明書的目的在於提供使用寬能隙半導體做為材料來製造半導體裝置之方法。
本說明書所揭示之半導體裝置的製造方法包括：將第一溝渠形成在半導體層中，其中，半導體層具有包括第一 區和第二區之表面，及第一溝渠係形成在半導體層的表面之第一區中；在形成第一溝渠之後，將第一導電型之基極層的晶體生長在半導體層之表面上；以及將第二導電型之源極層的晶體生長在基極層之表面上。半導體層、基極層、及源極層的材料為寬能隙半導體。在說明書中，“半導體層、基極層、及源極層的材料為寬能隙半導體”的詞句包括使用相同類型的寬能隙半導體做為材料之組態、及使用不同類型的寬能隙半導體做為材料之組態。本說明書所揭示之製造方法具有特徵如下：在生長基極及源極層的晶體之前，將第一溝渠形成在半導體層的表面之第一區中。藉由形成第一溝渠，可製造使用寬能隙半導體做為材料之有用的半導體裝置。
1A‧‧‧第一區
2A‧‧‧第二區
10‧‧‧基板
11‧‧‧漂移層
11a‧‧‧表面
12‧‧‧基極層
13‧‧‧源極層
21‧‧‧第一溝渠
21a‧‧‧溝渠
22‧‧‧第二溝渠
23‧‧‧第三溝渠
30‧‧‧絕緣溝渠閘極
31‧‧‧溝渠閘極電極
32‧‧‧閘極絕緣膜
33‧‧‧源極電極
40‧‧‧遮罩層
112‧‧‧基極層
113‧‧‧源極層
121‧‧‧第一溝渠
121a‧‧‧溝渠
122‧‧‧第二溝渠
123‧‧‧第三溝渠
130‧‧‧絕緣溝渠閘極
131‧‧‧溝渠閘極電極
132‧‧‧閘極絕緣膜
133‧‧‧源極電極
230‧‧‧絕緣溝渠閘極
231‧‧‧溝渠閘極電極
231A‧‧‧深度
232‧‧‧閘極絕緣膜
233‧‧‧源極電極
330‧‧‧絕緣溝渠閘極
331‧‧‧溝渠閘極電極
332‧‧‧閘極絕緣膜
333‧‧‧源極電極
430‧‧‧絕緣平面閘極
431‧‧‧平面閘極電極
432‧‧‧閘極絕緣膜
圖1為根據第一實施例之半導體裝置的一製造處理之主要部分的概要橫剖面圖。
圖2為根據第一實施例之半導體裝置的一製造處理之主要部分的概要橫剖面圖。
圖3為根據第一實施例之半導體裝置的一製造處理之主要部分的概要橫剖面圖。
圖4為根據第一實施例之半導體裝置的一製造處理之主要部分的概要橫剖面圖。
圖5為根據第一實施例之半導體裝置的一製造處理之主要部分的概要橫剖面圖。
圖6為根據第一實施例之半導體裝置的一製造處理之主要部分的概要橫剖面圖。
圖7為根據第一實施例之半導體裝置的一製造處理之主要部分的概要橫剖面圖。
圖8為根據第一實施例的修改之半導體裝置的一製造處理之主要部分的概要橫剖面圖。
圖9為根據第一實施例的修改之半導體裝置的一製造處理之主要部分的概要橫剖面圖。
圖10為根據第一實施例的修改之半導體裝置的一製造處理之主要部分的概要橫剖面圖。
圖11為根據第一實施例的修改之半導體裝置的一製造處理之主要部分的概要橫剖面圖。
圖12為根據第一實施例的修改之半導體裝置的一製造處理之主要部分的概要橫剖面圖。
圖13為根據第一實施例的修改之半導體裝置的一製造處理之主要部分的概要橫剖面圖。
圖14為根據第一實施例的修改之半導體裝置的一製造處理之主要部分的概要橫剖面圖。
圖15為根據第一實施例的修改之半導體裝置的一製造處理之主要部分的概要橫剖面圖。
圖16為根據第二實施例之半導體裝置的一製造處理之主要部分的概要橫剖面圖。
圖17為根據第二實施例之半導體裝置的一製造處理之主要部分的概要橫剖面圖。
圖18為根據第二實施例之半導體裝置的一製造處理之主要部分的概要橫剖面圖。
圖19為根據第二實施例之半導體裝置的一製造處理之主要部分的概要橫剖面圖。
圖20為在根據第二實施例之半導體裝置中容易製造溝渠閘極的有利點之說明圖。
圖21為根據第二實施例的修改之半導體裝置的一製造處理之主要部分的概要橫剖面圖。
圖22為根據第二實施例的修改之半導體裝置的一製造處理之主要部分的概要橫剖面圖。
圖23為根據第二實施例的修改之半導體裝置的一製造處理之主要部分的概要橫剖面圖。
圖24為根據第二實施例的修改之半導體裝置的一製造處理之主要部分的概要橫剖面圖。
圖25為根據第三實施例之半導體裝置的一製造處理之主要部分的概要橫剖面圖。
圖26為根據第三實施例之半導體裝置的一製造處理之主要部分的概要橫剖面圖。
圖27為根據第三實施例之半導體裝置的一製造處理之主要部分的概要橫剖面圖。
圖28為根據第三實施例之半導體裝置的一製造處理之主要部分的概要橫剖面圖。
下面概述本說明書所揭示之技術的一些有利點。下面所說明之主題具有獨立的技術有用性。
(特徵1)本說明書所揭示的一製造方法係用於製造使用寬能隙半導體做為半導體材料之半導體裝置。寬能隙半導體為具有能帶隙大於矽的能帶隙之半導體，及例子為碳化矽、氮化鎵、及金剛鑽。有關半導體裝置，例如使用MOSFET(金氧半導體場效電晶體)或IGBT(絕緣閘雙極電晶體)。
(特徵2)本說明書所揭示之半導體裝置的製造方法包括將第一溝渠形成在具有包括第一區和第二區之表面的半導體層之處理。第一溝渠係形成在半導體層的表面之第一區中。方法另包括將第一導電型之基極層的晶體生長在半導體層之表面上的處理，及將第二導電型之源極層的晶體生長在基極層之表面上的處理。在說明書中，“將組件生長在另一組件上”的詞句包括將組件直接形成在另一組件上之組態，以及將組件形成在另一組件上方且具有另一組件插入在其間之組態。相同解釋應用到“留下存在於另一組件上之組件”、“將組件形成在另一組件上”、及“存在於另一組件上的組件”。在生長基極層的晶體之前可形成另一層，及可將另一層形成在基極層與源極層之間。除了第一區和第二區之外，半導體層的表面還可具有另一區。例如，半導體層的表面可在對應於半導體裝置的元件區之位置中具有第一區和第二區，及在對應於半導體層的終端區之位置中具有其他區。基極層亦被稱作本體層。源極層亦被稱作射極層。
(特徵3)本說明書所揭示之半導體裝置的製造方法之一例子可另包括藉由貫穿存在於半導體層的表面之第二區上的源極和基極層之至少一部分以露出半導體層來形成第二溝渠的處理，以及將絕緣溝渠閘極形成在第二溝渠之處理。根據此製造方法，因為半導體裝置達成具有深基極層係配置在絕緣溝渠閘極的組態，所以可獲得高壓半導體裝置。
(特徵4)根據特徵3之製造方法可另包括在形成第二溝渠之前將遮罩層形成在源極層的表面上之處理，以及藉由從遮罩層的表面蝕刻預定厚度來選擇性留下存在於半導體層的表面之第一區上的遮罩層之處理。在此事例中，在形成第二溝渠的處理中，第二溝渠係藉由使用遮罩層做為遮罩來形成。根據此製造方法，可藉由使用反映第一溝渠的組態之溝渠來選擇性圖案化遮罩層。因此，根據此製造方法，因為不需要圖案化遮罩層的光遮罩，所以可以低成本製造半導體裝置。
(特徵5)根據特徵3或4之製造方法可另包括藉由蝕刻存在於半導體層的表面之第一區上的源極層之至少一部分來露出基極層的處理，以及形成與露出的基極層相接觸之源極電極的處理。
(特徵6)本說明書所揭示之半導體裝置的製造方法之一例子可另包括藉由貫穿存在於半導體層的表面之第一區上的源極和基極層之至少一部分以露出半導體層來形成第三溝渠的處理，以及將絕緣溝渠閘極形成在第三溝渠之處理。
(特徵7)在根據特徵6之製造方法中，在形成第三溝渠 的處理中，第三溝渠可被形成，以便留下沿著存在於第三溝渠的側表面上之深度方向延伸的源極層。根據此製造方法，因為源極層被形成直至沿著絕緣溝渠閘極的側表面之深位置，所以可抑制形成絕緣溝渠閘極時之溝渠閘極電極的蝕刻量變化之影響。
(特徵8)在根據特徵6之製造方法中，在形成第三溝渠的處理中，第三溝渠可被形成，以便未留下沿著存在於第三溝渠的側表面上之深度方向延伸的源極層。根據此製造方法，因為基極層被形成直至沿著絕緣溝渠閘極的側表面之深位置，所以可抑制鎖定。
(特徵9)根據特徵6至8的任一個之製造方法可另包括藉由蝕刻存在於半導體層的表面之第二區上的源極層之至少一部分來露出基極層的處理，以及形成與露出的基極層相接觸之源極電極的處理。
(特徵10)本說明書所揭示之半導體裝置的製造方法之一例子可另包括藉由從源極層的表面蝕刻預定厚度來選擇性留下存在於半導體層的表面之第一區上的源極和基極層之處理，以及形成面向被留下存在於半導體層的第一區上之基極層的絕緣平面閘極之處理。根據此製造方法，可製造平面型的半導體裝置。
現在將參考附圖更進一步詳細說明本發明之代表性且非限制性的例子。此詳細說明僅用於教導精於本技藝之人士用以實施本教學的較佳態樣之更多的細節，並不用於限制本發明的範疇。而且，可將下面所揭示之額外特徵及教 學的每一個分開或連同其他特徵及教學來加以利用，以提供改良的半導體裝置以及半導體裝置製造方法。
而且，以最廣義而言，實施本發明可不需要下面詳細說明所揭示之特徵和步驟的組合，取而代之的是，僅被教示用於特別說明本發明的代表性例子。而且，可以非具體和明確列舉的方式來組合上述及下述的代表性例子之各種特徵與各種獨立項和非獨立項申請專利範圍，以便提供本教示之額外有用的實施例。
本說明書及/或申請專利範圍所揭示之所有特徵欲用於為了原有所寫的揭示與為了限制所請的標的而彼此分開及獨立揭示，不受實施例及/或申請專利範圍中的特徵之組成限制。此外，為了說明書中的說明及為了限制所請的標的，所有值範圍或實體的群組之指示為了揭示每一可能的中間值或中間實體。
在下文中，參考圖式說明MOSFET的製造方法。共同的參考符號被附加到各個實施例所共有之組態元件，及共有的組態元件之說明被適當省略。
(第一實施例)
根據第一實施例之MOSFET的製造方法，首先，如圖1所示，備製藉由堆疊n+型基板10和n型漂移層11所形成之半導體層。基板10為具有平面取向(0001)的碳化矽基板。碳化矽的漂移層11係藉由使用磊晶生長技術從基板11生長晶體所形成。漂移層11的表面11a包括第一區1A和第二區2A。
如圖2所示，藉由使用蝕刻技術將第一溝渠21形成在漂移層11的表面11a之第一區1A中。第一溝渠21在漂移層11的表面層中具有預定深度。
接著，如圖3所示，藉由使用磊晶生長技術將碳化矽的p型基極層12和碳化矽的n+型源極層13之晶體生長在漂移層11的表面11a上。在磊晶生長基極層12之前，具有雜質濃度高於漂移層11的雜質濃度之n型電流散佈層係可磊晶生長在漂移層11與基極層12之間。基極層12和源極層13覆蓋漂移層11的表面11a之第一區1A和第二區2A二者。尤其是，基極層12和源極層13係形成在漂移層11的表面11a之第一區1A中的第一溝渠21，及依據第一溝渠21的組態而具有沿著深度方向延伸的部位。反映第一溝渠21的組態之溝渠21a係形成在對應於漂移層11的第一區1A之區域中。
接著，如圖4所示，藉由蝕刻技術，到達漂移層11之第二溝渠22係藉由貫穿存在於漂移層11的表面11a之第二區2A上的基極層12和源極層13之一部分所形成。第二溝渠22被形成淺於第一溝渠21。因此，第二溝渠22的底表面淺於形成在第一溝渠21中之基極層12的位置。
接著，如圖5所示，絕緣溝渠閘極30係形成在第二溝渠22中。尤其是，在藉由使用熱氧化技術將氧化矽的閘極絕緣膜32形成在第二溝渠22的內壁之後，藉由使用汽相沉積技術將多晶矽的溝渠閘極電極31充填在第二溝渠22中。
接著，如圖6所示，藉由使用蝕刻技術，將存在於漂移層11之表面11a的第一區1A上之源極層13的一部分移 除，及露出基極層12。在存在於漂移層11的表面11a之第一區1A上的源極層13之本例中，沿著深度方向延伸的所有部位被移除。
接著，如圖7所示，與源極層13和基極層12歐姆接觸之源極電極33係藉由汽相沉積技術所形成。在一例子中，源極電極33的材料為鎳或矽化鎳。
最後，將汲極電極(未圖示)形成在基板10的背表面上，及完成MOSFET。以此方式，根據上述製造方法，可製造使用碳化矽做為材料之MOSFET，卻不必過度依賴離子植入技術。另外，由上述製造方法所製造之MOSFET具有特徵如下：MOSFET具有在漂移層11的表面層部分中沿著側向方向交替配置漂移層11和基極層12之組態。因此，當MOSFET關閉時，藉由從基極層12延伸到側向方向之空乏層，漂移層11的表面部分令人滿意地被空乏，及介電強度提高。尤其是，因為基極層12被設置成深於絕緣溝渠閘極30，所以絕緣溝渠閘極30的底部中之電場濃度被減輕，及可抑制絕緣溝渠閘極30的閘極絕緣膜32之破壞。
(修改)
下面說明根據第一實施例之MOSFET的製造方法之修改。如圖8所示，在備製藉由堆疊n+型基板10和n型漂移層11所形成的半導體層之後，第一溝渠121係形成在漂移層11的表面11a之第一區1A中。第一溝渠121在漂移層11的表面層中具有預定深度。
接著，如圖9所示，藉由使用磊晶生長技術將碳化矽的p型基極層112和碳化矽的n+型源極層113之晶體生長在漂移層11的表面11a上。在磊晶生長基極層112之前，具有雜質濃度高於漂移層11的雜質濃度之n型電流散佈層係可磊晶生長在漂移層11與基極層112之間。基極層112和源極層113覆蓋漂移層11的表面11a之第一區1A和第二區2A二者。尤其是，基極層112和源極層113係形成在漂移層11的表面11a之第一區1A中的第一溝渠121，及依據第一溝渠121的組態而具有沿著深度方向延伸的部位。反映第一溝渠121的組態之溝渠121a係形成在對應於漂移層11的第一區1A之區域中。
接著，如圖10所示，藉由使用CVD技術將遮罩層40形成在源極層113的表面上。遮罩層40係充填在反映第一溝渠121的組態之溝渠121a中。在一例子中，遮罩層40的材料為氧化矽。
接著，如圖11所示，藉由使用蝕刻技術，藉由預定厚度從表面移除遮罩層40的頂部。尤其是，藉由使用乾蝕刻技術，遮罩層40被移除直到露出存在於漂移層11的表面11a之第二區2A上的源極層113為止。以此方式，藉由將第一溝渠121形成在漂移層11中，可選擇性將遮罩層40留在反映第一溝渠121的組態之溝渠121a中。
接著，如圖12所示，藉由使用遮罩層40做為遮罩來形成第二溝渠122，及露出漂移層11。在形成第二溝渠122之後，移除遮罩層40。
接著，如圖13所示，絕緣溝渠閘極130係形成在第二溝渠122中。尤其是，在藉由使用熱氧化技術或CVD技術將氧化矽的閘極絕緣膜132形成在第二溝渠122的內壁上之後，藉由使用汽相沉積技術將多晶矽的溝渠閘極電極131充填在第二溝渠122中。
接著，如圖14所示，藉由使用蝕刻技術，存在於漂移層11之表面的第一區1A上之源極層113的一部分被蝕刻，及露出基極層112。
接著，如圖15所示，藉由使用汽相沉積技術，形成與源極層113和基極層112歐姆接觸之源極電極133。在一例子中，源極電極133的材料為鎳或矽化鎳。
最後，將汲極電極(未圖示)形成在基板10的背表面上，及完成MOSFET。根據上述修改中的製造方法，可製造使用碳化矽做為材料之MOSFET，卻不必一定要使用離子植入技術。根據上述修改中的製造方法，藉由使用反映第一溝渠121的組態之溝渠121a(見圖11)，可選擇性圖案化遮罩層40。因此，在本製造方法中，因為不一定要圖案化遮罩層40的光遮罩，所以可以低成本製造MOSFET。
(第二實施例)
第二實施例中之MOSFET的製造方法同於第一實施例中之MOSFET的製造方法，直至將基極層12和源極層13形成在漂移層11的表面11a上(見圖1至3)。
接著，如圖16所示，藉由使用蝕刻技術，到達漂移層 11之第三溝渠23係藉由貫穿位在漂移層11之表面11a的第一區1A中之基極層12和源極層13的一部分所形成。第三溝渠23被形成，使得沿著深度方向延伸之源極層13被留下存在於第三溝渠23的側表面上。即、第三溝渠23被形成，使得形成在第一溝渠21中之源極層13的底表面之一部分被留下存在著。
接著，如圖17所示，絕緣溝渠閘極230係形成在第三溝渠23中。尤其是，在藉由使用熱氧化技術將氧化矽的閘極絕緣膜232形成在第三溝渠23的內壁上之後，藉由使用汽相沉積技術將多晶矽的溝渠閘極電極231充填在第三溝渠23中。
接著，如圖18所示，藉由使用蝕刻技術，存在於漂移層11之表面11a的第二區2A上之源極層13的一部分被蝕刻，及露出基極層12。
接著，如圖19所示，藉由使用汽相沉積技術，形成與源極層13和基極層12歐姆接觸之源極電極233。在一例子中，源極電極233的材料為鎳或矽化鎳。
最後，將汲極電極(未圖示)形成在基板10的背表面上，及完成MOSFET。根據上述製造方法，可製造使用碳化矽做為材料之MOSFET，卻不必一定要使用離子植入技術。根據藉由上述製造方法所製造之MOSFET，源極層13係存在直至第三溝渠23的側表面之深位置。如圖20所示，為了將溝渠閘極電極231選擇性充填在第三溝渠23中，沉積在除了第三溝渠23以外的其他位置之溝渠閘極電極231必 須被蝕刻。為了蝕刻多晶矽的溝渠閘極電極231，例如，使用氯氣。然而，因為多晶矽的蝕刻率高，所以第三溝渠23中之溝渠閘極電極231被蝕刻的深度231A之變化大。根據上述製造方法所製造之MOSFET，因為源極層13係存在直至第三溝渠23的側表面之深位置，所以可抑制蝕刻第三溝渠23中之溝渠閘極電極231的深度231A之變化的影響。
(修改)
下面說明根據第二實施例之MOSFET的製造方法之修改。如圖21所示，藉由使用蝕刻技術，到達漂移層11之第三溝渠123係藉由貫穿位在漂移層11的表面11a之第一區1A上的基極層12和源極層13之一部分所形成。第三溝渠123被形成，使得沿著深度方向延伸之源極層13未被留下存在於第三溝渠123的側表面上。即、第三溝渠123被形成，使得形成在第一溝渠21中之源極層13的底表面未被留下。
接著，如圖22所示，將絕緣溝渠閘極330形成在第三溝渠123中。尤其是，在藉由使用熱氧化技術將氧化矽的閘極絕緣膜332形成在第三溝渠123的內壁上之後，藉由使用汽相沉積技術將多晶矽的溝渠閘極電極331充填在第三溝渠123中。
接著，如圖23所示，藉由使用蝕刻技術，存在於漂移層11之表面11a的第二區2A上之源極層13的一部分被蝕刻，及露出基極層12。
接著，如圖24所示，藉由使用汽相沉積技術，形成與 源極層13和基極層12歐姆接觸之源極電極333。在一例子中，源極電極333的材料為鎳或矽化鎳。
最後，將汲極電極(未圖示)形成在基板10的背表面上，及完成MOSFET。根據上述修改中的製造方法，可製造使用碳化矽做為材料之MOSFET，卻不必一定要使用離子植入技術。另外，根據藉由上述修改中之製造方法所製造的MOSFET，因為基極層12係存在直至第三溝渠123的側表面之位置，所以抑制鎖定的效果高。
(第三實施例)
第三實施例中之MOSFET的製造方法同於第一實施例中之MOSFET的製造方法，直至將基極層12和源極層13形成在漂移層11的表面11a上(見圖1至3)。
接著，如圖25所示，藉由使用蝕刻技術，從表面藉由預定厚度蝕刻源極層13。尤其是，藉由使用氯做為材料之乾蝕刻技術，源極層13、基極層12、及漂移層11被移除，直到源極層13和基極層12被選擇性留下存在於漂移層11的表面11a之第一區1A上。
接著，如圖26所示，在露出源極層13的一部分之狀態中形成與源極層13、基極層12、及漂移層11相對之絕緣平面閘極430。尤其是，在藉由使用熱氧化技術將氧化矽的閘極絕緣膜432形成在源極層13、基極層12、及漂移層11的表面上之後，藉由使用汽相沉積技術將多晶矽的平面閘極電極431形成在閘極絕緣膜432上。
接著，如圖27所示，藉由使用蝕刻技術，存在於漂移層11之表面11a的第一區1A上之源極層13的一部分被蝕刻，及露出基極層12。
接著，如圖28所示，藉由使用汽相沉積技術，形成與源極層13和基極層12歐姆接觸之源極電極433。在一例子中，源極電極433的材料為鎳或矽化鎳。
接著，將汲極電極(未圖示)形成在基板10的背表面上，及完成MOSFET。根據上述製造方法，可製造使用碳化矽做為材料之MOSFET，卻不必一定要使用離子植入技術。另外，根據上述製造方法所製造之MOSFET，可容易製造包括絕緣平面閘極430之MOSFET。
儘管上面詳細說明本發明的具體例子，但是這些僅是例示，並不限制申請專利範圍的範疇。申請專利範圍所說明之技術包括上述例示化具體例子的各種修改和變更。
例如，在上述實施例中，雖然說明將第一溝渠21及121形成在MOSFET的元件區之漂移層11及121的例子，但是可將第一溝渠21及121形成在MOSFET的終端區。在此事例中，藉由將基極層12及112充填在形成於終端區之第一溝渠21及121中，可使用充填結果做為防護環。可簡化將防護環形成在終端區之處理。
另外，為了提高源極電極的歐姆特性，藉由使用離子植入技術可添加產生高濃度區之處理。
本說明書或圖式所說明之技術元件獨立或以各種組合來展現出技術實用性，及並不侷限於申請時申請專利範圍 中所說明的組合。另外，本說明書或圖式所說明之技術可同時達成複數個目的，及藉由達成目的的其中之一，自行具有技術實用性。
1A‧‧‧第一區
2A‧‧‧第二區
10‧‧‧基板
11‧‧‧漂移層
11a‧‧‧表面
12‧‧‧基極層
13‧‧‧源極層
21‧‧‧第一溝渠
22‧‧‧第二溝渠
30‧‧‧絕緣溝渠閘極
31‧‧‧溝渠閘極電極
32‧‧‧閘極絕緣膜
33‧‧‧源極電極

Claims (12)

  1. 一種半導體裝置的製造方法，該方法包含：將第一溝渠形成在半導體層中，其中，該半導體層具有包括第一區和第二區之表面，及該第一溝渠係形成在該第一區中；在形成該第一溝渠之後，將第一導電型之基極層的晶體生長在該半導體層的該表面上，以及將第二導電型之源極層的晶體生長該基極層的表面上，其中，該半導體層、該基極層、及該源極層的材料為寬能隙半導體。
  2. 根據申請專利範圍第1項之方法，另包含：形成第二溝渠，該第二溝渠貫穿存在於該半導體層之該表面的該第二區上之該源極和基極層的至少一部分，使得在該第二溝渠露出該半導體層，以及將絕緣溝渠閘極形成在該第二溝渠中。
  3. 根據申請專利範圍第2項之方法，另包含：在形成該第二溝渠之前，將遮罩層形成在該源極層的表面上；以及藉由從該遮罩層的表面蝕刻預定厚度，以選擇性留下存在於該半導體層的該表面之該第一區上的該遮罩層，其中，在形成該第二溝渠時，該第二溝渠係藉由使用該遮罩層做為遮罩所形成。
  4. 根據申請專利範圍第2項或第3項之方法，另包 含：藉由蝕刻存在於該半導體層之該表面的該第一區上之該源極層的至少一部分，以露出該基極層；以及形成接觸該露出的基極層之源極電極。
  5. 根據申請專利範圍第1項之方法，另包含：形成第三溝渠，該第三溝渠貫穿存在於該半導體層之該表面的該第一區上之該源極和基極層的至少一部分，使得在該第三溝渠露出該半導體層；以及將絕緣溝渠閘極形成在該第三溝渠中。
  6. 根據申請專利範圍第5項之方法，其中在形成該第三溝渠時，該第三溝渠被形成，以便留下沿著存在於該第三溝渠的側表面上之深度方向延伸的該源極層。
  7. 根據申請專利範圍第5項之方法，其中在形成該第三溝渠時，該第三溝渠被形成，以便未留下沿著存在於該第三溝渠的側表面上之深度方向延伸的該源極層。
  8. 根據申請專利範圍第5至7項中任一項之方法，另包含：藉由蝕刻存在於該半導體層之該表面的該第二區上之該源極層的至少一部分，以露出該基極層，以及形成接觸該露出的基極層之源極電極。
  9. 根據申請專利範圍第1項之方法，另包含：藉由從該源極層的表面蝕刻預定厚度，以選擇性留下 存在於該半導體層的該表面之該第一區上的該源極和基極層，形成面向被留下存在於該半導體層的該第一區上之該基極層的絕緣平面閘極。
  10. 根據申請專利範圍第1至3項、第5至7項及第9項中任一項之方法，其中該寬能隙半導體為碳化矽。
  11. 根據申請專利範圍第4項之方法，其中該寬能隙半導體為碳化矽。
  12. 根據申請專利範圍第8項之方法，其中該寬能隙半導體為碳化矽。
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TWI534910B (zh) 2016-05-21
CN104919594B (zh) 2017-10-27
DE112014000565T5 (de) 2015-10-22
KR101710815B1 (ko) 2017-02-27
JP5961563B2 (ja) 2016-08-02
WO2014115494A1 (en) 2014-07-31
US9660046B2 (en) 2017-05-23

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