TW201436033A - 利用採用非腐蝕性蝕刻劑之電漿蝕刻腔室之二氧化矽-多晶矽多層堆疊蝕刻 - Google Patents
利用採用非腐蝕性蝕刻劑之電漿蝕刻腔室之二氧化矽-多晶矽多層堆疊蝕刻 Download PDFInfo
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Classifications
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Abstract
利用非腐蝕性處理氣體化學物對多層堆疊進行電漿蝕刻,該多層堆疊具有矽層,該等矽層與介電層(諸如二氧化矽)交錯。藉由脈衝RF激活(energize)氟源氣體(諸如通常僅適合於介電層之SF6及/或NF3)之蝕刻電漿,以在不添加腐蝕性氣體(諸如HBr或Cl2)的情況下,達成對矽/二氧化矽雙層堆疊進行高深寬比蝕刻。在實施例中,遮罩開口蝕刻及多層堆疊蝕刻在致能單一腔室(即用於圖案化該等多層堆疊之單一配方解決方案)的同一電漿處理腔室中執行。在實施例中,利用記憶體插塞(memory plug)及/或採用氟基RF脈衝電漿蝕刻之字線分離蝕刻製造3D NAND記憶體單元。
Description
本申請案為申請於2013年1月25之美國臨時專利申請案第61/757,027號申請案的非臨時申請案,本申請案主張該美國臨時專利申請案的優先權,且為達成全部目的,本申請案將該美國臨時專利申請案以引用之方式全部併入。
本發明之實施例係關於半導體處理領域,且本發明尤其係關於電漿蝕刻包含矽及介電層兩者之多層薄膜的方法。
記憶體晶片包含所製造之半導體裝置的較大部分。一種普及的半導體記憶體技術為NAND EEPROM(快閃記憶體),該NAND EEPROM之示意圖在第1A圖中圖示。一般而言,NAND之16位元單元包括一串18個電晶體。由於各尺寸的縮小,微影術之局限性變得具有更多問題,半導體裝
置微縮化中的目前趨勢包括三維(3D)裝置設計。第1B圖圖示一個示例性3D NAND架構,藉以垂直定向(而非橫向定向)該電晶體串。如第1B所示,串150中之每一電晶體均耦接至閘極電極層,形成上部選擇閘極及下部選擇閘極,及位於上部選擇閘極與下部選擇閘極之間的16個控制閘極。
儘管3D NAND針對進一步之可擴展性(例如潛在地致能萬億位元單元陣列)有前景,甚至代替進一步之微影進步,但是製造該種裝置(尤其相對於形成延伸穿過許多閘極電極層之垂直特徵(例如插塞))是一種挑戰。如第1B圖所示,藉由層間介電質彼此分隔的18個閘極電極層可能需要以某些有利的整合方案進行蝕刻。因而,對超過16對的薄膜(亦即雙層,且其中每一薄膜具有有限之厚度(例如20-60奈米(nm))進行蝕刻,待清除雙層堆疊之總蝕刻深度可能非常厚,該厚度增加至超過兩微米,此時由於更高的位元計數,故垂直電晶體計數增加。
雙層中之材料的成分差異使得蝕刻3D NAND雙層堆疊更具挑戰性。鑒於典型的蝕刻製程在3D NAND雙層堆疊內部清除對下層具有高選擇性之薄膜,閘極電極層有利地為多晶矽,而層間介電質(ILD)則為二氧化矽。然而,大多數電漿蝕刻系統經設計以蝕刻此等材料之任一者,而非兩者。確實,可很好地蝕刻二氧化矽之系統通常對於多晶矽具有很高的選擇性,而對於導體蝕刻系統則相反,使得使用單一電漿蝕刻系統蝕刻兩種薄膜具有固有的難度。
本文描述利用採用非腐蝕性蝕刻劑之電漿蝕刻腔室之二氧化矽-多晶矽多層堆疊蝕刻。
在一個實施例中,一種蝕刻設置於基板之上之矽與介電層堆疊之方法涉及將基板載入電漿蝕刻腔室中。基板具有遮罩層,該遮罩層設置於矽與介電層之堆疊之上。該方法涉及將處理氣體引入至腔室中。處理氣體全部為非腐蝕性氣體。該方法涉及用具有至少一種頻率之RF能量將處理氣體激活為電漿。RF能量在RF開啟狀態與RF關閉狀態之間隨時間經脈衝(pulsed over time)。該方法進一步涉及使用未經遮罩層覆蓋之堆疊的電漿部分蝕刻。對於遮罩層之蝕刻選擇率至少為1:1。該方法亦涉及將基板從電漿蝕刻腔室卸載。
在一個實施例中,一種形成三維(3D)NAND記憶體裝置之方法涉及將基板載入電漿蝕刻腔室。基板具有遮罩層,該遮罩層設置在矽字線閘極電極層之堆疊上,該等矽字線閘極電極層藉由插入矽基介電層彼此電隔離。該方法涉及將處理氣體引入至該腔室中。處理氣體全部為非腐蝕性氣體。該方法涉及用具有至少一種頻率之RF能量將處理氣體激活為電漿。RF能量在RF開啟狀態與RF關閉狀態之間隨時間經脈衝。該方法涉及使用電漿蝕刻穿過未經遮罩層覆蓋之區域中的堆疊之厚度的通孔或溝槽,該蝕刻對於該遮罩層之選擇率大於1:1。該方法亦涉及將基板從電漿蝕刻腔室卸載。
根據一個實施例,電漿蝕刻設備包括處理腔室及夾盤,該夾盤設置於處理腔室中,以在蝕刻基板的同時支撐基板。設備包括垂直(plumb)於該腔室之複數個源氣體。該等
複數個源氣體包括SF6、NF3、CH4、O2、N2及COS。設備包括複數個RF發生器,以用複數個RF頻率激活該等處理氣體成為電漿。該設備亦包括耦接至該等複數個RF發生器之脈衝控制器。脈衝控制器在RF開啟狀態與RF關閉狀態之間隨時間同步地脈衝RF發生器之每一者,以使全部發生器至少在一些時段同時地處於RF關閉狀態。
150‧‧‧串
200‧‧‧方法
201‧‧‧操作
203‧‧‧操作
205‧‧‧操作
207‧‧‧操作
210‧‧‧操作
215‧‧‧操作
220‧‧‧操作
250‧‧‧方法
300‧‧‧電漿蝕刻系統
305‧‧‧腔室
310‧‧‧基板
315‧‧‧開口
320‧‧‧陰極
321‧‧‧第二熱區域
322‧‧‧第一熱區域
325‧‧‧偏壓功率RF發生器
326‧‧‧偏壓功率RF發生器
327‧‧‧RF匹配器
330‧‧‧RF源/源發生器
335‧‧‧電漿生成元件
340‧‧‧磁線圈
341‧‧‧磁線圈
343‧‧‧源氣體
344‧‧‧源氣體
345‧‧‧源氣體
346‧‧‧源氣體
347‧‧‧源氣體
349‧‧‧質量流量控制器
351‧‧‧排氣閥
355‧‧‧大容量真空泵堆疊
370‧‧‧控制器
372‧‧‧中央處理器
373‧‧‧記憶體
374‧‧‧輸入/輸出電路
410‧‧‧基板
415‧‧‧蝕刻終止層
420‧‧‧雙層堆疊
425‧‧‧含碳層/非晶碳層/含碳遮罩
430‧‧‧無機介電帽層
1002‧‧‧腔室
1004‧‧‧夾盤
1100‧‧‧電漿
1102‧‧‧工件
1104‧‧‧反應區
本文以附圖之圖式中之實例的方式說明(而非限制)本發明之實施例,在該等圖式中:第1A圖為習知的NAND架構之示意圖;第1B圖為3D NAND架構之等角視圖,該3D NAND架構可根據本發明之實施例製造。
第2A圖為一流程圖,該流程圖圖示根據本發明之實施例用於打開遮罩且蝕刻多晶矽/二氧化矽雙層之堆疊的方法;第2B圖為一流程圖,該流程圖圖示根據本發明之實施例用於蝕刻多晶矽/二氧化矽雙層之堆疊的方法;第3圖為根據本發明之實施例之蝕刻系統的示意圖;第4A圖至第4C圖為根據實施例執行第2A圖及第2B圖所示之方法中的操作所形成之結構的橫截面圖;第5圖為圖示根據本發明之實施例RF脈衝的時序圖;第6A圖及第6B圖圖示根據本發明之實施例RF功
率開啟及關閉狀態下之電漿蝕刻腔室;第7A圖及第7B圖為圖示根據本發明之實施例電漿蝕刻條件之表格;以及第8A圖為根據本發明之實施例藉由利用非腐蝕性處理氣體蝕刻的多晶矽/二氧化矽雙層之堆疊的橫截面SEM圖像;以及第8B圖為藉由習知的介電蝕刻製程蝕刻之多晶矽/二氧化矽雙層之堆疊的橫截面SEM圖像。
利用非腐蝕性處理氣體化學物對多層堆疊進行電漿蝕刻,該等多層堆疊具有矽層,該等矽層與介電層(諸如二氧化矽)交錯。以下描述中闡述了許多特定的詳細內容(諸如電漿腔室硬體、氣體化學物及製程序列),以便提供對本發明之實施例之徹底的瞭解。熟習此項技術者將顯而易見,本發明之實施例可在沒有此等特定詳細內容的情況下實施。在其他情況下,未詳細描述諸如積體電路製造之眾所熟知的態樣,以便不必要地模糊本發明之實施例。此外,應瞭解,圖式中所示之多種實施例為說明性表示,且不一定按比例繪製該等實施例。
在實施例中,採用非腐蝕性氣體蝕刻堆疊之矽層及介電層兩者,該堆疊包含此等材料層兩者。儘管眾所熟知腐蝕性氣體(諸如HBr或Cl2)易於快速蝕刻矽,本文之實施例有利地避免使用該等氣體,致能更簡單之蝕刻硬體,該蝕刻硬體具有較低的固定成本及較低的消耗成本兩者。在實施例
中,該等非腐蝕性氣體為氟基氣體,該氟基氣體不僅以易於快速蝕刻許多介電質(例如矽基介電質,諸如二氧化矽、氮化矽、氧氮化矽等)為人熟知,並且眾所熟知,在習知的電漿蝕刻條件下該氟基氣體為矽的較差蝕刻劑。然而,發明人已經發現,在對激活包括氟物質及實質上沒有腐蝕性氣體(例如未有意添加Cl2、HBr或類似氣體)之電漿的RF源進行適當控制的情況下,可以相當高之速率蝕刻矽,且免受蝕刻在很高之深寬比(AR)(例如20或20以上之深寬比)處終止。即使矽層(例如多晶矽)之厚度大於插入介電層(例如二氧化矽)之厚度,蝕刻速度亦足夠高,上覆遮罩層之可接受的選擇性足夠蝕刻穿過甚至2微米(μm)之矽/介電雙層的堆疊。
在實施例中,蝕刻電漿包括藉由脈衝RF激活之含氟源氣體(諸如SF6及/或NF3),以在不添加腐蝕性氣體的情況下達成對多晶矽/介電雙層之堆疊的高深寬比蝕刻。在實施例中,遮罩開口蝕刻及多層堆疊蝕刻在致能單一腔室(即用於圖案化該等多層堆疊之單一配方解決方案)之同一電漿處理腔室中執行。在實施例中,使用記憶體插塞及/或採用氟基RF脈衝電漿蝕刻之字線分離蝕刻製造3D NAND記憶體單元。
第2A圖為一流程圖,該流程圖圖示根據本發明之實施例用於打開遮罩且蝕刻多晶矽/二氧化矽雙層堆疊之方法200。一般而言,方法200為單一腔室蝕刻製程,藉以首先在操作201處將基板載入腔室,且隨後在操作203處(例如,在製程配方之第一部分期間)蝕刻非光可界定之遮罩層。完
成此「遮罩-開口」蝕刻後,在操作205處,該同一蝕刻腔室執行第二蝕刻製程,以移除矽/矽基介電雙層之堆疊的部分。如上所述,電漿蝕刻操作205實質上未使用腐蝕性處理氣體,而是使用氟基源氣體作為代替。在清除堆疊之厚度後,在操作207處,將基板從蝕刻腔室中卸載。
第3圖為根據本發明之實施例之蝕刻系統的示意圖,該蝕刻系統用於執行方法200。在特定實施例中,系統300為耦接至平台的介電蝕刻腔室,該平台諸如可購自於加利福尼亞州聖克拉拉市之應用材料公司的Centura®平台,且該平台能夠代管複數個系統300。系統300亦可購自於應用材料公司商標名為Avatar EtchTM的產品。一般而言,系統300包括接地腔室305。基板310經由開口315載入腔室300,且將基板夾持至溫度受控之陰極320。在特定實施例中,溫度受控之陰極320包括複數個區域,每一區域獨立可控到一溫度設定點,諸如第一熱區域322(位於基板310之中心附近)及第二熱區域321(位於基板310之外圍附近)。從源氣體343、344、345、346及347經由各自的質量流量控制器349將處理氣體供給至腔室305之內部。例如,經由連接至包括渦輪分子泵之大容量真空泵堆疊355之排氣閥351,使腔室305排空至20mTorr與100mTorr之間。
當應用RF功率時,電漿在基板310上之腔室處理區形成。偏壓功率RF發生器325耦接至陰極320,且提供偏壓功率以激活電漿。偏壓功率RF發生器325通常具有約2MHz至60MHz之間之低頻率,且在特定實施例中,該頻率
約為2MHz。在某些實施例中,電漿蝕刻系統300包括可在約60MHz下操作之第二偏壓功率RF發生器326。兩種偏壓功率連接至同一RF匹配器327,然而,亦可使用單獨的匹配。電源RF發生器330亦經由匹配(未圖示)耦接至電漿生成元件335(相對於陰極320可能為陽極),以提供激活該電漿之高頻電源。電源RF發生器330通常比偏壓RF發生器325、326具有更高之頻率,且例如在100與180MHz之間之頻率,且在一個實施例中,該頻率為162MHz頻帶。一般而言,偏壓功率影響基板310上之偏壓,控制基板310之離子轟擊,而電源相對獨立於基板310上之偏壓影響電漿密度。
應注意,根據實施例,給定輸入氣體組(電漿由該組氣體生成)的蝕刻效能隨電漿密度及晶圓偏壓顯著地變化,因此激活該電漿之功率的數量及頻率兩者都是重要的。因為基板直徑隨時間漸增(從150mm、200mm、300mm等),因此在此項技術中,歸一化(normalize)對基板區域施加的電漿蝕刻系統之電源及偏壓功率為常見的。在所圖示之實施例中,系統300亦包括磁線圈340及341,以生成磁場,該磁場致能對電漿均勻性的調整。
在本發明之實施例中,系統300為可由控制器370實現電腦可控,以控制低頻率偏壓功率、高頻率電源、源氣體流動速率、壓力及基板溫度以及其他製程參數。控制器370可為任何形式之通用資料處理系統之一,該資料處理系統可用於工業設置中,以控制多種子處理器及子控制器。一般而言,除其他常見元件之外,控制器370還包括與記憶體373
通訊之中央處理器(CPU)372,及輸入/輸出(I/O)電路374。藉由CPU 372執行軟體指令,使得系統300進行一些操作,例如將基板載入電漿蝕刻腔室、引入包括來自源343、344、345、346及347之一或更多處理氣體之處理氣體混合物及經由傳遞來自一或更多RF源325、326及330之RF能量,將此等處理氣體混合物激活為電漿。本發明之部分可作為可包括電腦可讀媒體之電腦程式產品提供,該電腦可讀媒體上儲存有指令,該等指令可用於程式化電腦(或其他電子裝置)以控制蝕刻系統300,以執行第2A圖之蝕刻方法200及/或第2B圖之蝕刻方法250。電腦可讀媒體可包括(但不僅限於)軟碟、光碟、CD-ROM(光碟唯讀記憶體)及磁光碟、ROM(唯讀記憶體)、RAM(隨機存取記憶體)、EPROM(可擦可程式唯讀記憶體)、EEPROM(電可擦可程式唯讀記憶體)、磁卡或光卡、快閃記憶體或其他通常熟知類型的適用於儲存電子指令之電腦可讀儲存媒體。此外,本發明亦可作為包含電腦程式產品之程式檔案下載,其中該程式檔案可從遠端電腦轉移至請求電腦。
在實施例中,三種RF源之每一者經進一步配置,以作為連續波(CW)模式操作或在脈衝模式中操作,在脈衝模式下,控制器(諸如控制器370)導致一或更多RF源在RF「開啟」及RF「關閉」狀態下重複循環。在實施例中,如本文進一步描述,在蝕刻矽/矽基介電質堆疊(例如在操作205處)之至少一部分期間,在脈衝模式下操作全部三種RF源325、326及330。
第2B圖為一流程圖,該流程圖圖示根據本發明之該實施例之用於蝕刻多晶矽/二氧化矽雙層之堆疊的方法250。方法250從將基板設置於蝕刻腔室中開始,例如在第2A圖中之操作210完成後開始。在操作210處,方法250以引入含氟蝕刻劑氣體(諸如SF6及/或NF3)繼續進行。在該示例性實施例中,一或更多含氟蝕刻劑氣體與其他處理氣體混合,該等其他氣體包括氧化劑(有利為O2)及碳源(有利為CH4)。在其他實施例中,亦引入氮,最有利為N2。儘管不受理論約束,當前認為碳源用作鈍化氣體,因為已發現碳源之存在改良對遮罩材料的選擇性且改良側壁輪廓,同時已發現O2減少在所蝕刻之特徵(例如通孔)的最高部分處發生阻塞,且亦鈍化矽層側壁部分。可將氮用作影響輪廓控制及遮罩腐蝕速度(亦即遮罩選擇性)之調整氣體。在採用SF6作為蝕刻劑氣體之一個實施例中,處理氣體混合物包括一份SF6、1.2-1.65份CH4、0.04-0.15份O2及0.7-1.5份N2。在採用SF6作為蝕刻劑氣體之某些有利實施例中,處理氣體混合物包括一份SF6、2-30份CH4、0.4-4份O2、1-30份N2及1-20份NF3。腔室壓力可不同,但是已發現20-50mT範圍之壓力為有利的,該範圍之壓力可提供良好的蝕刻薄膜蝕刻速度及良好的輪廓控制兩者。
在操作215處,使用由一或更多RF源施加之RF功率將該(該等)處理氣體激活為電漿。已發現當三種RF源325、326及330全部用於激活電漿時,可達成具有良好選擇率(亦即顯著高於1:1)之高深寬比(HAR)蝕刻。在示例性
實施例中,偏壓功率發生器325輸出之功率在4kW與8kW之間,偏壓功率發生器326輸出之功率在0.5kW與3kW之間,而源發生器330輸出之功率在1kW與3kW之間。
在操作220處,RF能量在RF開啟狀態與RF關閉狀態之間隨時間經脈衝。已發現當RF能量在RF開啟狀態與RF關閉狀態之間隨時間經脈衝時,可獲得對遮罩材料(特定言之為非晶碳遮罩層)更高之選擇率。在有利之實施例中,脈衝將對非晶碳遮罩材料之選擇率增加至2:1或更高。此外,已發現,隨著深寬比增加,脈衝減少了(多)矽層上蝕刻終止的發生。第5圖為描述根據本發明之實施例RF脈衝的時序圖。如圖所示,電漿功率在工作循環中循環。一般而言,在脈衝電漿蝕刻操作220期間,單一RF能量源可經脈衝或複數個RF源可同時經脈衝。在單一RF源脈衝時,電源330或偏壓功率325、326之一者可使用在0%(連續關閉)或100%(連續波)之工作循環下操作的剩餘RF源而經脈衝。
發明人已發現同步脈衝實施例對於保持高遮罩選擇率(由於本文其他處所描述之SF6、NF3、CH4、O2、N2之示例性處理氣體混合物,選擇率可為2:1或更高),及減少蝕刻終止發生(由於深寬比增加超過20,且更特定言之超過25-30)兩者特定有利。在同步脈衝時,兩個或更多個RF源經脈衝之工作循環相等且同相,或不相等且/或彼此異相。在高度有利之實施例中,全部的RF頻率在脈衝之工作循環(亦即,工作循環,即使相位不相等)期間之至少一些時段同時處於RF關閉狀態。如第5圖所示,即使工作循環不相等,例如在電源
330之工作循環大於偏壓功率326之工作循環,偏壓功率326之工作循環又大於偏壓功率325之工作循環的情況下,總有一段時期,全部三個發生器同時處於RF關閉狀態中。各RF發生器之電漿脈衝頻率通常可在1Hz與200kHz之間,但是已發現在5-8kHz範圍內之脈衝,且關閉狀態下循環重疊20與125μsec(微秒)之間,此對蝕刻矽/二氧化矽多層有利。
第6A圖至第6B圖圖示根據本發明之實施例分別在電漿開啟狀態與電漿關閉狀態中之腔室,例如來自蝕刻系統300之腔室。參閱第6A圖,在開啟狀態(當電漿1100存在時)期間,在接近設置於夾盤1004上之工件1102處形成反應區1104。在脈衝蝕刻操作220期間,在反應區1104內可能形成蝕刻副產物,且該等蝕刻副產物會在反應區1104內滯留(至少一段時間)。因此,根據本發明之實施例,用於脈衝控制器370之該組指令包括時序指令,以使得開啟狀態的持續時間充分短,以在反應區1104內以第一標稱水平(例如20eV)實質施加離子能量。參閱第4B圖,腔室1002處於電漿關閉狀態(例如中性反應氣體)。根據本發明之實施例,用於脈衝控制器370之該組指令包括時序指令,使得將脈衝電漿蝕刻操作220中之工作循環的關閉狀態的持續時間選擇為充分長,以清除反應產物之蝕刻前面,且使用處理氣體物質刷新蝕刻前面的曝露表面。目前認為,此時間為10微秒或100微秒數量級。
即使在RF脈衝期間,處理氣體可持續不斷地流動。然而,因為脈衝電漿蝕刻製程中工作循環之開啟狀態期間,
可能消耗用於生成電漿之反應氣體物質,電漿自偏壓條件可能隨著電漿脈衝工作循環之持續時間而改變。在一些情況下,電漿修改實質上可能足以改變電漿偏壓電位。藉由在蝕刻製程期間補充反應氣體,可緩和電漿修改情況。
在實施例中,第4A圖至第4C圖為結構之橫截面圖,該等結構由執行第2A圖及第2B圖所示之方法中的操作所形成,以形成三維(3D)NAND記憶體裝置。首先參閱第4A圖,執行遮罩開口蝕刻,以在非光可界定材料(諸如但不僅限於含碳層)中打開圖案。如本文中所用,含碳層包括具有至少20重量%之碳的無機層。此類材料中包含非晶碳,該非晶碳通常具有高於50重量%的碳,且低介電常數介電質具有至少20重量%的碳含量。「含碳」類不包括含碳總量小於20重量%的有機材料,諸如彼等通常用作底部抗反射塗層(BARC)之材料,該等材料通常包括聚醯胺及聚碸,且具有少於5重量%的碳。在所圖示之實施例中,含碳層425在雙層堆疊420、蝕刻終止層415及基板410之上形成。
含碳層425可使用噴塗式/旋塗式方法、使用熱沉積製程(CVD)或使用電漿增強沉積製程(PECVD)形成。第4A圖所示之實施例中,使用CVD或PECVE沉積非晶碳層425,以形成至少包含50重量%之碳,具有sp1、sp2及sp3鍵結態的碳材料,該等鍵結態使得沉積碳材料具有薄膜性能,該薄膜性能為熱解性、石墨性及類金剛石之彼等典型性能之混合。由於沉積碳材料可含有多種比例之複數個鍵結態,該沉積碳材料缺乏長程有序,且因此常將該材料稱為「非
晶碳」。在特定實施例中,非晶碳層425可使用烴前驅物之PECVD製程形成,該等烴前驅物諸如(但不僅限於)甲烷(CH4)、丙烯(C3H6)、丙炔(C3H4)、丙烷(C3H8)、丁烷(C4H10)、丁烯(C4H8)、丁二烯(C4H6)、乙炔(C2H2)、甲苯(C7H8(C6H5CH3))及以上各者之混合物。非晶碳層425亦可包括氮或其他的添加物,諸如硼摻質。示例性非晶碳材料可購自美國加利福尼亞州應用材料公司商標名為Advanced Patterning FilmTM(APF)的產品,而摻雜硼之非晶碳材料亦可購自應用材料公司商標名為Saphira的產品。儘管未進行描述,在另一實施例中,在碳重量%範圍之下端點,含碳層為低介電常數介電質,諸如可購自應用材料公司商標名為Black DiamondTM的介電質。
在該示例性實施例中,含碳遮罩425之厚度至少為1.2μm,且可為3-5μm或更厚,此厚度視雙層之下層堆疊420的厚度而定。同樣也如第4A圖所示,使用無機介電帽層430覆蓋非晶碳層425。無機介電帽層430可用作介電抗反射層(DARC),且/或改良隨後藉由旋塗技術塗覆的有機薄膜之黏著力,否則該薄膜可能不能較好地黏附至非晶碳層425。無機介電帽層430可為單一薄膜或薄膜之多層堆疊,該多層堆疊包括以二氧化矽、氮化矽或矽氧氮化物(SiON)形式存在的矽、氮化物、氧。由於在特徵之微影圖案化期間採用特定的波長,組合物及厚度亦可經調整以提供最小反射及高對比度。在示例性實施例中,形成的無機介電帽層430之厚度約在25nm與400nm之間。設置在帽層430上的為任何習知的
光阻劑(未圖示),該光阻劑用作用於蝕刻(該蝕刻用於打開帽層430)及/或遮罩開口蝕刻(在該蝕刻期間打開含碳層425)之遮罩。在一些光阻劑實施例中,有機BARC應用於無機介電帽層430之上,以進一步減少感光層之圖案化期間的光反射。BARC通常包括聚醯胺及聚碸。
在特定實施例中,遮罩開口蝕刻(例如在第2A圖中操作203處執行)使用包括具有(COS)x之化學通式的碳硫終端配位基的處理氣體混合物執行。在較佳實施例中,包括碳硫終端配位基之氣體為硫化羰,COS。儘管兩組份COS:O2蝕刻劑混合物實施例可為有利的,在將其他物質引入至處理氣體混合物的情況下,可實現側壁輪廓之改良。在特定實施例中,蝕刻劑氣體混合物進一步包括N2、CO、CO2、O3、H2O、H2O2之至少一者。亦應注意,在替代實施例中,可將N2源替換為其他氮源,諸如(但不僅限於)氮氧化合物(NO、N2O等)或氨(NH3)。蝕刻劑氣體混合物可進一步包括惰性氣體,諸如氬氣、氦氣或氙氣。
在遮罩開口電漿蝕刻之後,處理氣體化學物經調整(例如在第二「主要蝕刻」配方步驟期間)以包括SF6及/或NF3,及含氧(例如O2)源氣體、含碳(例如CH4)源氣體及含氮(例如N2)源氣體(例如以本文其他處所描述之比率添加)。如本文其他處所描述,隨後激活電漿(例如使用本文其他處所描述之偏壓及電源),且在示例性實施例中經脈衝。在限定時間內執行此主要蝕刻(例如第2A圖中之操作205),或執行該主要蝕刻直至曝露終止層(第4B圖中的415),以
清除出穿過包括16-24個矽字線閘電極層(例如多晶矽)之堆疊420之開口(例如通孔),藉由插入矽基介電層(例如二氧化矽),矽字線閘電極層彼此電隔離。在實施例中,對於各雙層,(多)矽層之厚度至少與該二氧化矽一樣厚。作為一個實例,各(多)矽字線閘電極層之厚度為50-60nm,而各二氧化矽層之厚度為20-50nm。在實施例中,堆疊420之總厚度在1.5μm與3μm之間,其中蝕刻至堆疊420中的開口(例如用於記憶體接線插塞或用於使字線電極分叉之溝槽)的直徑為60-80μm。因而,所蝕刻之特徵的深寬比為25-40或更高。在如本文所述採用具有RF脈衝之本文所描述的氟基化學物的示例性實施例中,對堆疊420之蝕刻以高於對含碳遮罩425之蝕刻速度的比率(例如大於1:1的選擇率),且有利地至少為2:1的比率進行。如第4C圖所示,在移除遮罩425的情況下,按照此項技術中的已知技術,預備對圖案化堆疊420進行一步處理。例如,在一個實施例中,插塞在各所蝕刻的開口中形成,以形成垂直的NAND記憶體串。
第7A圖及第7B圖為圖示根據本發明之實施例之電漿蝕刻條件之表格。第8A圖為根據本發明之實施例之藉由使用第7A圖中所列之非腐蝕性蝕刻劑氣體蝕刻的多晶矽/二氧化矽雙層之堆疊的橫截面SEM。如第8A圖所示,且與第8B圖相比,蝕刻幾乎完全穿過堆疊420,而沒有穿透遮罩425。第8B圖為橫截面SEM圖像,第8B圖示包括設置於基板410之上的雙層420之堆疊(該堆疊與第8A圖所示之堆疊相同)的測試晶圓,第8B圖展示使用介電蝕刻工具蝕刻多晶矽及二
氧化矽之雙層堆疊的困難。儘管如此,第8B圖所採用之蝕刻製程是更為習知的介電蝕刻製程,亦採用氟基化學物,但是該製程缺乏以第7A圖中表格所列內容為特徵的射頻脈衝及特定處理氣體混合物。因而,第8B圖表示使用執行習知通孔蝕刻製程之習知的介電蝕刻系統可完成的結果。明顯看出,第8B圖與第8A形成對比,雙層堆疊420僅被部分地蝕刻(約堆疊厚度的20%),可是由於藉由虛線突出顯示,已經大大地消耗了遮罩材料425(亦即蝕刻選擇率遠低於2:1,且由於化學物與功率組合,蝕刻選擇率甚至可能低於1:1)。
第7B圖中之表格圖示涉及RF脈衝及氣體比例(類似於第7A圖之表中的彼等比例)之其他實施例。然而,第7B圖之表格中描述的氣體混合物除包括SF6之外還包括NF3。與第7A圖中所描述之氣體比例相比,包括NF3及SF6之氣體混合物可導致相似或改良之蝕刻結果。
返回到第4C圖,在主要蝕刻之後,可去除任何剩餘遮罩材料(例如現場(在執行遮罩開口及主要蝕刻操作之同一蝕刻腔室內)去除),以達到第4A圖所示之圖案化結構。完成電漿蝕刻後,將基板從蝕刻腔室中卸載,且以此項技術中任何已知方式(例如記憶體插塞沉積等)進行3D NAND處理。
應瞭解,以上描述意欲為說明而非限制。舉例而言,儘管圖式中流程圖顯示由本發明之某些實施例執行的特定的順序的操作,應瞭解,該順序並非必需(例如替代實施例可以不同的順序執行該等操作、可組合某些操作、可重複某些
操作等)。此外,在閱讀且理解以上描述的情況下,許多其他實施例對於熟悉此項技術者將變得顯而易見。儘管本文已參考特定示例性實施例描述本發明,應認識到本發明並不受限於所描述之實施例,而是在附加之申請專利範圍之精神及範疇內,可實施經修改及改變的本發明。因此,應參考附加申請專利範圍,及該等申請專利範圍對同等物全部範疇所主張之權利判定本發明之範疇。
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Claims (20)
- 一種蝕刻設置於一基板之上的矽及介電層之一堆疊的方法,該方法包含以下步驟:將該基板加載至一電漿蝕刻腔室中,該基板具有一遮罩層,該遮罩層設置於該矽及介電層之堆疊之上;將處理氣體引入該腔室中,其中該等處理氣體均為非腐蝕性;用具有至少一種頻率之RF能量將該等處理氣體激活為一電漿,其中該RF能量在一RF開啟狀態與一RF關閉狀態之間隨時間經脈衝(pulsed);使用該電漿蝕刻未經該遮罩層覆蓋之該堆疊之部分,該蝕刻對於該遮罩層之一選擇率至少為1:1;以及將該基板從該電漿蝕刻腔室中卸載。
- 如請求項1所述之方法,其中該堆疊包含至少16個雙層,各雙層具有一多晶矽層及一二氧化矽層,且其中該遮罩層包含非晶碳。
- 如請求項1所述之方法,其中該等處理氣體包括一含氟氣體,且該等處理氣體實質上不含HBr及Cl2。
- 如請求項1所述之方法,其中該RF能量包含同步經脈衝之複數個頻率,且在該脈衝之一工作循環期間,至少有一段時間全部RF頻率同時處於該RF關閉狀態。
- 如請求項4所述之方法,其中該RF能量由操作頻率為2MHz之一第一發生器、操作頻率為60MHz之一第二發生器及操作頻率為162MHz之一第三發生器供給,且其中每一發生器使用一相應的工作循環經脈衝,該等三個工作循環經同步以使得至少一段時間內全部三個發生器同時處於該RF關閉狀態。
- 如請求項5所述之方法,其中該段時間在20μs與125μs之間。
- 如請求項5所述之方法,其中該第一及第二發生器輸出一功率,該功率在4kW與8kW之間,且其中該第三發生器輸出一功率,該功率在1kW與3kW之間。
- 如請求項3所述之方法,其中該等處理氣體包括SF6及NF3之至少一者。
- 如請求項8所述之方法,其中該等處理氣體進一步包括一氧化劑及一碳源氣體。
- 如請求項9所述之方法,其中該氧化劑包含O2,且其中該碳源氣體包含CH4。
- 如請求項10所述之方法,其中該等處理氣體進一步包括N2。
- 如請求項10所述之方法,其中在為20mT與50mT之間的一腔室壓力下,該等處理氣體包含1份SF6、2-30份CH4、0.4-4份O2、1-30份N2及1-20份NF3。
- 如請求項1所述之方法,該方法進一步包含以下步驟:在將該基板載入該腔室之後,使用一第二電漿對一上覆圖案化層選擇性地蝕刻穿過該遮罩層,該第二電漿包含由包括COS、N2及O2之第二處理氣體所激活的物質。
- 一種形成三維(3D)NAND記憶體裝置之方法,該方法包含以下步驟:將一基板載入一電漿蝕刻腔室中,該基板具有一遮罩層,該遮罩層設置在矽字線閘極電極層之一堆疊上,該等閘極電極層藉由一插入的矽基介電層彼此電隔離;將處理氣體引入該腔室,其中該等處理氣體全部為非腐蝕性;使用具有至少一種頻率之RF能量激活該等處理氣體,其中該RF能量在一RF開啟狀態與一RF關閉狀態之間隨時間經脈衝; 使用該電漿蝕刻穿過未經該遮罩層覆蓋之區域的該堆疊之厚度的通孔或溝槽,該蝕刻對該遮罩層之一選擇率大於1:1;以及將該基板從該電漿蝕刻腔室卸載。
- 如請求項14所述之方法,其中該堆疊至少包含16個雙層,各雙層具有一多晶矽層及一二氧化矽層,且其中該遮罩層包含非晶碳。
- 如請求項14所述之方法,其中該RF能量由操作頻率為2MHz之一第一發生器、操作頻率為60MHz之一第二發生器及操作頻率為162MHz之一第三發生器供給,且其中每一發生器使用一相應的工作循環經脈衝,該等三個工作循環經同步以使得至少一段時間內所有三個發生器同時處於該RF關閉狀態下。
- 如請求項16所述之方法,其中該段時間在20msec與100msec之間。
- 如請求項14所述之方法,其中在為20mT與50mT之間的一腔室壓力下,該等處理氣體包含1份SF6、2-30份CH4、0.4-4份O2、1-30份N2及1-20份NH3,且其中對該遮罩層之蝕刻選擇率至少為2:1。
- 一種電漿蝕刻設備,該設備包含:一處理腔室;一夾盤,該夾盤設置在該處理腔室中,以在蝕刻一基板之同時支持該基板;複數個源氣體,該等複數個源氣體垂直於(plumbed to)該腔室,該等複數個源氣體包括SF6、NF3、CH4、O2、N2及COS;複數個RF發生器,以用複數個RF頻率將該等處理氣體激活為一電漿;以及一脈衝控制器,該脈衝控制器耦接至該等複數個RF發生器,該脈衝控制器在一RF開啟狀態與一RF關閉狀態之間隨時間同步地脈衝該等複數個RF發生器之每一者,以使得全部的發生器至少在某一時段同時處於該RF關閉狀態。
- 如請求項19所述之電漿蝕刻設備,其中該脈衝控制器界定在20μs與125μs之間之時段。
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Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20150087144A1 (en) * | 2013-09-26 | 2015-03-26 | Taiwan Semiconductor Manufacturing Company Ltd. | Apparatus and method of manufacturing metal gate semiconductor device |
KR20160039739A (ko) * | 2014-10-01 | 2016-04-12 | 삼성전자주식회사 | 하드 마스크막의 형성 방법 및 이를 이용한 반도체 소자의 제조 방법 |
US9799494B2 (en) * | 2015-04-03 | 2017-10-24 | Tokyo Electron Limited | Energetic negative ion impact ionization plasma |
KR102384893B1 (ko) | 2015-05-21 | 2022-04-08 | 삼성전자주식회사 | 반도체 소자 및 이의 제조 방법 |
US9922806B2 (en) * | 2015-06-23 | 2018-03-20 | Tokyo Electron Limited | Etching method and plasma processing apparatus |
US9711360B2 (en) | 2015-08-27 | 2017-07-18 | Applied Materials, Inc. | Methods to improve in-film particle performance of amorphous boron-carbon hardmask process in PECVD system |
US10418243B2 (en) | 2015-10-09 | 2019-09-17 | Applied Materials, Inc. | Ultra-high modulus and etch selectivity boron-carbon hardmask films |
US10424467B2 (en) * | 2017-03-13 | 2019-09-24 | Applied Materials, Inc. | Smart RF pulsing tuning using variable frequency generators |
JP2018200925A (ja) * | 2017-05-25 | 2018-12-20 | 東京エレクトロン株式会社 | エッチング方法およびエッチング装置 |
JP2022510370A (ja) * | 2018-12-04 | 2022-01-26 | サンライズ メモリー コーポレイション | 多層水平nor型薄膜メモリストリングの形成方法 |
US20230326737A1 (en) * | 2022-03-28 | 2023-10-12 | Tokyo Electron Limited | Technologies for high aspect ratio carbon etching with inserted charge dissipation layer |
WO2023230406A1 (en) * | 2022-05-24 | 2023-11-30 | Lam Research Corporation | Underlayer with bonded dopants for photolithography |
Family Cites Families (40)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100322695B1 (ko) | 1995-03-20 | 2002-05-13 | 윤종용 | 강유전성캐패시터의제조방법 |
KR100468700B1 (ko) | 1997-12-30 | 2005-03-16 | 삼성전자주식회사 | 반도체장치의미세패턴을형성하기위한건식식각방법 |
US6417080B1 (en) | 1999-01-28 | 2002-07-09 | Canon Kabushiki Kaisha | Method of processing residue of ion implanted photoresist, and method of producing semiconductor device |
US7137354B2 (en) * | 2000-08-11 | 2006-11-21 | Applied Materials, Inc. | Plasma immersion ion implantation apparatus including a plasma source having low dissociation and low minimum plasma voltage |
US6569257B1 (en) * | 2000-11-09 | 2003-05-27 | Applied Materials Inc. | Method for cleaning a process chamber |
US6951823B2 (en) | 2001-05-14 | 2005-10-04 | Axcelis Technologies, Inc. | Plasma ashing process |
US6991739B2 (en) | 2001-10-15 | 2006-01-31 | Applied Materials, Inc. | Method of photoresist removal in the presence of a dielectric layer having a low k-value |
JP3643580B2 (ja) | 2002-11-20 | 2005-04-27 | 株式会社東芝 | プラズマ処理装置及び半導体製造装置 |
US7064078B2 (en) | 2004-01-30 | 2006-06-20 | Applied Materials | Techniques for the use of amorphous carbon (APF) for various etch and litho integration scheme |
US7449416B2 (en) | 2004-09-01 | 2008-11-11 | Axcelis Technologies, Inc. | Apparatus and plasma ashing process for increasing photoresist removal rate |
JP4488999B2 (ja) | 2005-10-07 | 2010-06-23 | 株式会社日立ハイテクノロジーズ | エッチング方法およびエッチング装置 |
US7381651B2 (en) | 2006-03-22 | 2008-06-03 | Axcelis Technologies, Inc. | Processes for monitoring the levels of oxygen and/or nitrogen species in a substantially oxygen and nitrogen-free plasma ashing process |
US7727413B2 (en) | 2006-04-24 | 2010-06-01 | Applied Materials, Inc. | Dual plasma source process using a variable frequency capacitively coupled source to control plasma ion density |
JP4768557B2 (ja) | 2006-09-15 | 2011-09-07 | 株式会社東芝 | 不揮発性半導体記憶装置及びその製造方法 |
US8133819B2 (en) | 2008-02-21 | 2012-03-13 | Applied Materials, Inc. | Plasma etching carbonaceous layers with sulfur-based etchants |
US8018164B2 (en) | 2008-05-29 | 2011-09-13 | Applied Materials, Inc. | Plasma reactor with high speed plasma load impedance tuning by modulation of different unmatched frequency sources |
US8337661B2 (en) | 2008-05-29 | 2012-12-25 | Applied Materials, Inc. | Plasma reactor with plasma load impedance tuning for engineered transients by synchronized modulation of an unmatched low power RF generator |
US7967944B2 (en) | 2008-05-29 | 2011-06-28 | Applied Materials, Inc. | Method of plasma load impedance tuning by modulation of an unmatched low power RF generator |
US8357264B2 (en) | 2008-05-29 | 2013-01-22 | Applied Materials, Inc. | Plasma reactor with plasma load impedance tuning for engineered transients by synchronized modulation of a source power or bias power RF generator |
US8002945B2 (en) | 2008-05-29 | 2011-08-23 | Applied Materials, Inc. | Method of plasma load impedance tuning for engineered transients by synchronized modulation of an unmatched low power RF generator |
US8324525B2 (en) | 2008-05-29 | 2012-12-04 | Applied Materials, Inc. | Method of plasma load impedance tuning for engineered transients by synchronized modulation of a source power or bias power RF generator |
WO2010033924A2 (en) * | 2008-09-22 | 2010-03-25 | Applied Materials, Inc. | Etch reactor suitable for etching high aspect ratio features |
US8404598B2 (en) | 2009-08-07 | 2013-03-26 | Applied Materials, Inc. | Synchronized radio frequency pulsing for plasma etching |
US8435901B2 (en) | 2010-06-11 | 2013-05-07 | Tokyo Electron Limited | Method of selectively etching an insulation stack for a metal interconnect |
TW201216331A (en) | 2010-10-05 | 2012-04-16 | Applied Materials Inc | Ultra high selectivity doped amorphous carbon strippable hardmask development and integration |
US8598040B2 (en) * | 2011-09-06 | 2013-12-03 | Lam Research Corporation | ETCH process for 3D flash structures |
US8778207B2 (en) | 2011-10-27 | 2014-07-15 | Applied Materials, Inc. | Plasma etch processes for boron-doped carbonaceous mask layers |
US8974684B2 (en) | 2011-10-28 | 2015-03-10 | Applied Materials, Inc. | Synchronous embedded radio frequency pulsing for plasma etching |
US8883028B2 (en) | 2011-12-28 | 2014-11-11 | Lam Research Corporation | Mixed mode pulsing etching in plasma processing systems |
US9530620B2 (en) | 2013-03-15 | 2016-12-27 | Lam Research Corporation | Dual control modes |
US9368329B2 (en) | 2012-02-22 | 2016-06-14 | Lam Research Corporation | Methods and apparatus for synchronizing RF pulses in a plasma processing system |
US9197196B2 (en) | 2012-02-22 | 2015-11-24 | Lam Research Corporation | State-based adjustment of power and frequency |
US9390893B2 (en) | 2012-02-22 | 2016-07-12 | Lam Research Corporation | Sub-pulsing during a state |
US9462672B2 (en) | 2012-02-22 | 2016-10-04 | Lam Research Corporation | Adjustment of power and frequency based on three or more states |
US9171699B2 (en) | 2012-02-22 | 2015-10-27 | Lam Research Corporation | Impedance-based adjustment of power and frequency |
US8937800B2 (en) | 2012-04-24 | 2015-01-20 | Applied Materials, Inc. | Electrostatic chuck with advanced RF and temperature uniformity |
US9408288B2 (en) | 2012-09-14 | 2016-08-02 | Lam Research Corporation | Edge ramping |
US9330927B2 (en) | 2013-08-28 | 2016-05-03 | Lam Research Corporation | System, method and apparatus for generating pressure pulses in small volume confined process reactor |
US9184029B2 (en) | 2013-09-03 | 2015-11-10 | Lam Research Corporation | System, method and apparatus for coordinating pressure pulses and RF modulation in a small volume confined process reactor |
US9269587B2 (en) | 2013-09-06 | 2016-02-23 | Applied Materials, Inc. | Methods for etching materials using synchronized RF pulses |
-
2014
- 2014-01-17 US US14/157,997 patent/US9299574B2/en active Active
- 2014-01-22 WO PCT/US2014/012592 patent/WO2014116736A1/en active Application Filing
- 2014-01-23 TW TW103102510A patent/TW201436033A/zh unknown
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2015
- 2015-12-04 US US14/960,196 patent/US10643854B2/en active Active
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US20160086771A1 (en) | 2016-03-24 |
US9299574B2 (en) | 2016-03-29 |
US10643854B2 (en) | 2020-05-05 |
US20140213062A1 (en) | 2014-07-31 |
WO2014116736A1 (en) | 2014-07-31 |
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