TW201419473A - 基板之連接結構及其製法 - Google Patents
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Abstract
一種基板之連接結構,該基板係具有複數連接墊及外露該些連接墊之絕緣保護層,該連接結構係包括:設於該連接墊之外露表面上並延伸至該絕緣保護層上金屬層、以及設於該金屬層上之導電凸塊,且該導電凸塊之寬度係小於該連接墊之寬度。因該金屬層完全覆蓋該連接墊之外露表面,故於後續進行覆晶製程之填膠步驟時,膠材不會流至該連接墊表面,因而有效避免該膠材與該基板間發生脫層。
Description
本發明係有關一種連接結構,尤指一種半導體封裝件中之連接結構。
於覆晶封裝製程中,係將半導體元件藉由銲錫凸塊放置並電性連接至一封裝基板(package substrate)上,再將封裝基板連同半導體元件進行封裝。因此,習知半導體元件與封裝基板上均具有連接墊,以供該封裝基板與半導體元件(晶片)藉由銲錫凸塊相互對接與電性連接。
如第1圖所示,一基板30(如封裝基板或半導體晶片)係具有複數鋁材之連接墊300(於此僅以單一連接墊300即可表示全部連接墊300之情況),且該基板30上形成有外露該連接墊300之一聚亞醯胺製之絕緣保護層31。接著,於該連接墊300之外露表面上進行圖案化製程,係依序形成由鈦部11a、一銅部11b及一鎳部11c構成之金屬層11,以作為凸塊底下金屬層結構(Under Bump Metallurgy,UBM)。之後,於該鎳層11c上形成一導電凸塊12,再形成銲錫材料13於該導電凸塊12上,並回銲(reflow)該銲錫材料13以形成銲錫凸塊,供作為封裝基板與半導體晶片電性對接之連接結構1。
惟,習知連接結構1中,該金屬層11之設計並未完全覆蓋該連接墊300之外露表面,且因該金屬層11中之鈦部11a與聚亞醯胺(即該絕緣保護層31)之結合性強,故
經常於蝕刻除去多餘之金屬材料時(即圖案化製程),該鈦部11a無法完全自該絕緣保護層31表面清除,而會在該絕緣保護層31上殘留鈦金屬,導致於封裝基板與晶片進行覆晶接合後,當晶片運作時將造成各連接結構1之間的電性漏電(leakage)現象,影響整體封裝件的電性功能。
再者,因該金屬層11並未完全覆蓋該連接墊300之外露表面,故於後續進行覆晶製程之填膠(underfill)步驟時,將造成膠材流至該連接墊300表面,而使該膠材與該基板30間容易發生脫層(peel off),致使該連接結構1龜裂(crack),因而嚴重影響產品之信賴性。
又,為了因應電子裝置之輕薄短小化之需求,該基板30遂朝細間距進行設計,例如各該導電凸塊12之間的距離係為80μm或80μm以下,因而造成電性漏電現象及該連接結構1龜裂之情形更為嚴重,故無法朝微小化作設計。
因此,如何克服習知技術中之種種問題,實已成目前亟欲解決的課題。
鑑於上述習知技術之缺失,本發明提供一種基板之連接結構,該基板係具有複數連接墊及外露該些連接墊之絕緣保護層,該連接結構係包括:金屬層,係設於該連接墊之外露表面上並延伸至該絕緣保護層上;以及導電凸塊,係設於該金屬層上,且該導電凸塊之寬度係小於該連接墊之寬度,而各該導電凸塊之間的距離係小於或等於80μm。
本發明復提供一種基板之連接結構之製法,係包括:
提供具有複數連接墊之一基板,該基板表面上形成有外露出該些連接墊之絕緣保護層;形成第一阻層於該絕緣保護層上,且於該第一阻層上形成有第一開口,以令該連接墊及部分該絕緣保護層外露於該第一開口;形成金屬結構於該第一開口中與該第一阻層上;移除該第一阻層上之該金屬結構,令該金屬結構僅位於該第一開口中以作為金屬層,使該金屬層係形成於該連接墊之外露表面上,且該金屬層係延伸至該絕緣保護層上;移除該第一阻層;以及形成導電凸塊於該金屬層上,且該導電凸塊之寬度係小於該連接墊之外露表面之寬度。
前述之製法中,各該導電凸塊之間的距離係小於或等於80μm。
前述之製法中,形成該第一阻層之材質係為鋁、銅或鎳/釩,且該第一阻層之開口係以蝕刻方式形成者。
前述之製法中,形成該導電凸塊之製程係包括:形成第二阻層於該絕緣保護層及該金屬層上,且於該第二阻層上形成有第二開口,以令該金屬層之部分表面外露於該第二開口;形成該導電凸塊於該第二開口中;以及移除該第二阻層。
依上述製程,該第二開口之口徑尺寸係小於該連接墊之外露表面之投影面積。
前述之連接結構及其製法中,該金屬層係包含鈦、銅或鎳。
另外,前述之連接結構及其製法中,該導電凸塊係為
銅柱。
由上可知,本發明之基板之連接結構及其製法,係藉由該金屬層完全覆蓋該連接墊之外露表面,且藉由該第一阻層形成於該金屬結構與該絕緣保護層之間,故當蝕刻移除該金屬結構時,只需移除該第一阻層上之金屬材即可,以有效避免該金屬層以外之金屬材殘留於該絕緣保護層上。因此,當晶片與封裝基板進行覆晶接合後,能避免各連接結構之間的電性漏電現象。
再者,因該金屬層完全覆蓋該連接墊之外露表面,故於後續進行覆晶製程之填膠步驟時,膠材不會流至該連接墊表面,因而有效避免該膠材與該基板間發生脫層,進而避免該連接結構龜裂而影響產品之信賴性的問題。
以下藉由特定的具體實施例說明本發明之實施方式,熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知,本說明書所附圖式所繪示之結構、比例、大小等,均僅用以配合說明書所揭示之內容,以供熟悉此技藝之人士之瞭解與閱讀,並非用以限定本發明可實施之限定條件,故不具技術上之實質意義,任何結構之修飾、比例關係之改變或大小之調整,在不影響本發明所能產生之功效及所能達成之目的下,均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時,本說明書中所引用之如“上”、“第一”、“第二”及“一”等之用語,亦僅為便於敘述
之明瞭,而非用以限定本發明可實施之範圍,其相對關係之改變或調整,在無實質變更技術內容下,當亦視為本發明可實施之範疇。
第2A至2H圖係為本發明之基板30之連接結構2之製法的剖面示意圖。
如第2A圖所示,提供具有連接墊300之一基板30,該基板30表面上形成有外露出該連接墊300之絕緣保護層31。
於本實施例中,該基板30係為半導體元件,可適用於半導體封裝基板結構,亦可運用於第二階段組裝電子元件之一般印刷電路板(Printed Circuit Board),但最佳者係應用於覆晶(Flip Chip)型之半導體晶片或晶圓。
再者,該連接墊300係為銅墊或鋁墊,其作為該基板30內部電路之輸出/入端。
又,該絕緣保護層31形成有開孔310以對應外露出各該連接墊300,且該絕緣保護層31係採用聚亞醯胺層(polyimide layer)等鈍化層(Passivasion layer)材質,其用以覆蓋住該基板30表面,以保護其避免受到外界環境污染及破壞。
另外,有關該基板30之內部結構態樣繁多,並無特別限制,故不詳述,且以下製程中,因各該連接墊300上之製程相同,故僅以其中一處之連接墊300作說明。
如第2B圖所示,形成一第一阻層32於該絕緣保護層31上,且於該第一阻層32上形成有複數第一開口320,以令各該連接墊300及部分該絕緣保護層31對應外露於該些
第一開口320,並使該第一開口320之口徑尺寸D大於該連接墊300之投影面積A(或該連接墊300之外露表面之投影面積A’)。
於本實施例中,係藉由例如濺鍍、蒸鍍、電鍍等物理或化學沈積等方式形成覆蓋該絕緣保護層31及連接墊300之第一阻層32,再移除對應該連接墊300位置之阻層材質,以形成該些第一開口320。
再者,該第一阻層32係與該連接墊300及絕緣保護層31之間具有良好之接合性,故其材質可例如鋁、銅、或鎳/釩金屬等,並以蝕刻方式形成該些第一開口320。
如第2C圖所示,形成一金屬結構21’於該第一開口320中與該第一阻層32上。
於本實施例中,利用例如濺鍍、蒸鍍、電鍍等物理或化學沈積等方式形成該金屬結構21’於該第一阻層32、絕緣保護層31及連接墊300上,且該金屬結構21’可因應實際製程需求加以變化其層數及種類,以作為凸塊底下金屬層結構(Under Bump Metallurgy,UBM),俾提供後續凸塊得以有效接置其上。
再者,該金屬結構21’係可如圖中所示之鈦部21a、銅部21b與鎳部21c(即Ti/Cu/Ni)之三層堆疊結構,且其製程採用之方法係包括濺鍍技術(Sputtering)、蒸鍍技術(Evaporation)及電鍍技術(Plating)等。
如第2D圖所示,圖案化該金屬結構21’以於該第一開口320中定義出形成於該連接墊300上之金屬層21(即UBM
結構),即移除該第一阻層32上之該金屬結構21’,令該金屬層21位於該第一開口320中之絕緣保護層31及連接墊300上。
於本實施例中,該金屬層21之佈設面積B係大於該連接墊300之投影面積A(或該連接墊300之外露表面之投影面積A’)。
再者,該圖案化製程係可先在該金屬結構21’上覆蓋一例如光阻(未圖示),再透過曝光、顯影等方式以於該光阻中形成複數開口區,接著蝕刻移除該開口區中之金屬結構21’,藉以形成位於該連接墊300之外露表面上並延伸至該絕緣保護層31上的該金屬層21。
如第2E圖所示,蝕刻移除該第一阻層32,以完整外露出該UBM結構(即該金屬層21)。
於本實施例中,該金屬層21係包含有一形成於該連接墊300上之黏著層(adhesion Layer,即鈦部21a)、一防止擴散之阻障層(barrier layer,即銅部21b)、及一用以接著凸塊之濕潤層(wettable layer,即鎳部21c),藉以提供接置凸塊、擴散阻障(diffusion barrier)與適當黏著性等功能在凸塊與連接墊300間。
本發明之製法中,該金屬層21之設計係完全覆蓋該連接墊300之外露表面,且藉由該第一阻層32形成於該金屬結構21’與該絕緣保護層31之間,故當蝕刻移除該金屬結構21’時,只需移除該第一阻層32上之金屬材,即可避免UBM結構以外之金屬材料殘留於該絕緣保護層31。因
此,當該基板30與封裝基板(或晶片)進行覆晶接合後而晶片運作時,能避免各連接結構2之間的電性漏電(leakage)現象。
再者,因該金屬層21完全覆蓋該連接墊300之外露表面,故於後續進行覆晶製程之填膠(underfill)步驟時,膠材(圖略)不會流至該連接墊300表面,因而有效避免該膠材與該基板30間發生脫層(peel off),進而避免該連接結構2龜裂(crack)而影響產品之信賴性的問題。
如第2F圖所示,形成第二阻層33於該絕緣保護層31及該金屬層21上,且於該第二阻層33上形成有第二開口330,以令該金屬層21之部分表面外露於該第二開口330。
於本實施例中,該第二開口330之口徑尺寸R(即該金屬層21之外露表面之投影面積)係小於該連接墊300之投影面積A(或該連接墊300之外露表面之投影面積A’)。
如第2G圖所示,以電鍍方式形成導電凸塊22於該第二開口330中之金屬層21之外露表面上,使該導電凸塊22之寬度W係小於該連接墊300之寬度H(或該連接墊300之外露表面之寬度H’)。於本實施例中,該導電凸塊22係為銅柱。
如第2H圖所示,移除該第二阻層33,以完整外露出該連接結構2(即由該金屬層21與該導電凸塊22構成)。
於本實施例中,各該導電凸塊22之間的距離L係為小於或等於80μm。
因此,本發明係提供一種基板30之連接結構2,該基
板30係具有複數連接墊300及外露各該連接墊300之絕緣保護層31,該連接結構2係包括一金屬層21以及一導電凸塊22。
所述之金屬層21係設於該連接墊300之外露表面上並延伸至該絕緣保護層31上,使該金屬層21之佈設面積B大於該連接墊300之投影面積A,又該金屬層21係包含鈦部21a、銅部21b與鎳部21c。
所述之導電凸塊22係為銅柱並設於該金屬層21之鎳部21c上,且該導電凸塊22之寬度W係小於該連接墊300之寬度H,而各該導電凸塊22之間的距離L≦80μm。
綜上所述,本發明之基板之連接結構及其製法,主要藉由該金屬層完全覆蓋該連接墊之外露表面,有效避免金屬材殘留於接點以外之聚亞醯胺上,而能避免產品信賴性及電性功能不佳等問題,且能避免脫層問題。
再者,本發明之基板之連接結構及其製法,於細間距之設計下,例如該導電凸塊之間距係為80μm以下,仍有效避免上述習知技術之問題。
上述實施例係用以例示性說明本發明之原理及其功效,而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下,對上述實施例進行修改。因此本發明之權利保護範圍,應如後述之申請專利範圍所列。
1,2‧‧‧連接結構
11,21‧‧‧金屬層
11a,21a‧‧‧鈦部
11b,21b‧‧‧銅部
11c,21c‧‧‧鎳部
12,22‧‧‧導電凸塊
13‧‧‧銲錫材料
21’‧‧‧金屬結構
30‧‧‧基板
300‧‧‧連接墊
31‧‧‧絕緣保護層
310‧‧‧開孔
32‧‧‧第一阻層
320‧‧‧第一開口
33‧‧‧第二阻層
330‧‧‧第二開口
D,R‧‧‧口徑尺寸
A,A’‧‧‧投影面積
B‧‧‧佈設面積
W,H,H’‧‧‧寬度
L‧‧‧距離
第1圖係為習知基板之連接結構的剖視示意圖;以及
第2A至2H圖係為本發明基板之連接結構之製法的剖面示意圖。
2‧‧‧連接結構
21‧‧‧金屬層
22‧‧‧導電凸塊
30‧‧‧基板
300‧‧‧連接墊
31‧‧‧絕緣保護層
L‧‧‧距離
Claims (11)
- 一種基板之連接結構,該基板係具有複數連接墊及外露該些連接墊之絕緣保護層,該連接結構係包括:金屬層,係設於該連接墊之外露表面上並延伸至該絕緣保護層上;以及導電凸塊,係設於該金屬層上,且該導電凸塊之寬度係小於該連接墊之寬度,而各該導電凸塊之間的距離係小於或等於80μm。
- 如申請專利範圍第1項所述之基板之連接結構,其中,該金屬層係包含鈦、銅或鎳。
- 如申請專利範圍第1項所述之基板之連接結構,其中,該導電凸塊係為銅柱。
- 一種基板之連接結構之製法,係包括:提供具有複數連接墊之一基板,該基板表面上形成有外露出該些連接墊之絕緣保護層;形成第一阻層於該絕緣保護層上,且於該第一阻層上形成有第一開口,以令該連接墊及部分該絕緣保護層外露於該第一開口;形成金屬結構於該第一開口中與該第一阻層上;移除該第一阻層上之該金屬結構,令該金屬結構僅位於該第一開口中以作為金屬層,使該金屬層係形成於該連接墊之外露表面上,且該金屬層係延伸至該絕緣保護層上;移除該第一阻層;以及 形成導電凸塊於該金屬層上,且該導電凸塊之寬度係小於該連接墊之外露表面之寬度。
- 如申請專利範圍第4項所述之基板之連接結構之製法,其中,形成該第一阻層之材質係為鋁、銅或鎳/釩。
- 如申請專利範圍第4項所述之基板之連接結構之製法,其中,該第一阻層之開口係以蝕刻方式形成者。
- 如申請專利範圍第4項所述之基板之連接結構之製法,其中,該金屬層係包含鈦、銅或鎳。
- 如申請專利範圍第4項所述之基板之連接結構之製法,其中,該導電凸塊係為銅柱。
- 如申請專利範圍第4項所述之基板之連接結構之製法,其中,各該導電凸塊之間的距離係小於或等於80μm。
- 如申請專利範圍第4項所述之基板之連接結構之製法,其中,形成該導電凸塊之製程係包括:形成第二阻層於該絕緣保護層及該金屬層上,且於該第二阻層上形成有第二開口,以令該金屬層之部分表面外露於該第二開口;形成該導電凸塊於該第二開口中;以及移除該第二阻層。
- 如申請專利範圍第10項所述之基板之連接結構之製法,其中,該第二開口之口徑尺寸係小於該連接墊之外露表面之投影面積。
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TW101142584A TWI473227B (zh) | 2012-11-15 | 2012-11-15 | 基板之連接結構及其製法 |
CN201210482795.5A CN103811442B (zh) | 2012-11-15 | 2012-11-23 | 基板的连接结构的制法 |
US13/729,710 US20140131072A1 (en) | 2012-11-15 | 2012-12-28 | Connection structure for a substrate and a method of fabricating the connection structure |
US14/683,716 US9666548B2 (en) | 2012-11-15 | 2015-04-10 | Method of fabricating connection structure for a substrate |
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CN107087341B (zh) * | 2016-01-28 | 2019-03-08 | 庆鼎精密电子(淮安)有限公司 | 电路板及其制作方法 |
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US6015652A (en) * | 1998-02-27 | 2000-01-18 | Lucent Technologies Inc. | Manufacture of flip-chip device |
US7902679B2 (en) * | 2001-03-05 | 2011-03-08 | Megica Corporation | Structure and manufacturing method of a chip scale package with low fabrication cost, fine pitch and high reliability solder bump |
US6740577B2 (en) * | 2002-05-21 | 2004-05-25 | St Assembly Test Services Pte Ltd | Method of forming a small pitch torch bump for mounting high-performance flip-flop devices |
TW582105B (en) * | 2003-03-05 | 2004-04-01 | Advanced Semiconductor Eng | Wafer surface processing |
TWI259572B (en) * | 2004-09-07 | 2006-08-01 | Siliconware Precision Industries Co Ltd | Bump structure of semiconductor package and fabrication method thereof |
US20090160053A1 (en) * | 2007-12-19 | 2009-06-25 | Infineon Technologies Ag | Method of manufacturing a semiconducotor device |
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US20110227216A1 (en) * | 2010-03-16 | 2011-09-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Under-Bump Metallization Structure for Semiconductor Devices |
US20120009777A1 (en) * | 2010-07-07 | 2012-01-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | UBM Etching Methods |
US8598030B2 (en) * | 2010-08-12 | 2013-12-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Process for making conductive post with footing profile |
TWI462199B (zh) * | 2010-12-21 | 2014-11-21 | Chipmos Technologies Inc | 凸塊結構及其製作方法 |
US9013037B2 (en) * | 2011-09-14 | 2015-04-21 | Stmicroelectronics Pte Ltd. | Semiconductor package with improved pillar bump process and structure |
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CN103811442A (zh) | 2014-05-21 |
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US20140131072A1 (en) | 2014-05-15 |
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