TW201413881A - 具有柱體的半導體封裝基板及其相關方法 - Google Patents

具有柱體的半導體封裝基板及其相關方法 Download PDF

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Publication number
TW201413881A
TW201413881A TW102130049A TW102130049A TW201413881A TW 201413881 A TW201413881 A TW 201413881A TW 102130049 A TW102130049 A TW 102130049A TW 102130049 A TW102130049 A TW 102130049A TW 201413881 A TW201413881 A TW 201413881A
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Prior art keywords
circuit pattern
substrate
dielectric layer
dielectric
portions
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TW102130049A
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English (en)
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TWI549239B (zh
Inventor
Tien-Szu Chen
Kuang-Hsiung Chen
Sheng-Ming Wang
Hsiang-Ming Feng
Yan-Hua Kuo
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Advanced Semiconductor Eng
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Publication of TWI549239B publication Critical patent/TWI549239B/zh

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    • H—ELECTRICITY
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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Abstract

一種具有柱體的半導體封裝基板及其相關方法。基板包括一第一介電層、一第一電路圖案、數個柱體與一第二電路圖案。第一介電層具有相對的一第一介電表面與一第二介電表面。第一電路圖案埋於第一介電層中，並定義數個彎曲的走線表面。柱體各具有一外表面與一曲基表面，其中外表面用以製造外部的電性連接，曲基表面鄰接走線表面中對應的一個。第二電路圖案位在第一介電層的第二介電表面上，並電性連接至第一電路圖案。

Description

具有柱體的半導體封裝基板及其相關方法
本實施例是有關於一種具有柱體的半導體封裝基板及其相關的方法
一些半導體封裝基板包括數個柱體，其用以連接一半導體晶粒之數個焊料凸塊至基板。在迴焊製程之後，焊料接點形成在晶粒與柱體之間，使得晶粒黏合至柱體，並穩固之間的電性連接。柱體可以電鍍法(electroplating)形成。然而，電渡槽中無法預料且多變的電鍍參數常導致過多(over-plating)或過少(under-plating)的電鍍，這會造成電鍍柱體的頂表面為非共平面。缺乏共平面性會負面地影響封裝之後焊料接點的可靠度。是微間距(fine pitch)焊料凸塊、晶圓級封裝(wafer level packaging；WLP)、及大尺寸基板對於這問題特別敏感。缺乏共平面性會引起不均勻(non-uniform)的電流密度分佈，其在微尺寸圖案上特別嚴重。此一般不均勻的電流密度分佈不只是被一個因素影響，其被各種的電鍍參數影響，其中電鍍參數由電鍍槽設計、化學添加物、電流密度的大小、使用的電流種類、陰極與陽極之間的距離、擾動方式、化學維持性、預清理溶液、圖案的結構、配置與體積、高的長寬比(aspect ratio)、等所構成。跨過整個基板的高度誤差很難控制在5μm之內，特別是當需要添加平整劑(leveling agent)、浸潤劑(wetting agent)、或光澤劑(brightener)至電鍍槽時。
本實施例其中之一是以關於一基板。基板包括一第 一介電層，其具有相對的一第一介電表面與一第二介電表面。基板更包括一第一電路圖案埋於第一介電層中。第一電路圖案包括數個走線，其定義從第一介電表面露出的數個走線表面。走線表面包括數個曲部分，其凹低於第一介電表面。基板更包括數個柱體。柱體各具有一曲基表面鄰接走線表面之曲部分中對應的一個，藉此定義一曲界面於各個柱體與走線表面之曲部分中對應的一個之間。
本實施例其中之另一是以關於一基板。基板包括一 第一介電層，其具有相對的一第一介電表面與一第二介電表面。 基板更包括一第一電路圖案埋於第一介電層中。第一電路圖案包括數個走線，其定義從第一介電表面露出的數個走線表面。走線表面定義從第一介電表面向外延伸的數個凹部分。基板更包括數個柱體。柱體各具有一凸基表面鄰接走線表面之凹部分中對應的一個，藉此定義一凹形/凸形的界面在各個柱體與走線表面中對應的一個之間。
本實施例其中之再另一是以關於製造一基板的一方 法。方法包括形成一圖案化層於一載體上，圖案化層定義數個開口。方法更包括形成數個柱體的第一柱部分在圖案化層中的開口中。方法更包括形成一導電膜覆蓋柱體的第一柱部分與圖案化層。方法更包括形成一第一電路圖案在圖案化層上，第一電路圖案定義數個走線表面。方法更包括形成一第一介電層於第一電路圖案與圖案化層上。方法更包括形成數個第一開口在第一介電層中。方法更包括形成數個導電穿孔在第一介電層中，與一第二電路圖案在第一介電層上，導電穿孔位在第一介電層中的第一開口中，第一電路圖案經由導電穿孔電性連接至第二電路圖案。方法更包括形成一第二介電層覆蓋第二電路圖案的數個部分，並定義數個第二開口，第二電路圖案包括被第二介電層中的第二開口所露出的數個接觸墊。方法更包括移除載體。方法更包括移除圖案化層。方法更包括移除導電膜未被第一柱部分覆蓋的數個部分， 其中導電膜剩餘的部分形成柱體的數個第二柱部分。
為了對本發明之上述及其他方面有更佳的瞭解，下文特舉較佳實施例，並配合所附圖式，作詳細說明如下：
100、200‧‧‧半導體封裝
102、202‧‧‧基板
104、204‧‧‧晶粒
106‧‧‧封裝體
108、208、308、408‧‧‧第一介電層
110、210、310、410‧‧‧第一電路圖案
112、212‧‧‧柱體
114、214、314、414‧‧‧第二電路圖案
116、216、316、416‧‧‧第二介電層
118、218、318、418‧‧‧導電穿孔
120、220‧‧‧第一介電表面
122、222、322、422‧‧‧第二介電表面
124、224、324、424‧‧‧走線
126、226‧‧‧走線表面
128、228‧‧‧基表面
130、132、138、230、232、330、332、430、432、1016、1018、2016、2018‧‧‧開口
134、234、334、434‧‧‧第一柱部分
136、236‧‧‧第二柱部分
140‧‧‧電性接觸
142‧‧‧導電凸塊
144‧‧‧底膠層
146、246‧‧‧外表面
148、248‧‧‧側壁
250‧‧‧側表面
252‧‧‧頂端
1002、2002‧‧‧載體
1004‧‧‧下表面
1006‧‧‧上表面
1008、1010、2008、2010‧‧‧導電層
1012、1014、2012、2014‧‧‧圖案化層
1020、1022、2020、2022‧‧‧基表面
1024、1026、1034、1038、1040、1048、1050、2024、2026、2034、2038、2040、2048、2050‧‧‧導電膜
1028、1030、2028、2030‧‧‧薄膜
1032、1036、2032、2036‧‧‧介電層
1042、1046、2042、2046‧‧‧開口
1044、2044‧‧‧圖案化導電膜
2052、2054‧‧‧側壁
H1、H2‧‧‧高度
W1、W3‧‧‧第一最大寬度
W2、W4‧‧‧第二最大寬度
第1圖為根據本實施例其中之一的半導體封裝的剖面圖；第2圖為根據本實施例其中之另一的半導體封裝的剖面圖；第3A圖至第3N圖繪示一實施例中第1圖顯示之基板的製造方法；以及第4A圖至第4L圖繪示一實施例中第2圖顯示之基板的製造方法。
請參照第1圖，其繪示根據本實施例其中之一的一半導體封裝100的剖面圖。半導體封裝100包括一基板102、一晶粒104與一封裝體106。
基板102包括一第一介電層108、一第一電路圖案110、數個柱體112、一第二電路圖案114、與一第二介電層116。第一電路圖案110經由數個導電穿孔118電性連接至第二電路圖案114。雖然基板102繪示出只包括兩層電路圖案，在其他實施例中，基板102可包括任何層數的電路圖案，例如三層或更多層。
第一介電層108具有一第一介電表面120與一第二介電表面122。第一介電表面120是相對於第二介電表面122。舉例來說，第一介電層108可由用以提高硬度的纖維強化樹脂材料及/或預浸體(prepreg)，或任何其他的材料所製得。舉例來說，纖維可為玻璃、或芳綸(aramid)、或任何其他的材料。可以纖維強化以用於壓合介電材料中的樹脂材料的例子包括ABF膜(Ajinomoto build-up film)、雙順丁烯二酸醯亞胺-三氮雜苯(bismaleimide triazine；BT)、預浸體、聚醯亞胺(polyimide；PI)、液晶聚合物(liquid crystal polymer；LCP)、環氧化合物(epoxy)、及其他樹脂材料。
第一電路圖案110埋在第一介電層108中。請參照 第1圖的放大插圖，第一電路圖案110包括數個走線124。走線124埋在第一介電層108中，除了數個彎曲的走線表面126從第一介電表面120露出。走線表面126凹低於第一介電表面120。
柱體112各具有一外表面146與一曲基表面128， 其中外表面146用作外部的電性連接件(例如連接至一半導體晶片中的其他電性連接件)，曲基表面128接觸走線表面126中對應的一個，走線表面126也是曲表面。換言之，柱體112與走線124之間具有一曲界面，其具有凸形的柱體基表面128與凹形的走線表面126。
各個柱體112更包括一第一柱部分134與一第二柱 部分136。第一柱部分134具有一第一最大寬度W1。第二柱部分136具有一第二最大寬度W2。第二最大寬度W2可大於第一最大寬度W1。因此，曲基表面128的邊緣是位在第一柱部分134橫向的外側。
由於柱體112的外表面146為自實質上平坦的硬質 載體上的一導電膜的相同表面形成，因此柱體112的外表面146具有高的共平面度，以下將進一步詳述。當基板102經由柱體112電性連接至晶粒104時，高的共平面度會增進半導體封裝100的可靠度。一些實施例中，柱體112之外表面146的共平面度為±3μm。換言之，柱體112的高度H1離預期且期望尺寸的偏差值是在3μm的範圍之內，其中高度H1是定義為柱體112之外表面146與第一介電層108之第一介電表面120之間的距離。在這些實施例中，高度H1中最大值與最小值之間的差值為6μm或更小。換言之，高度H1之間的差異(variation)為6μm或更小。或者，高度H1中最大值與最小值之間的差值可小於預期且期望尺寸的10%。柱體112的材料可為銅或其他任意的材料。
第二電路圖案114配置在第一介電層108的第二介 電表面122上。第二介電層116部分地覆蓋第二電路圖案114。 第二介電層116定義出數個開口130，其露出第二電路圖案114的數個部分以形成數個接觸墊132。第二介電層116可例如為綠漆，或任何其他的材料。接觸墊132可用作半導體封裝100連接外部的電性連接件，例如連接至另一半導體封裝，或連接至電路板上其他構件的電性連接件。舉例來說，一電性接觸140，例如焊料球，可電性連接至並配置鄰近於接觸墊132中對應的一個。 導電穿孔118各從第一電路圖案110穿過第一介電層108中開口138對應的一個而延伸至第二電路圖案114。導電穿孔118各電性連接第一電路圖案110至第二電路圖案114。第一電路圖案110的走線124電性連接各個柱體112至導電穿孔118中對應的一個，並至接觸墊132中對應的一個。
晶粒104可經由數個熔融的導電凸塊142，或藉由 任何其他的技術，電性連接至柱體112。熔融的導電凸塊142可由導電材料，例如焊料或其他任何的材料製得。底膠層144可形成在晶粒104與基板102之間。
封裝體106實質上覆蓋或包覆晶粒104、第一電路 圖案110、柱體112與熔融的導電凸塊142，以提供機械穩定性，與防止氧化、濕氣、及其他環境條件的保護作用。封裝體106可由封裝材料製得，其可包括例如酚醛基樹脂(Novolac-based resin)、環氧基樹脂(epoxy-based resin)、矽基樹脂(silicone-based resin)或其他適當之包覆劑。封裝體106也可包括適當的填充劑(filler)，例如是粉狀的二氧化矽(SiO2)，或任何其他的填充劑。
第2圖繪示根據本實施例其中之另一的一半導體封 裝200的剖面圖。半導體封裝200相似於參照第1圖說明的半導體封裝100。因此，在此僅討論半導體封裝200不同於半導體封裝100的部分。請參照第2圖的放大插圖，柱體212各具有一外表面246與一曲基表面228，其中外表面246用作外部的電性連接(例如連接至一半導體晶片中的其他電性連接件)，曲基表面228接觸走線224的走線表面226中對應的一個。換言之，柱體212 與走線224之間具有一曲界面，其具有凸形的柱體基表面228與凹形的走線表面226。相較於第1圖的半導體封裝100，走線表面226提升高過第一介電表面220。由各個柱體基表面228/走線表面226定義出的曲面其頂端252實質上位於第一介電層208定義的平面中。
柱體212更包括一第一柱部分234與一第二柱部分 236。第二柱部分236各具有一凸出部分248，其從曲基表面228的外邊緣凸出並圍繞走線224的凹部分。凸出部分248具有一側表面250鄰近第二柱部分236的曲基表面228。側表面250與曲基表面228之間夾有一銳角。第一柱部分234具有一第一最大寬度W3。第二柱部分236具有一第二最大寬度W4。第一最大寬度W3與第二最大寬度W4實質上相等。曲基表面228的剖面寬度小於第一柱部分234的剖面寬度，使得曲基表面228的邊緣是放射狀地坐落在第一柱部分234的內部。
請參照第2圖，由於柱體212為自實質上平坦的硬 質載體上的一導電膜的相同表面形成，因此柱體212具有高的共平面度，以下將進一步詳述。當基板202經由柱體212電性連接至晶粒204時，高的共平面度會增進半導體封裝200的可靠度。 一些實施例中，柱體112的高度容許公差如同參照第1圖之半導體封裝100所述。柱體212的材料可為銅或任何其他的材料。
基板102與基板202並不限於如第1圖與第2圖所 示的覆晶接合。其他實施例中，基板102與基板202可用於其他應用，例如打線接合應用或任何其他的應用。
第3A圖至第3N圖繪示根據本實施例其中之一的製 造基板的方法。為了方便表示，以下步驟是參照第1圖之半導體封裝100的基板102做說明。
第3A圖繪示實質上平坦的硬質載體1002。一些實 施例中，載體1002可包括一核心層(未顯示)介於兩個載體導電層(未顯示)之間，載體導電層貼附至核心層。各個載體導電層可由 金屬、金屬合金、具有金屬或金屬合金散佈其中的基質、或其他合適的電導性材料形成。舉例來說，各個載體導電層可包括由銅或銅合金形成的金屬箔。金屬箔的厚度可介於約10μm至約30μm的範圍，例如介於約15μm至約25μm的範圍。
載體1002具有一下表面1004與一上表面1006。一 導電層1008配置鄰近於下表面1004，且一導電層1010配置鄰近於上表面1006。導電層1008、1010各可由金屬、金屬合金、具有金屬或金屬合金散佈其中的基質、或任何其他合適的電導性材料形成。舉例來說，導電層1008、1010可包括形成自銅或銅合金的可離型式(releasable)金屬箔。導電膜1008、1010可藉由一離型層(未顯示)貼附至載體1002。一些實施例中，離型層為一黏著層，其可為有機或無機的，例如膠帶。膠帶可使用單面或雙面膠帶。膠帶將構件穩固在彼此間恰當的間隔，並使得之後進行的步驟能對配置鄰近載體1002的構件實行。各個導電層1008、1010的厚度可介於約2μm至約20μm的範圍，例如約3μm至約5μm的範圍，約3μm至約10μm的範圍，約10μm至約20μm的範圍，與約15μm至約20μm的範圍。
請參照第3B圖，形成圖案化層1012、1014分別鄰 近於導電膜1008、1010。圖案化層1012、1014定義出數個開口1016、1018，其露出導電膜1008、1010。圖案化層1012、1014可以光阻層形成，光阻層可為乾膜光阻、或其他類型的可圖案化層或介電層。光阻層中被選擇的部分可被光影像化(photoimaged)並顯影(developed)，藉此形成開口1016、1018。光阻層可利用光罩(未顯示)光化學性地(photochemically)被定義出。相較於用以形成開口1016、1018於圖案化層1012、1014中的其他方法，光影像化及顯影可具有成本較低、製程時間縮減的優勢，然可使用任何的技術。產生的開口1016、1018可具有任何的形狀，包括柱形(cylindrical)，例如圓柱形(circular cylindrical)、橢圓柱形(elliptical cylindrical)、方柱形(square cylindrical)、或矩柱形 (rectangular cylindrical)，或非柱形(non-cylindrical shape)，例如錐形(cone)、漏斗形(funnel)，或任何一頭逐漸變細的(tapered)形狀。
請參照第3C圖，填充一導電材料至圖案化層1012、 1014的開口1016、1018中，以形成第一柱部分134、334。於此實施例中，是藉由電鍍法將導電材料過度填充開口1016、1018，使得形成的第一柱部分134、334突出自圖案化層1012、1014，並形成曲基表面1020、1022(例如以上所述的凸形的表面)。第一柱部分134、334可以金屬、金屬合金、具有金屬或金屬合金散佈於其中的基質，或任何其他合適的電導性材料。舉例來說，第一柱部分134、334可包括一個或更多個銅或銅合金層。
請參照第3D圖，分別形成兩個導電膜1024、1026 在第一柱部分134、334與圖案化層1012、1014上。一些實施例中，導電膜1024、1026可以濺鍍的方式形成。藉由過度填充開口1016、1018，可減少開口1016、1018中空隙(voids)或死角(dead spaces)發生的機會，而藉此避免斷路(open circuit)問題。導電膜1024、1026可由金屬、金屬合金、具有金屬或金屬合金散佈其中的基質、或任何其他合適的導電性材料形成。舉例而言，導電膜1024、1026可包括包括一個或更多個銅或銅合金層。在進一步的示例中，導電膜1024、1026可為一濺鍍銅膜。
請參照第3E圖，形成第一電路圖案110、310於導 電膜1024、1026上。第一電路圖案110、310包括走線124，324，其接觸導電膜1024、1026並共形於導電膜1024、1026，以形成曲界面。一些實施例中，第一電路圖案110、310的形成方法包括形成數個圖案化的光阻層，其定義露出導電膜1024、1026數個部分的數個開口，然後以導電性材料填充圖案化的光阻層中的開口(例如使用導電膜1024、1026作為陰極的電鍍方法)，並然後移除圖案化的光阻層。或者，第一電路圖案110、310的形成方法可包括形成數個導電材料層(未顯示)覆蓋導電膜1024、1026，然後 形成數個光阻圖案(未顯示)其定義露出導電材料層之數個部分的數個開口，然後利用蝕刻方法移除導電材料層被光阻圖案之開口露出的數個部分，其中導電材料層留下的數個部分形成第一電路圖案110、310，且然後移除光阻層。第一電路圖案110、310可由金屬、金屬合金、具有金屬或金屬合金散佈其中的基質、或任何其他合適的導電性材料形成，且可為濺鍍或電鍍法形成，並可為圖案化的。一些實施例中，第一電路圖案110、310是由銅形成。
請參照第3F圖，壓合一薄膜1028在第一電路圖案 110與導電膜1024上，並壓合一薄膜1030在第一電路圖案310與導電膜1026上。薄膜1028可包括一介電層1032壓合在第一電路圖案110與導電膜1024上，與一導電膜1034覆蓋介電層1032。薄膜1030可包括一介電層1036壓合在第一電路圖案310與導電膜1026上，與一導電膜1038覆蓋介電層1036。導電膜1034、1038可以類似導電膜1008、1010的材料形成。
介電層1032、1036可由用以提高硬度的纖維強化樹 脂材料及/或預浸體(prepreg)製得。纖維可為玻璃、或芳綸(aramid)、或任何其他的材料。介電層1032、1036可由利用纖維強化的一薄膜形成，以增強介電材料。可利用纖維強化以用於壓合介電材料中的樹脂材料的例子包括ABF膜(Ajinomoto build-up film)、雙順丁烯二酸醯亞胺-三氮雜苯(bismaleimide triazine；BT)、預浸體、聚醯亞胺(polyimide；PI)、液晶聚合物(liquid crystal polymer；LCP)、環氧化合物(epoxy)、及其他樹脂材料。一些實施例中，介電層1032、1036是預先形成(preformed)，以在對應第一電路圖案110、310的位置定義出數個開口。
或者，介電層1032、1036可以未強化、低硬度材料 形成，例如綠漆(solder mask；solder resist)，樹脂材料包括但不限於ABF膜、BT、預浸體、PI、LCP、及環氧化合物、或任何其他種類的可圖案化層或介電層。此材料可利用任何塗佈技術提供，例如印刷、旋塗(spinning)、或噴塗(spraying)。
請參照3G圖，接著，移除第3F圖中所示之介電層 1032與薄膜1028之導電膜1034的數個部分，以形成第一介電層108與一圖案化導電膜1040，其定義出露出第一電路圖案110數個部分的數個開口1042。此外，移除第3F圖所示之介電層1036與薄膜1030之導電膜1038的數個部分，以形成第一介電層308與一圖案化導電膜1044，其定義出露出第一電路圖案310數個部分的數個開口1046。一些實施例中，開口1046可在導電膜1040、1044中雷射鑽出孔洞，並對雷射鑽出之孔洞所露出的介電層1032、1036(第3F圖)進行電漿蝕刻而形成。或者，開口1046可以化學蝕刻、或機械鑽孔的方式形成。產生的開口1042、1046可具有任何的形狀，包括柱形，例如圓柱形、橢圓柱形、方柱形、或矩柱形，或非柱形，例如錐形、漏斗形，或任何一頭逐漸變細的形狀。產生之開口的側邊界(lateral boundaries)可為彎曲或結構粗操的(roughly textured)。
請參照第3H圖，形成一導電材料在第一介電層 108、308中的開口1042、1046與圖案化導電膜1040、1044(第3G圖)中，以形成數個導電穿孔118、318與數個導電膜1048、1050，導電膜1048、1050從第一介電層108、308之第二介電表面122、322上的導電穿孔118、318延伸。導電膜1048、1050可包括第3G圖中所示的圖案化導電膜1040、1044，或更包括形成在第3G圖中所示之圖案化導電膜1040、1044上的額外的導電材料。一些實施例中，導電穿孔118、318與導電膜1048、1050的形成方式為，利用無電鍍法形成數個導電材料(未顯示)在第3G圖所示之被開口1042、1046露出的第一介電層108、308其側壁上，與圖案化導電膜1040、1044上，並然後填充另外數個導電材料在開口1042、1046中。一些實施例中，導電穿孔118、318與導電膜1048、1050可由金屬、金屬合金、具有金屬或金屬合金散佈其中的基質、或任何其他合適的導電性材料形成。舉例來說，導電穿孔118、318與導電膜1048、1050可由銅形成。
然後，圖案化導電膜1048以形成一第二電路圖案 114，其電性連接至導電穿孔118，如第3I圖所示。此外，圖案化第3H圖所示之導電膜1050，以形成一第二電路圖案314，其電性連接至導電穿孔318。第二電路圖案114、314的形成方式可為，形成數個光阻層(未顯示)，其定義出露出第3H圖所示之導電膜1048、1050數個部分的數個開口，然後利用蝕刻方式移除導電膜1048、1050被光阻層中之開口露出的部分，其中導電膜1048、1050留下的部分形成第3I圖所示之第二電路圖案114、314，並然後移除光阻層。雖然以上所述的第二電路圖案114、314是以減成法(subtractive method)形成，然其亦可以半加成法(semi-additive process)形成。
請參照第3J圖，形成一第二介電層116於第一介電 層108的第二介電表面122上與第二電路圖案114上。第二介電層116包括數個開口130露出第二電路圖案114的數個部分以形成數個接觸墊132。形成一第二介電層316在第一介電層308的第二介電表面322上，與第二電路圖案314上。第二介電層316定義出數個開口330露出第二電路圖案314的數個部分以形成數個接觸墊332。第二介電層116、316可以綠漆或任何其他種類的介電材料形成。
請參照第3K圖，移除載體1002以露出導電膜1008、1010。然後，移除導電層1008以露出第一柱部分134的外表面146與圖案化層1012，如第3L圖所示。移除製程可包括例如蝕刻，或任何其他技術。接著，移除圖案化層1012以露出第一柱部分134的數個側壁148，及導電膜1024位在第一柱部分134之側壁148外側的數個部分，如第3M圖所示。移除製程可包括例如剝除(stripping)，或任何其他的技術。接著，移除如第3M圖所示之導電膜1024位在第一柱部分134之側壁148外側的部分，以形成基板102的數個第二柱部分136，如第3N圖所示。移除製程可包括例如蝕刻，或任何其他的技術。
第4A圖至第4L圖繪示根據本實施例其中另一個之 製造基板的方法。為了方便表示，以下步驟是參照第2圖之半導體封裝200的基板202做說明。一些實施例中，第4A圖所示之階段之前的步驟相似於第3A圖及第3B圖。
請參照第4A圖，於此實施例中，一導電材料形成 在圖案化層2012、2014中的各個開口2016、2018中，以形成第一柱部分234、434。圖案化層2012、2014各個側壁2052、2054的數個部分並未被導電材料覆蓋。第一柱部分234、434可以電鍍或任何其他製程形成。第一柱部分234、434可以類似於第一柱部分134、334(第3C圖)的材料形成。
請參照第4B圖，分別形成兩個導電膜2024、2026 在圖案化層2012、2014與第一柱部分234、434的曲基表面2020、2022上。一些實施例中，導電膜2024、2026可以無電鍍的方式形成，使得導電膜2024能夠連續地形成在圖案化層2012之側壁2052與第一柱部分234之曲基表面2020之間的角落空間中，及圖案化層2014之側壁2054與第一柱部分434之曲基表面2022之間的角落空間。在此手法中，可避免死角問題發生。導電膜2024、2026可由金屬、金屬合金、具有金屬或金屬合金散佈其中的基質、或任何其他合適的導電性材料形成。舉例來說，導電膜2024、2026可包括一或更多個銅或銅合金層。
請參照第4C圖，形成第一電路圖案210、410在導 電膜2024、2026上。第一電路圖案210、410包括數個走線224、424，其接觸導電膜2024、2026。第一電路圖案210、410的形成方法可類似於參照第3E圖所述之第一電路圖案110、310的形成方法。
請參照第4D圖，形成薄膜2028、2030。薄膜2028 可包括一介電層2032與一導電膜2034。薄膜2030可包括一介電層2036與一導電膜2038。薄膜2028、2030的形成方法可類似參照第3F圖所述之薄膜1028、1030的形成方法。
接著，移除介電層2032與薄膜2028之導電膜 2034(第4D圖)的數個部分，以形成一第一介電層208與一圖案化導電膜2040其定義出露出第一電路圖案210數個部分的數個開口2042，如第4E圖所示。此外，移除介電層2036與薄膜2030之導電膜2038(第4D圖)的數個部分，以形成一第一介電層408與一圖案化導電膜2044其定義出露出第一電路圖案410數個部分的數個開口2046。第一介電層208、408與圖案化導電膜2040、2044的形成方法可類似於參照第3G圖所述之第一介電層108、308與圖案化導電膜1040、1044的形成方法。
請參照第4F圖，形成一導電材料於第一介電層 208、408與圖案化導電膜2040，2044的開口2042、2046(第4E圖)中，以形成導電穿孔218、418與導電膜2048、2050，其中導電膜2048、2050是從第一介電層208、408之第二介電表面222、422上的導電穿孔218、418延伸。導電穿孔218、418與導電膜2048、2050的形成方法可類似於先前參照第3H圖所述之導電穿孔118、318與導電膜1048、1050的形成方法。
接著，圖案化導電膜2048，以形成一第二電路圖案 214，其電性連接至導電穿孔218，如第4G圖所示。再者，圖案化導電膜2050(第4F圖)以形成一第二電路圖案414，其電性連接至導電穿孔418。第二電路圖案214、414的形成方法可類似於參照第3I圖所述之第二電路圖案114、314的形成方法。
請參照第4H圖，形成一第二介電層216在第一介 電層208的第二介電表面222上，與第二電路圖案214上。第二介電層216定義露出第二電路圖案214數個部分的數個開口230，以形成數個接觸墊232。形成一第二介電層416在第一介電層408的第二介電表面422上，與第二電路圖案414上。第二介電層416定義露出第二電路圖案414數個部分的數個開口430，以形成數個接觸墊432。第二介電層216、416可以綠漆或其他任何種類的介電材料形成。
請參照第4I圖，移除載體2002以露出導電層2008、 2010。接著，移除導電層2008以露出第一柱部分234的外表面246與圖案化層2012，如第4J圖所示。移除製程可包括例如蝕刻，或任何其他的技術。
接著，移除圖案化層2012，以露出第一柱部分234 的側壁248、及導電膜2024位在第一柱部分234外側的數個部分，如第4K圖所示。移除製程可包括例如蝕刻，或任何其他的技術。
接著，移除導電膜2024位在第一柱部分234之側壁 248(第4K圖)外側的部分，以形成數個第二柱部分236，如第4L圖所示。
綜上所述，雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明。本發明所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作各種之更動與潤飾。因此，本發明之保護範圍當視後附之申請專利範圍所界定者為準。
100‧‧‧半導體封裝
102‧‧‧基板
104‧‧‧晶粒
106‧‧‧封裝體
108‧‧‧第一介電層
110‧‧‧第一電路圖案
112‧‧‧柱體
114‧‧‧第二電路圖案
116‧‧‧第二介電層
118‧‧‧導電穿孔
120‧‧‧第一介電表面
122‧‧‧第二介電表面
124‧‧‧走線
126‧‧‧走線表面
128‧‧‧基表面
130、132‧‧‧開口
134‧‧‧第一柱部分
136‧‧‧第二柱部分
138‧‧‧開口
140‧‧‧電性接觸
142‧‧‧導電凸塊
144‧‧‧底膠層
146‧‧‧外表面
H1‧‧‧高度
W1‧‧‧第一最大寬度
W2‧‧‧第二最大寬度

Claims (20)

  1. 一基板，包括：一第一介電層，具有相對的一第一介電表面與一第二介電表面；一第一電路圖案，埋在該第一介電層中，該第一電路圖案包括數個走線，該些走線定義從該第一介電表面露出的走線表面，該些走線表面包括低於該第一介電表面的曲部分；以及數個柱體，各具有一曲基表面鄰接該些走線表面的該些曲部分中對應的一個，藉此在各該些柱體與該些走線表面的該些曲部分中對應的一個之間定義出一曲界面。
  2. 如申請專利範圍第1項所述之基板，更包括一第二電路圖案於該第一介電層的該第二介電表面上，並電性連接至該第一電路圖案。
  3. 如申請專利範圍第2項所述之基板，更包括一第二介電層鄰接該第一介電層的該第二介電表面，並覆蓋部分的該第二電路圖案。
  4. 如申請專利範圍第1項所述之基板，其中該些柱體各個的該曲基表面為凸形的。
  5. 如申請專利範圍第4項所述之基板，其中該些走線表面的該些曲部分各為凹形的。
  6. 如申請專利範圍第1項所述之基板，其中該些柱體各包括互相鄰接的兩個分部。
  7. 如申請專利範圍第1項所述之基板，其中該些柱體各包括一第一柱部分與一第二柱部分，該第一柱部分與該些走線表面中對應的一個係隔開，該第二柱部分配置在該第一柱部分與該些走線表面中對應的該一個。
  8. 如申請專利範圍第7項所述之基板，其中該些第一柱部分各具有一第一寬度，該些第二柱部分各具有一第二寬度，且該第二寬度大於該第一寬度。
  9. 一種基板，包括： 一第一介電層，具有相對的一第一介電表面與一第二介電表面；一第一電路圖案，埋在該第一介電層中，該第一電路圖案包括數個走線，該些走線定義從該第一介電表面露出的走線表面，該些走線表面定義從該第一介電表面延伸出的凹部分；以及數個柱體，各具有一凸基表面鄰接該些走線表面之該些凹部分中對應的一個，藉此在各該些柱體與該些走線表面中對應的一個之間定義出一凹/凸界面。
  10. 如申請專利範圍第9項所述之基板，其中該些凹部分各個的頂端實質上位於該第一介電表面的平面中。
  11. 如申請專利範圍第9項所述之基板，更包括一第二電路圖案在該第一介電層的該第二介電表面上，並電性連接至該第一電路圖案。
  12. 如申請專利範圍第11項所述之基板，更包括一第二介電層鄰接該第一介電層的該第二介電表面，並覆蓋該第二電路圖案的數個部分。
  13. 如申請專利範圍第9項所述之基板，其中該些柱體各包括互相鄰接的兩個分部。
  14. 如申請專利範圍第9項所述之基板，其中該些柱體各包括一第一柱部分與一第二柱部分，該第一柱部分與該些走線表面中對應的一個係隔開，該第二柱部分配置在該第一柱部分與該些走線表面中該對應的一個之間。
  15. 如申請專利範圍第14項所述之基板，其中該些第二柱部分各包括一導電膜。
  16. 如申請專利範圍第14項所述之基板，其中該些第二柱部分各包括一側表面，該側表面與該曲基表面之間夾有一銳角。
  17. 一種製造基板的方法，包括：形成一圖案化層於一載體上，該圖案化層定義數個開口；形成數個柱體的數個第一柱部分在該圖案化層的該些開口中； 形成一導電膜覆蓋該些柱體的該些第一柱部分與該圖案化層；形成一第一電路圖案在該圖案化層上，該第一電路圖案定義數個走線表面；形成一第一介電層在該第一電路圖案與該圖案化層上；形成數個第一開口於該第一介電層中；形成數個導電穿孔在該第一介電層中，與一第二電路圖案在該第一介電層上，該些導電穿孔位在該第一介電層的該些第一開口中，該第一電路圖案經由該些導電穿孔電性連接至該第二電路圖案；形成一第二介電層覆蓋該第二電路圖案的數個部分，且定義數個第二開口，該第二電路圖案包括數個接觸墊，該些接觸墊自該第二介電層中的該些第二開口露出；移除該載體；移除該圖案化層；以及移除該導電膜未被該些第一柱部分覆蓋的數個部分，其中該導電膜留下的部分形成該些柱體的數個第二柱部分。
  18. 如申請專利範圍第17項所述之製造基板的方法，其中該些柱體各具有一曲基表面，該曲基表面在一曲界面處鄰接該些走線表面中對應的一個。
  19. 如申請專利範圍第18項所述之製造基板的方法，其中該些第一柱部分填充超過該圖案化層中該些開口中對應的數個，以形成該些曲基表面。
  20. 如申請專利範圍第17項所述之製造基板的方法，其中該導電膜是以濺鍍的方式形成。
TW102130049A 2012-09-21 2013-08-22 具有柱體的半導體封裝基板及其相關方法 TWI549239B (zh)

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