CN103681565A - 具有柱体的半导体封装基板及其相关方法 - Google Patents

具有柱体的半导体封装基板及其相关方法 Download PDF

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CN103681565A
CN103681565A CN201310384435.6A CN201310384435A CN103681565A CN 103681565 A CN103681565 A CN 103681565A CN 201310384435 A CN201310384435 A CN 201310384435A CN 103681565 A CN103681565 A CN 103681565A
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those
circuit pattern
dielectric layer
several
dielectric
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CN103681565B (zh
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陈天赐
陈光雄
王圣民
冯相铭
郭燕桦
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Abstract

一种具有柱体的半导体封装基板及其相关方法。基板包括一第一介电层、一第一电路图案、数个柱体与一第二电路图案。第一介电层具有相对的一第一介电表面与一第二介电表面。第一电路图案埋于第一介电层中，并定义数个弯曲的走线表面。柱体各具有一外表面与一曲基表面，其中外表面用以制造外部的电性连接，曲基表面邻接走线表面中对应的一个。第二电路图案位在第一介电层的第二介电表面上，并电性连接至第一电路图案。

Description

具有柱体的半导体封装基板及其相关方法
技术领域
本实施例是有关于一种具有柱体的半导体封装基板及其相关的方法。
背景技术
一些半导体封装基板包括数个柱体，其用以连接一半导体晶粒的数个焊料凸块至基板。在回焊工艺之后，焊料接点形成在晶粒与柱体之间，使得晶粒黏合至柱体，并稳固之间的电性连接。柱体可以电镀法(electroplating)形成。然而，电渡槽中无法预料且多变的电镀参数常导致过多(over-plating)或过少(under-plating)的电镀，这会造成电镀柱体的顶表面为非共平面。缺乏共平面性会负面地影响封装之后焊料接点的可靠度。是微间距(fine pitch)焊料凸块、晶圆级封装(wafer levelpackaging;WLP)、及大尺寸基板对于这问题特别敏感。缺乏共平面性会引起不均匀(non-uniform)的电流密度分布，其在微尺寸图案上特别严重。此一般不均匀的电流密度分布不只是被一个因素影响，其被各种的电镀参数影响，其中电镀参数由电镀槽设计、化学添加物、电流密度的大小、使用的电流种类、阴极与阳极之间的距离、扰动方式、化学维持性、预清理溶液、图案的结构、配置与体积、高的长宽比(aspect ratio)、等所构成。跨过整个基板的高度误差很难控制在5μm之内，特别是当需要添加平整剂(leveling agent)、浸润剂(wetting agent)、或光泽剂(brightener)至电镀槽时。
发明内容
本实施例其中之一是以关于一基板。基板包括一第一介电层，其具有相对的一第一介电表面与一第二介电表面。基板更包括一第一电路图案埋于第一介电层中。第一电路图案包括数个走线，其定义从第一介电表面露出的数个走线表面。走线表面包括数个曲部分，其凹低于第一介电表面。基板更包括数个柱体。柱体各具有一曲基表面邻接走线表面的曲部分中对应的一个，藉此定义一曲界面于各个柱体与走线表面的曲部分中对应的一个之间。
本实施例其中的另一是以关于一基板。基板包括一第一介电层，其具有相对的一第一介电表面与一第二介电表面。基板更包括一第一电路图案埋于第一介电层中。第一电路图案包括数个走线，其定义从第一介电表面露出的数个走线表面。走线表面定义从第一介电表面向外延伸的数个凹部分。基板更包括数个柱体。柱体各具有一凸基表面邻接走线表面的凹部分中对应的一个，藉此定义一凹形/凸形的界面在各个柱体与走线表面中对应的一个之间。
本实施例其中的再另一是以关于制造一基板的一方法。方法包括形成一图案化层于一载体上，图案化层定义数个开口。方法更包括形成数个柱体的第一柱部分在图案化层中的开口中。方法更包括形成一导电膜覆盖柱体的第一柱部分与图案化层。方法更包括形成一第一电路图案在图案化层上，第一电路图案定义数个走线表面。方法更包括形成一第一介电层于第一电路图案与图案化层上。方法更包括形成数个第一开口在第一介电层中。方法更包括形成数个导电穿孔在第一介电层中，与一第二电路图案在第一介电层上，导电穿孔位在第一介电层中的第一开口中，第一电路图案经由导电穿孔电性连接至第二电路图案。方法更包括形成一第二介电层覆盖第二电路图案的数个部分，并定义数个第二开口，第二电路图案包括被第二介电层中的第二开口所露出的数个接触垫。方法更包括移除载体。方法更包括移除图案化层。方法更包括移除导电膜未被第一柱部分覆盖的数个部分，其中导电膜剩余的部分形成柱体的数个第二柱部分。
为了对本发明的上述及其他方面有更佳的了解，下文特举较佳实施例，并配合附图，作详细说明如下：
附图说明
图1为根据本实施例其中之一的半导体封装的剖面图；
图2为根据本实施例其中的另一的半导体封装的剖面图；
图3A至图3N绘示一实施例中图1显示的基板的制造方法；以及
图4A至图4L绘示一实施例中图2显示的基板的制造方法。
符号说明：
100、200～半导体封装
102、202～基板
104、204～晶粒
106～封装体
108、208、308、408～第一介电层
110、210、310、410～第一电路图案
112、212～柱体
114、214、314、414～第二电路图案
116、216、316、416～第二介电层
118、218、318、418～导电穿孔
120、220～第一介电表面
122、222、322、422～第二介电表面
124、224、324、424～走线
126、226～走线表面
128、228～基表面
130、132、138、230、232、330、332、430、432、1016、1018、2016、2018～开口
134、234、334、434～第一柱部分
136、236～第二柱部分
140～电性接触
142～导电凸块
144～底胶层
146、246～外表面
148、248～侧壁
250～侧表面
252～顶端
1002、2002～载体
1004～下表面
1006上表面
1008、1010、2008、2010～导电层
1012、1014、2012、2014～图案化层
1020、1022、2020、2022～基表面
1024、1026、1034、1038、1040、1048、1050、2024、2026、2034、2038、2040、2048、2050～导电膜
1028、1030、2028、2030～薄膜
1032、1036、2032、2036～介电层
1042、1046、2042、2046～开口
1044、2044～图案化导电膜
2052、2054～侧壁
H1、H2～高度
W1、W3～第一最大宽度
W2、W4～第二最大宽度
具体实施方式
请参照图1，其绘示根据本实施例其中之一的一半导体封装100的剖面图。半导体封装100包括一基板102、一晶粒104与一封装体106。
基板102包括一第一介电层108、一第一电路图案110、数个柱体112、一第二电路图案114、与一第二介电层116。第一电路图案110经由数个导电穿孔118电性连接至第二电路图案114。虽然基板102绘示出只包括两层电路图案，在其他实施例中，基板102可包括任何层数的电路图案，例如三层或更多层。
第一介电层108具有一第一介电表面120与一第二介电表面122。第一介电表面120是相对于第二介电表面122。举例来说，第一介电层108可由用以提高硬度的纤维强化树脂材料及/或预浸体(prepreg)，或任何其他的材料所制得。举例来说，纤维可为玻璃、或芳纶(aramid)、或任何其他的材料。可以纤维强化以用于压合介电材料中的树脂材料的例子包括ABF膜(Ajinomoto build-up film)、双顺丁烯二酸酰亚胺－三氮杂苯(bismaleimide triazine;BT)、预浸体、聚酰亚胺(polyimide;PI)、液晶聚合物(liquid crystal polymer;LCP)、环氧化合物(epoxy)、及其他树脂材料。
第一电路图案110埋在第一介电层108中。请参照图1的放大插图，第一电路图案110包括数个走线124。走线124埋在第一介电层108中，除了数个弯曲的走线表面126从第一介电表面120露出。走线表面126凹低于第一介电表面120。
柱体112各具有一外表面146与一曲基表面128，其中外表面146用作外部的电性连接件(例如连接至一半导体芯片中的其他电性连接件)，曲基表面128接触走线表面126中对应的一个，走线表面126也是曲表面。换言之，柱体112与走线124之间具有一曲界面，其具有凸形的柱体基表面128与凹形的走线表面126。
各个柱体112更包括一第一柱部分134与一第二柱部分136。第一柱部分134具有一第一最大宽度W1。第二柱部分136具有一第二最大宽度W2。第二最大宽度W2可大于第一最大宽度W1。因此，曲基表面128的边缘是位在第一柱部分134横向的外侧。
由于柱体112的外表面146为自实质上平坦的硬质载体上的一导电膜的相同表面形成，因此柱体112的外表面146具有高的共平面度，以下将进一步详述。当基板102经由柱体112电性连接至晶粒104时，高的共平面度会增进半导体封装100的可靠度。一些实施例中，柱体112的外表面146的共平面度为±3μm。换言之，柱体112的高度H1离预期且期望尺寸的偏差值是在3μm的范围之内，其中高度H1是定义为柱体112的外表面146与第一介电层108的第一介电表面120之间的距离。在这些实施例中，高度H1中最大值与最小值之间的差值为6μm或更小。换言之，高度H1之间的差异(variation)为6μm或更小。或者，高度H1中最大值与最小值之间的差值可小于预期且期望尺寸的10%。柱体112的材料可为铜或其他任意的材料。
第二电路图案114配置在第一介电层108的第二介电表面122上。第二介电层116部分地覆盖第二电路图案114。第二介电层116定义出数个开口130，其露出第二电路图案114的数个部分以形成数个接触垫132。第二介电层116可例如为绿漆，或任何其他的材料。接触垫132可用作半导体封装100连接外部的电性连接件，例如连接至另一半导体封装，或连接至电路板上其他构件的电性连接件。举例来说，一电性接触140，例如焊料球，可电性连接至并配置邻近于接触垫132中对应的一个。导电穿孔118各从第一电路图案110穿过第一介电层108中开口138对应的一个而延伸至第二电路图案114。导电穿孔118各电性连接第一电路图案110至第二电路图案114。第一电路图案110的走线124电性连接各个柱体112至导电穿孔118中对应的一个，并至接触垫132中对应的一个。
晶粒104可经由数个熔融的导电凸块142，或经由任何其他的技术，电性连接至柱体112。熔融的导电凸块142可由导电材料，例如焊料或其他任何的材料制得。底胶层144可形成在晶粒104与基板102之间。
封装体106实质上覆盖或包覆晶粒104、第一电路图案110、柱体112与熔融的导电凸块142，以提供机械稳定性，与防止氧化、湿气、及其他环境条件的保护作用。封装体106可由封装材料制得，其可包括例如酚醛基树脂(Novolac-basedresin)、环氧基树脂(epoxy-based resin)、硅基树脂(silicone-based resin)或其他适当的包覆剂。封装体106也可包括适当的填充剂(filler)，例如是粉状的二氧化硅(SiO2)，或任何其他的填充剂。
图2绘示根据本实施例其中的另一的一半导体封装200的剖面图。半导体封装200相似于参照图1说明的半导体封装100。因此，在此仅讨论半导体封装200不同于半导体封装100的部分。请参照图2的放大插图，柱体212各具有一外表面246与一曲基表面228，其中外表面246用作外部的电性连接(例如连接至一半导体芯片中的其他电性连接件)，曲基表面228接触走线224的走线表面226中对应的一个。换言之，柱体212与走线224之间具有一曲界面，其具有凸形的柱体基表面228与凹形的走线表面226。相较于图1的半导体封装100，走线表面226提升高过第一介电表面220。由各个柱体基表面228/走线表面226定义出的曲面其顶端252实质上位于第一介电层208定义的平面中。
柱体212更包括一第一柱部分234与一第二柱部分236。第二柱部分236各具有一凸出部分248，其从曲基表面228的外边缘凸出并围绕走线224的凹部分。凸出部分248具有一侧表面250邻近第二柱部分236的曲基表面228。侧表面250与曲基表面228之间夹有一锐角。第一柱部分234具有一第一最大宽度W3。第二柱部分236具有一第二最大宽度W4。第一最大宽度W3与第二最大宽度W4实质上相等。曲基表面228的剖面宽度小于第一柱部分234的剖面宽度，使得曲基表面228的边缘是放射状地坐落在第一柱部分234的内部。
请参照图2，由于柱体212为自实质上平坦的硬质载体上的一导电膜的相同表面形成，因此柱体212具有高的共平面度，以下将进一步详述。当基板202经由柱体212电性连接至晶粒204时，高的共平面度会增进半导体封装200的可靠度。一些实施例中，柱体112的高度容许公差如同参照图1的半导体封装100所述。柱体212的材料可为铜或任何其他的材料。
基板102与基板202并不限于如图1与图2所示的覆晶接合。其他实施例中，基板102与基板202可用于其他应用，例如打线接合应用或任何其他的应用。
图3A至图3N绘示根据本实施例其中之一的制造基板的方法。为了方便表示，以下步骤是参照图1的半导体封装100的基板102做说明。
图3A绘示实质上平坦的硬质载体1002。一些实施例中，载体1002可包括一核心层(未显示)介于两个载体导电层(未显示)之间，载体导电层贴附至核心层。各个载体导电层可由金属、金属合金、具有金属或金属合金散布其中的基质、或其他合适的电导性材料形成。举例来说，各个载体导电层可包括由铜或铜合金形成的金属箔。金属箔的厚度可介于约10μm至约30μm的范围，例如介于约15μm至约25μm的范围。
载体1002具有一下表面1004与一上表面1006。一导电层1008配置邻近于下表面1004，且一导电层1010配置邻近于上表面1006。导电层1008、1010各可由金属、金属合金、具有金属或金属合金散布其中的基质、或任何其他合适的电导性材料形成。举例来说，导电层1008、1010可包括形成自铜或铜合金的可离型式(releasable)金属箔。导电膜1008、1010可经由一离型层(未显示)贴附至载体1002。一些实施例中，离型层为一黏着层，其可为有机或无机的，例如胶带。胶带可使用单面或双面胶带。胶带将构件稳固在彼此间恰当的间隔，并使得之后进行的步骤能对配置邻近载体1002的构件实行。各个导电层1008、1010的厚度可介于约2μm至约20μm的范围，例如约3μm至约5μm的范围，约3μm至约10μm的范围，约10μm至约20μm的范围，与约15μm至约20μm的范围。
请参照图3B，形成图案化层1012、1014分别邻近于导电膜1008、1010。图案化层1012、1014定义出数个开口1016、1018，其露出导电膜1008、1010。图案化层1012、1014可以光阻层形成，光阻层可为干膜光阻、或其他类型的可图案化层或介电层。光阻层中被选择的部分可被光影像化(photoimaged)并显影(developed)，藉此形成开口1016、1018。光阻层可利用光罩(未显示)光化学性地(photochemically)被定义出。相较于用以形成开口1016、1018于图案化层1012、1014中的其他方法，光影像化及显影可具有成本较低、工艺时间缩减的优势，然可使用任何的技术。产生的开口1016、1018可具有任何的形状，包括柱形(cylindrical)，例如圆柱形(circular cylindrical)、椭圆柱形(elliptical cylindrical)、方柱形(square cylindrical)、或矩柱形(rectangular cylindrical)，或非柱形(non-cylindricalshape)，例如锥形(cone)、漏斗形(funnel)，或任何一头逐渐变细的(tapered)形状。
请参照图3C，填充一导电材料至图案化层1012、1014的开口1016、1018中，以形成第一柱部分134、334。于此实施例中，是经由电镀法将导电材料过度填充开口1016、1018，使得形成的第一柱部分134、334突出自图案化层1012、1014，并形成曲基表面1020、1022(例如以上所述的凸形的表面)。第一柱部分134、334可以金属、金属合金、具有金属或金属合金散布于其中的基质，或任何其他合适的电导性材料。举例来说，第一柱部分134、334可包括一个或更多个铜或铜合金层。
请参照图3D，分别形成两个导电膜1024、1026在第一柱部分134、334与图案化层1012、1014上。一些实施例中，导电膜1024、1026可以溅镀的方式形成。经由过度填充开口1016、1018，可减少开口1016、1018中空隙(voids)或死角(deadspaces)发生的机会，而藉此避免断路(open circuit)问题。导电膜1024、1026可由金属、金属合金、具有金属或金属合金散布其中的基质、或任何其他合适的导电性材料形成。举例而言，导电膜1024、1026可包括一个或更多个铜或铜合金层。在进一步的示例中，导电膜1024、1026可为一溅镀铜膜。
请参照图3E，形成第一电路图案110、310于导电膜1024、1026上。第一电路图案110、310包括走线124，324，其接触导电膜1024、1026并共形于导电膜1024、1026，以形成曲界面。一些实施例中，第一电路图案110、310的形成方法包括形成数个图案化的光阻层，其定义露出导电膜1024、1026数个部分的数个开口，然后以导电性材料填充图案化的光阻层中的开口(例如使用导电膜1024、1026作为阴极的电镀方法)，并然后移除图案化的光阻层。或者，第一电路图案110、310的形成方法可包括形成数个导电材料层(未显示)覆盖导电膜1024、1026，然后形成数个光阻图案(未显示)其定义露出导电材料层的数个部分的数个开口，然后利用蚀刻方法移除导电材料层被光阻图案的开口露出的数个部分，其中导电材料层留下的数个部分形成第一电路图案110、310，且然后移除光阻层。第一电路图案110、310可由金属、金属合金、具有金属或金属合金散布其中的基质、或任何其他合适的导电性材料形成，且可为溅镀或电镀法形成，并可为图案化的。一些实施例中，第一电路图案110、310是由铜形成。
请参照图3F，压合一薄膜1028在第一电路图案110与导电膜1024上，并压合一薄膜1030在第一电路图案310与导电膜1026上。薄膜1028可包括一介电层1032压合在第一电路图案110与导电膜1024上，与一导电膜1034覆盖介电层1032。薄膜1030可包括一介电层1036压合在第一电路图案310与导电膜1026上，与一导电膜1038覆盖介电层1036。导电膜1034、1038可以类似导电膜1008、1010的材料形成。
介电层1032、1036可由用以提高硬度的纤维强化树脂材料及/或预浸体(prepreg)制得。纤维可为玻璃、或芳纶(aramid)、或任何其他的材料。介电层1032、1036可由利用纤维强化的一薄膜形成，以增强介电材料。可利用纤维强化以用于压合介电材料中的树脂材料的例子包括ABF膜(Ajinomoto build-up film)、双顺丁烯二酸酰亚胺－三氮杂苯(bismaleimide triazine;BT)、预浸体、聚酰亚胺(polyimide;PI)、液晶聚合物(liquid crystal polymer;LCP)、环氧化合物(epoxy)、及其他树脂材料。一些实施例中，介电层1032、1036是预先形成(preformed)，以在对应第一电路图案110、310的位置定义出数个开口。
或者，介电层1032、1036可以未强化、低硬度材料形成，例如绿漆(solder mask;solder resist)，树脂材料包括但不限于ABF膜、BT、预浸体、PI、LCP、及环氧化合物、或任何其他种类的可图案化层或介电层。此材料可利用任何涂布技术提供，例如印刷、旋涂(spinning)、或喷涂(spraying)。
请参照图3G，接着，移除图3F中所示的介电层1032与薄膜1028的导电膜1034的数个部分，以形成第一介电层108与一图案化导电膜1040，其定义出露出第一电路图案110数个部分的数个开口1042。此外，移除图3F所示的介电层1036与薄膜1030的导电膜1038的数个部分，以形成第一介电层308与一图案化导电膜1044，其定义出露出第一电路图案310数个部分的数个开口1046。一些实施例中，开口1046可在导电膜1040、1044中激光钻出孔洞，并对激光钻出的孔洞所露出的介电层1032、1036(图3F)进行等离子体蚀刻而形成。或者，开口1046可以化学蚀刻、或机械钻孔的方式形成。产生的开口1042、1046可具有任何的形状，包括柱形，例如圆柱形、椭圆柱形、方柱形、或矩柱形，或非柱形，例如锥形、漏斗形，或任何一头逐渐变细的形状。产生的开口的侧边界(lateral boundaries)可为弯曲或结构粗操的(roughly textured)。
请参照图3H，形成一导电材料在第一介电层108、308中的开口1042、1046与图案化导电膜1040、1044(图3G)中，以形成数个导电穿孔118、318与数个导电膜1048、1050，导电膜1048、1050从第一介电层108、308的第二介电表面122、322上的导电穿孔118、318延伸。导电膜1048、1050可包括图3G中所示的图案化导电膜1040、1044，或更包括形成在图3G中所示的图案化导电膜1040、1044上的额外的导电材料。一些实施例中，导电穿孔118、318与导电膜1048、1050的形成方式为，利用无电镀法形成数个导电材料(未显示)在图3G所示的被开口1042、1046露出的第一介电层108、308其侧壁上，与图案化导电膜1040、1044上，并然后填充另外数个导电材料在开口1042、1046中。一些实施例中，导电穿孔118、318与导电膜1048、1050可由金属、金属合金、具有金属或金属合金散布其中的基质、或任何其他合适的导电性材料形成。举例来说，导电穿孔118、318与导电膜1048、1050可由铜形成。
然后，图案化导电膜1048以形成一第二电路图案114，其电性连接至导电穿孔118，如图3I所示。此外，图案化图3H所示的导电膜1050，以形成一第二电路图案314，其电性连接至导电穿孔318。第二电路图案114、314的形成方式可为，形成数个光阻层(未显示)，其定义出露出图3H所示的导电膜1048、1050数个部分的数个开口，然后利用蚀刻方式移除导电膜1048、1050被光阻层中的开口露出的部分，其中导电膜1048、1050留下的部分形成图3I所示的第二电路图案114、314，并然后移除光阻层。虽然以上所述的第二电路图案114、314是以减成法(subtractivemethod)形成，然其亦可以半加成法(semi-additive process)形成。
请参照图3J，形成一第二介电层116于第一介电层108的第二介电表面122上与第二电路图案114上。第二介电层116包括数个开口130露出第二电路图案114的数个部分以形成数个接触垫132。形成一第二介电层316在第一介电层308的第二介电表面322上，与第二电路图案314上。第二介电层316定义出数个开口330露出第二电路图案314的数个部分以形成数个接触垫332。第二介电层116、316可以绿漆或任何其他种类的介电材料形成。
请参照图3K，移除载体1002以露出导电膜1008、1010。然后，移除导电层1008以露出第一柱部分134的外表面146与图案化层1012，如图3L所示。移除工艺可包括例如蚀刻，或任何其他技术。接着，移除图案化层1012以露出第一柱部分134的数个侧壁148，及导电膜1024位在第一柱部分134的侧壁148外侧的数个部分，如图3M所示。移除工艺可包括例如剥除(stripping)，或任何其他的技术。接着，移除如图3M所示的导电膜1024位在第一柱部分134的侧壁148外侧的部分，以形成基板102的数个第二柱部分136，如图3N所示。移除工艺可包括例如蚀刻，或任何其他的技术。
图4A至图4L绘示根据本实施例其中另一个的制造基板的方法。为了方便表示，以下步骤是参照图2的半导体封装200的基板202做说明。一些实施例中，图4A所示的阶段之前的步骤相似于图3A及图3B。
请参照图4A，于此实施例中，一导电材料形成在图案化层2012、2014中的各个开口2016、2018中，以形成第一柱部分234、434。图案化层2012、2014各个侧壁2052、2054的数个部分并未被导电材料覆盖。第一柱部分234、434可以电镀或任何其他工艺形成。第一柱部分234、434可以类似于第一柱部分134、334(图3C)的材料形成。
请参照图4B，分别形成两个导电膜2024、2026在图案化层2012、2014与第一柱部分234、434的曲基表面2020、2022上。一些实施例中，导电膜2024、2026可以无电镀的方式形成，使得导电膜2024能够连续地形成在图案化层2012的侧壁2052与第一柱部分234的曲基表面2020之间的角落空间中，及图案化层2014的侧壁2054与第一柱部分434的曲基表面2022之间的角落空间。在此手法中，可避免死角问题发生。导电膜2024、2026可由金属、金属合金、具有金属或金属合金散布其中的基质、或任何其他合适的导电性材料形成。举例来说，导电膜2024、2026可包括一或更多个铜或铜合金层。
请参照图4C，形成第一电路图案210、410在导电膜2024、2026上。第一电路图案210、410包括数个走线224、424，其接触导电膜2024、2026。第一电路图案210、410的形成方法可类似于参照图3E所述的第一电路图案110、310的形成方法。
请参照图4D，形成薄膜2028、2030。薄膜2028可包括一介电层2032与一导电膜2034。薄膜2030可包括一介电层2036与一导电膜2038。薄膜2028、2030的形成方法可类似参照图3F所述的薄膜1028、1030的形成方法。
接着，移除介电层2032与薄膜2028的导电膜2034(图4D)的数个部分，以形成一第一介电层208与一图案化导电膜2040其定义出露出第一电路图案210数个部分的数个开口2042，如图4E所示。此外，移除介电层2036与薄膜2030的导电膜2038(图4D)的数个部分，以形成一第一介电层408与一图案化导电膜2044其定义出露出第一电路图案410数个部分的数个开口2046。第一介电层208、408与图案化导电膜2040、2044的形成方法可类似于参照图3G所述的第一介电层108、308与图案化导电膜1040、1044的形成方法。
请参照图4F，形成一导电材料于第一介电层208、408与图案化导电膜2040，2044的开口2042、2046(图4E)中，以形成导电穿孔218、418与导电膜2048、2050，其中导电膜2048、2050是从第一介电层208、408的第二介电表面222、422上的导电穿孔218、418延伸。导电穿孔218、418与导电膜2048、2050的形成方法可类似于先前参照图3H所述的导电穿孔118、318与导电膜1048、1050的形成方法。
接着，图案化导电膜2048，以形成一第二电路图案214，其电性连接至导电穿孔218，如图4G所示。再者，图案化导电膜2050(图4F)以形成一第二电路图案414，其电性连接至导电穿孔418。第二电路图案214、414的形成方法可类似于参照图3I所述的第二电路图案114、314的形成方法。
请参照图4H，形成一第二介电层216在第一介电层208的第二介电表面222上，与第二电路图案214上。第二介电层216定义露出第二电路图案214数个部分的数个开口230，以形成数个接触垫232。形成一第二介电层416在第一介电层408的第二介电表面422上，与第二电路图案414上。第二介电层416定义露出第二电路图案414数个部分的数个开口430，以形成数个接触垫432。第二介电层216、416可以绿漆或其他任何种类的介电材料形成。
请参照图4I，移除载体2002以露出导电层2008、2010。接着，移除导电层2008以露出第一柱部分234的外表面246与图案化层2012，如图4J所示。移除工艺可包括例如蚀刻，或任何其他的技术。
接着，移除图案化层2012，以露出第一柱部分234的侧壁248、及导电膜2024位在第一柱部分234外侧的数个部分，如图4K所示。移除工艺可包括例如蚀刻，或任何其他的技术。
接着，移除导电膜2024位在第一柱部分234的侧壁248(图4K)外侧的部分，以形成数个第二柱部分236，如图4L所示。
综上所述，虽然本发明已以较佳实施例揭露如上，然其并非用以限定本发明。本发明所属技术领域中具有通常知识者，在不脱离本发明的精神和范围内，当可作各种的更动与润饰。因此，本发明的保护范围当视权利要求书所界定者为准。

Claims (20)

1.一基板，其特征在于，包括：
一第一介电层，具有相对的一第一介电表面与一第二介电表面；
一第一电路图案，埋在该第一介电层中，该第一电路图案包括数个走线，该些走线定义从该第一介电表面露出的走线表面，该些走线表面包括低于该第一介电表面的曲部分；以及
数个柱体，各具有一曲基表面邻接该些走线表面的该些曲部分中对应的一个，藉此在各该些柱体与该些走线表面的该些曲部分中对应的一个之间定义出一曲界面。
2.如权利要求1所述的基板，其特征在于，更包括一第二电路图案于该第一介电层的该第二介电表面上，并电性连接至该第一电路图案。
3.如权利要求2所述的基板，其特征在于，更包括一第二介电层邻接该第一介电层的该第二介电表面，并覆盖部分的该第二电路图案。
4.如权利要求1所述的基板，其特征在于，该些柱体各个的该曲基表面为凸形的。
5.如权利要求4所述的基板，其特征在于，该些走线表面的该些曲部分各为凹形的。
6.如权利要求1所述的基板，其特征在于，该些柱体各包括互相邻接的两个分部。
7.如权利要求1所述的基板，其特征在于，该些柱体各包括一第一柱部分与一第二柱部分，该第一柱部分与该些走线表面中对应的一个隔开，该第二柱部分配置在该第一柱部分与该些走线表面中对应的该一个。
8.如权利要求7所述的基板，其特征在于，该些第一柱部分各具有一第一宽度，该些第二柱部分各具有一第二宽度，且该第二宽度大于该第一宽度。
9.一种基板，其特征在于，包括：
一第一介电层，具有相对的一第一介电表面与一第二介电表面；
一第一电路图案，埋在该第一介电层中，该第一电路图案包括数个走线，该些走线定义从该第一介电表面露出的走线表面，该些走线表面定义从该第一介电表面延伸出的凹部分；以及
数个柱体，各具有一凸基表面邻接该些走线表面的该些凹部分中对应的一个，藉此在各该些柱体与该些走线表面中对应的一个之间定义出一凹/凸界面。
10.如权利要求9所述的基板，其特征在于，该些凹部分各个的顶端实质上位于该第一介电表面的平面中。
11.如权利要求9所述的基板，其特征在于，更包括一第二电路图案在该第一介电层的该第二介电表面上，并电性连接至该第一电路图案。
12.如权利要求11所述的基板，其特征在于，更包括一第二介电层邻接该第一介电层的该第二介电表面，并覆盖该第二电路图案的数个部分。
13.如权利要求9所述的基板，其特征在于，该些柱体各包括互相邻接的两个分部。
14.如权利要求9所述的基板，其特征在于，该些柱体各包括一第一柱部分与一第二柱部分，该第一柱部分与该些走线表面中对应的一个隔开，该第二柱部分配置在该第一柱部分与该些走线表面中该对应的一个之间。
15.如权利要求14所述的基板，其特征在于，该些第二柱部分各包括一导电膜。
16.如权利要求14所述的基板，其特征在于，该些第二柱部分各包括一侧表面，该侧表面与该曲基表面之间夹有一锐角。
17.一种制造基板的方法，其特征在于，包括：
形成一图案化层于一载体上，该图案化层定义数个开口；
形成数个柱体的数个第一柱部分在该图案化层的该些开口中；
形成一导电膜覆盖该些柱体的该些第一柱部分与该图案化层；
形成一第一电路图案在该图案化层上，该第一电路图案定义数个走线表面；
形成一第一介电层在该第一电路图案与该图案化层上；
形成数个第一开口于该第一介电层中；
形成数个导电穿孔在该第一介电层中，与一第二电路图案在该第一介电层上，该些导电穿孔位在该第一介电层的该些第一开口中，该第一电路图案经由该些导电穿孔电性连接至该第二电路图案；
形成一第二介电层覆盖该第二电路图案的数个部分，且定义数个第二开口，该第二电路图案包括数个接触垫，该些接触垫自该第二介电层中的该些第二开口露出；
移除该载体；
移除该图案化层；以及
移除该导电膜未被该些第一柱部分覆盖的数个部分，其中该导电膜留下的部分形成该些柱体的数个第二柱部分。
18.如权利要求17所述的制造基板的方法，其特征在于，该些柱体各具有一曲基表面，该曲基表面在一曲界面处邻接该些走线表面中对应的一个。
19.如权利要求18所述的制造基板的方法，其特征在于，该些第一柱部分填充超过该图案化层中该些开口中对应的数个，以形成该些曲基表面。
20.如权利要求17所述的制造基板的方法，其特征在于，该导电膜是以溅镀的方式形成。
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