TW201409635A - 用於表面安置模組之擴散阻障 - Google Patents

用於表面安置模組之擴散阻障 Download PDF

Info

Publication number
TW201409635A
TW201409635A TW102125294A TW102125294A TW201409635A TW 201409635 A TW201409635 A TW 201409635A TW 102125294 A TW102125294 A TW 102125294A TW 102125294 A TW102125294 A TW 102125294A TW 201409635 A TW201409635 A TW 201409635A
Authority
TW
Taiwan
Prior art keywords
layer
diffusion barrier
sub
module
level
Prior art date
Application number
TW102125294A
Other languages
English (en)
Other versions
TWI588957B (zh
Inventor
Arun Virupaksha Gowda
Paul Alan Mcconnelee
Ri-An Zhao
Shakti Singh Chauhan
Original Assignee
Gen Electric
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Gen Electric filed Critical Gen Electric
Publication of TW201409635A publication Critical patent/TW201409635A/zh
Application granted granted Critical
Publication of TWI588957B publication Critical patent/TWI588957B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H01L23/49894—Materials of the insulating layers or coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13022—Disposition the bump connector being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199—Material of the matrix
    • H01L2224/2929—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92142—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92144—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/564—Details not otherwise provided for, e.g. protection against moisture
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Materials Engineering (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)
  • Wire Bonding (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

本發明揭示一種用於減少濕氣及氣體進入至其之表面安置封裝結構。該表面安置結構包括一子模組，該子模組具有：一介電層；半導體裝置，其附接至該介電層；一第一級互連結構，其電耦合至該等半導體裝置；及一第二級I/O連接件，其電耦合至該第一級互連且形成在該介電層上，其中該第二級I/O連接件經組態以將該子模組連接至一外部電路。該子模組之半導體裝置附接至一基板結構，其中一介電材料定位在該介電層與該基板結構之間以填充該表面安置結構中之間隙。一擴散阻障層施加在該子模組上、鄰近該第一級I/O連接件及該第二級I/O連接件且向下延伸至該基板結構，以減少濕氣及氣體自一周圍環境進入至該表面安置結構中。

Description

用於表面安置模組之擴散阻障
本發明之實施例大體上係關於用於封裝半導體裝置之結構及方法，且更特定而言，係關於包括一擴散阻障塗層之一表面安置封裝結構。
表面安置技術為用於建構電子裝置之一方法，其中表面安置組件或封裝直接安置至印刷電路板(PCB)或其他類似外部電路之表面上。在業界中，表面安置技術已代替使用引線將組件裝配於電路板中之孔中之介層孔技術建構方法。
一種常見類型之表面安置組件為一電力半導體裝置(其為用作電力電子電路中之一開關或整流器之一半導體裝置)，例如，諸如切換模式電力供應器。大多數電力半導體裝置僅以換向模式使用(即，其等要麼接通要麼關斷)，且因此針對此最佳化。許多電力半導體裝置用於高電壓電力應用中且經設計以運載大量電流且支援一大電壓。在使用中，高電壓電力半導體裝置憑藉一電力覆疊(POL)封裝及互連系統而表面安置至一外部電路，其中POL封裝亦提供一種移除由該裝置產生之熱且保護該裝置免遭外部環境之方式。
一標準POL封裝製程通常以憑藉一黏合劑將一或多個半導體裝置放置至一介電層上而開始。接著，將金屬互連(諸如，銅互連)電鍍至該介電層上以形成與該(該等)電力半導體裝置之一直接金屬連接，以便形成一POL子模組。該等金屬互連可呈一低剖面(諸如，小於200微米厚)、平坦互連結構之形式，該互連結構提供該(該等)半導體裝置往 返於該(該等)半導體裝置之一輸入/輸出(I/O)系統之形成。接著，使用焊接互連將該POL子模組焊接至一陶瓷基板(使用直接接合銅(DBC)之氧化鋁、使用AMB Cu之AlN，等等)以用於電及熱連接性。接著，使用毛細流動(底部填充)、非流動底部填充或注射模製(模製化合物)而使用一介電有機材料填充POL介電層與該陶瓷基板之間之半導體周圍之間隙，以形成該POL封裝。
應認識到，POL封裝易受到濕氣之影響，此係因為環境中之濕氣可被POL封裝中之材料吸收。舉例而言，該模組可吸收在由Kapton黏合劑層及有機材料(即，底部填充、模製化合物，等等)組成之主體內且在由此等材料在該封裝內產生之界面處的濕氣。當將具有吸收濕氣之POL模組焊接至一電路板時，達到在攝氏210度至260度之範圍內之溫度，且在此等溫度下，POL封裝中之濕氣之蒸氣壓迅速升高。此蒸氣壓升高在濕氣過量之情況下可引起剝離、「爆裂」及故障。此外，在曝露於濕氣時之長期儲存及使用中，由POL封裝進行之過量濕氣吸收及該封裝內之不同材料界面處之腐蝕可引起歸因於增加之洩漏電流之電故障及機械故障且亦可引起歸因於POL模組在板組裝操作期間之迴焊之後之回脹之對互連之損害。
在空氣(或富氧環境)中之升高溫度下之長期操作/儲存或在曝露於有毒/腐蝕性氣體之情況下之長期操作/儲存亦可影響POL模組之長期壽命及功能性。在升高溫度下之氧氣進入之情況下，各種界面可降級且該模組之機械/電/熱效能可受到嚴重影響。舉例而言，POL金屬(Cu)與Kapton(聚醯亞胺薄膜)之間之黏合受到升高溫度下之對氧氣之曝露之強烈影響，其中於200C至250C之間之溫度下1000小時之儲存中發現黏合強度之降級。包括一強健之擴散阻障可減緩氧氣(或其他降級氣體)之進入且增加該等模組之長期壽命。
因此，需要提供一種表面安置封裝，其具有減少濕氣及氣體進 入至該封裝中之擴散阻障，以便提供濕氣相關及氣體相關故障機構之增強可靠性。進一步需要在該表面安置封裝之各種製造階段期間引入此一擴散阻障。
本發明之實施例藉由提供包括一擴散阻障塗層之一表面安置封裝結構來克服上文提及之缺陷，該擴散阻障塗層經組態以減少濕氣及氣體自一周圍環境進入至表面安置結構中。
根據本發明之一態樣，一表面安置結構包括一子模組，該子模組具有：一介電層；至少一個半導體裝置，其附接至該介電層，該至少一個半導體裝置包括由一半導體材料組成之一基板；一第一級金屬互連結構，其電耦合至該至少一個半導體裝置，該第一級金屬互連延伸通過經形成穿過該介電層之介層孔以連接至該至少一個半導體裝置；及一第二級輸入/輸出(I/O)連接件，其電耦合至該第一級金屬互連結構且在與該至少一個半導體裝置相對之一側上形成在該介電層上，其中該第二級I/O連接件經組態以將該子模組連接至一外部電路。該表面安置結構亦包括一多層基板結構，該多層基板結構具有一第一表面及一第二表面，其中該子模組之至少一個半導體裝置附接至該多層基板之第一表面。該表面安置結構進一步包括：一介電材料，該介電材料定位在該介電層與該多層基板結構之該第一表面之間且至少部分地圍繞該子模組之該至少一個半導體裝置而定位；及一擴散阻障層，其其施加在該子模組上、鄰近該第一級I/O連接件及該第二級I/O連接件且向下延伸至該多層基板結構，其中該擴散基板層經組態以減少濕氣及氣體自一周圍環境進入至該表面安置結構中。
根據本發明之另一態樣，一種製造一表面安置封裝及互連結構之方法包括以下步驟：建構一子模組，該子模組包括至少一個半導體裝置及圍繞該至少一個半導體裝置形成之一封裝結構，其中建構該子 模組之步驟進一步包括以下步驟：將該至少一個半導體裝置附接至一介電層；在該介電層上形成一第一級金屬互連結構，該第一級金屬互連結構延伸通過該介電層中之介層孔以電連接至該至少一個半導體裝置；及在與該至少一個半導體裝置相對之一側上在該介電層上形成一第二級輸入/輸出(I/O)連接件，其中該第二級I/O連接件經組態以將該子模組連接至一外部電路。該方法亦包括以下步驟：形成一基板結構，該基板結構包括一中心基板層及位於該中心基板層之相對側上之第一金屬層及第二金屬層，使得該第一金屬層及該第二金屬層分別形成該基板結構之一第一表面及一第二表面；將該子模組附接至該基板結構之第一表面；及在該介電層與該基板結構之第一表面之間提供一介電材料，其中該介電材料至少部分地囊封該子模組之該至少一個半導體裝置。該方法進一步包括以下步驟：施加一擴散阻障層，該擴散阻障層施加在該子模組上、鄰近該第二級I/O連接件且向下延伸至該多層基板結構，其中該擴散阻障層經組態以減少濕氣及氣體自一周圍環境進入至該表面安置封裝及互連結構中。
根據本發明之又另一態樣，一種電力覆疊(POL)封裝結構包括一POL子模組，該POL子模組具有：一介電層；複數個半導體裝置，其附接至該介電層；一第一級互連結構，其電耦合至該複數個半導體裝置，該第一級互連結構延伸通過經形成穿過該介電層之介層孔以連接至該複數個半導體裝置；及一第二級互連結構，其將該POL子模組電耦合至一外部電路結構，其中該第二級互連結構包含複數個焊料凸塊，該複數個焊料凸塊形成在該介電層及第一級互連結構上且經組態以製造與該外部電路結構之一互連。該POL封裝結構亦包括一多層基板結構，該多層基板結構具有一第一表面及一第二表面，其中該POL子模組之該複數個半導體裝置附接至該多層基板結構之該第一表面。該多層基板結構進一步包括：一第一直接接合銅(DBC)層，其形成該 多層基板結構之該第一表面；一第二DBC層，其形成該多層基板結構之該第二表面；及一陶瓷層，其夾在該第一DBC層與該第二DBC層之間。該POL封裝結構進一步包括：一囊封材料，其定位在該介電層與該多層基板結構之該第一表面之間且至少部分地圍繞該子模組之該複數個半導體裝置而定位；及一擴散阻障層，其施加在該POL子模組上、鄰近該第二級互連結構且向下延伸至該多層基板結構，其中該擴散阻障層經組態以減少濕氣及氣體自一周圍環境進入至POL封裝結構中。
將根據結合附圖提供之對本發明之較佳實施例之以下詳細描述而更容易地理解此等及其他優點及特徵。
10‧‧‧POL結構
12‧‧‧半導體裝置
14‧‧‧POL子模組14
16‧‧‧第二級I/O連接件/第二級I/O互連
17‧‧‧焊料凸塊
18‧‧‧基板結構
20‧‧‧陶瓷磚/陶瓷層
22‧‧‧直接接合銅(DBC)層/頂DBC層/晶粒側DBC層/金屬材料片
24‧‧‧直接接合銅(DBC)層/底DBC層24/非晶粒側DBC層/背側DBC層/金屬材料片
26‧‧‧介電材料/聚合物底部填充材料/囊封材料/模製化合物
28‧‧‧擴散阻障層
28A‧‧‧第一擴散阻障層
28B‧‧‧第二擴散阻障層
30‧‧‧介電層
32‧‧‧框架結構
34‧‧‧黏合劑層/黏合劑
36‧‧‧介層孔/開口
37‧‧‧銅填隙片
38‧‧‧第一級互連/金屬互連/第一級金屬互連
39‧‧‧頂面
40‧‧‧焊料材料/焊料遮罩
42‧‧‧焊料遮罩/焊料遮罩層
50‧‧‧單一層
52‧‧‧第一層
54‧‧‧第二層
56‧‧‧具有一分級組成物之一層
58‧‧‧區域
60‧‧‧區域
62‧‧‧區域
圖式繪示當前針對實施本發明而預期之實施例。
在該等圖式中：圖1為根據本發明之一實施例之一電力覆疊(POL)結構之一示意性橫截面側視圖。
圖2至圖9為在根據本發明之一實施例之一製造/堆積程序之各種階段期間之一POL結構之示意性橫截面側視圖。
圖10A至圖10D為根據本發明之實施例之具有施加至其之一擴散阻障層之一POL結構之示意性橫截面側視圖。
圖11A至圖11C為根據本發明之實施例之一擴散阻障層之示意性橫截面側視圖。
本發明之實施例提供一種具有包括在其上之一擴散阻障層之一表面安置封裝以及一種形成此一表面安置封裝之方法。該表面安置封裝經製造使得該擴散阻障層減少濕氣及氣體進入至該封裝中，同時仍然提供該表面安置封裝與一外部電路之附接。
參考圖1，展示根據本發明之一實施例之一表面安置封裝及互連結構10。在圖1中展示之實施例中，表面安置封裝結構10呈一電力覆疊(POL)結構之形式，但是應認識到，其他表面安置封裝結構被認為係在本發明之範圍內。該POL結構10在其中包括一或多個半導體裝置12，根據各種實施例，該一或多個半導體裝置12可呈晶粒、二極體或其他電力電子裝置之形式。如圖1中所展示，在POL結構10中提供三個半導體裝置12，然而，應認識到，在POL結構10中可包括更多或更少數目之半導體裝置12。半導體裝置12封裝在一POL子模組14內，該POL子模組14形成與電力半導體裝置12之一直接金屬連接，其中，舉例而言，該連接呈一低剖面、平坦第一級互連結構之形式。
一第二級輸入/輸出(I/O)連接件16提供在POL子模組14上以實現POL結構10至一外部電路(諸如一印刷電路板(PCB)(未展示))之表面安置。根據一例示性實施例，第二級I/O連接件16以平台格柵陣列(LGA)焊料凸塊17形成，該等平台格柵陣列(LGA)焊料凸塊17經組態以附接/固定至PCB以將POL結構10電耦合至PCB，然而亦可使用其他合適第二級焊料互連，諸如球格柵陣列(BGA)焊料凸塊。LGA焊料凸塊17提供在高應力條件下對故障具有抵抗性之一高可靠性互連結構。
如圖1中所展示，POL結構10亦包括一基板結構18，POL子模組14附接至該基板結構18。根據一示例性實施例，該基板結構18由一陶瓷磚(諸如，氧化鋁)20組成，其中一直接接合銅(DBC)層22、24藉由一高溫接合程序接合至該陶瓷磚20之兩側。對於該接合程序，基於(舉例而言)磚20是否以氧化鋁或氮化鋁及氮化矽等等組成，可使用不同銅焊及直接接合技術。接著，在燒製之後蝕刻基板結構18之頂DBC層22或「晶粒側DBC層」，以基於半導體裝置12之數目/配置根據需要對該層進行圖案化。基板結構18之背側上之底DBC層24或「非晶粒側DBC層」保持完全或部分曝露，以提供自POL結構10之有效熱傳遞。 雖然在上文及下文中稱為「DBC層」，但應認識到，可替代銅而將鋁用作金屬層，且因此此一實施例被認為在本發明之範圍內。因此，在下文中使用術語「DBC層」意欲涵蓋包括接合至一陶瓷磚(諸如，氧化鋁)20之兩側之任意合適金屬材料片22、24(諸如銅或鋁)之一基板結構18。如圖1中所展示，一介電材料26亦提供在POL結構10上以填充POL結構10中之間隙，以便向POL結構10提供額外結構完整性。介電材料26在下文中一般稱為一「底部填充材料」，且在一較佳實施例中為一有機介電材料，該有機介電材料對濕氣敏感且在固化之前如液體般流動。然而，應認識到，介電材料26可由許多合適材料中之任一者形成，包括底部填充材料、矽氧烷、模製化合物、囊封材料或其他合適有機材料。
如圖1中所展示，POL結構10亦包括一擴散阻障層28，圍繞POL結構10之POL子模組14而施加該擴散阻障層28。根據本發明之實施例，擴散阻障層28經組態以具有一低濕氣及氣體(諸如，氧氣)滲透性，以便顯著減少由POL子模組14中之材料、底部填充材料26吸收及在該子模組中之材料之間之界面處吸收之濕氣及氣體之數量，並且防止其他污染物與POL子模組14接觸。此外，阻障層28使得POL結構10對於焊接操作(諸如，將第二級I/O連接件16焊接至一PCB)更可靠。擴散阻障層28鄰近第二級I/O連接件16而施加且以不阻礙將第二級I/O連接件16焊接至一PCB之一厚度而施加。下文根據本發明之各種實施例更詳細地論述將擴散阻障層28施加至POL結構10。
現在參考圖2至圖12，根據本發明之一實施例，提供用於製造圖1之POL結構10之一技術之程序步驟之詳細視圖。如圖2至圖9中所展示，提供用於堆積POL子模組14之程序步驟。參考圖2，POL子模組14之堆積程序以將一介電層30或「撓曲層」放置及附接至一框架結構32上而開始。介電層30呈層壓材料或膜之形式且放置在框架結構32上 以在POL子模組14之堆積程序期間提供穩定性。根據本發明之實施例，介電層30可以一複數種介電材料形成，諸如Kapton®、Ultem®、聚四氟乙烯(PTFE)、Upilex®、聚碸材料(諸如，Udel®、Radel®)、或另一聚合物薄膜(諸如一液晶聚合物(LCP)或一聚醯亞胺材料)。
如圖3中所展示，在將介電層30緊固至框架結構32之後，將一黏合劑層34沈積至介電層30上。接著，形成穿過黏合劑層34及介電層30之複數個介層孔36，如圖4中繪示。根據本發明之實施例，可憑藉一雷射燒蝕或雷射鑽孔程序、電漿蝕刻、光定義或機械鑽孔程序形成介層孔36。在下一技術步驟中，憑藉黏合劑層34將一或多個半導體裝置12(諸如，三個半導體裝置)緊固至介電層30，如圖5中繪示。為將半導體裝置12緊固至介電層30，將半導體裝置12放置至黏合劑層34上且接著固化黏合劑34以將半導體裝置12緊固在介電層30上。根據本發明之一實施例，且如圖5中繪示，半導體裝置12可具有變化之厚度/高度。為增加一半導體裝置12之一厚度/高度，可將一銅填隙片37焊接至半導體裝置12之一或多者以增加其厚度/高度，使得所有半導體裝置12之厚度/高度係相等的且半導體裝置12之一背面被「平坦化」。
雖然在圖4中展示在將半導體裝置12放置至黏合劑層34上之前執行形成穿過黏合劑層34及介電層壓結構30之介層孔36，但應認識到，半導體裝置12之放置可發生在介層孔形成之前。即，取決於受制於介層孔大小之約束，可首先將半導體裝置12放置在黏合劑層34及介電層30上，而介層孔36隨後形成在對應於形成在半導體裝置12上之複數個金屬化電路及/或連接墊(未展示)之位置處。此外，可根據需要使用預鑽孔介層孔及後鑽孔介層孔之一組合。
如圖6及圖7中所展示，在將半導體裝置12緊固在介電層30上且形成介層孔36之後，清除介層孔36(諸如，通過一反應性離子蝕刻(RIE)去污(desoot)程序)且隨後使介層孔36金屬化以形成第一級互連 38。第一級金屬互連38通常通過濺鍍及電鍍應用之一組合而形成，但應認識到，亦可使用其他金屬沈積之無電鍍方法。舉例而言，可首先經由一濺鍍程序施加一鈦黏附層及銅晶種層，接著進行將該銅之一厚度增加至一所要位階之一電鍍程序。接著，隨後將所施加之金屬材料圖案化成具有所要形狀且用作經形成穿過介電層30及黏合劑層34形成之垂直饋通件之金屬互連38(即，第一級互連)。金屬互連38自半導體裝置12之電路及/或連接墊(未展示)延伸出，通過介層孔/開口36且穿過介電層30之一頂面39。
現在參考圖8，製造POL結構10之技術以將POL子模組14附接至基板結構18繼續。根據本發明之一實施例，憑藉一焊料材料40將POL子模組附接至基板結構18，以便將POL子模組14及基板結構18緊固在一起。即，將半導體裝置12之各者焊接至晶粒側DBC層22。接著，如圖9中所展示，在POL結構10上提供填充POL結構10中之間隙之一聚合物底部填充材料、囊封材料或模製化合物26(諸如，環氧樹脂或其他有機填充物材料)，以約束介電層30且向POL結構10提供額外電絕緣及結構完整性。
現在參考圖10A至圖10D，繪示POL結構10之製造中之下一個步驟之各種實施例，其中將一或多個擴散阻障層28施加至POL結構10。在圖10A至圖10D中展示之各種替代步驟之各者中，將擴散阻障層28施加至POL結構10以顯著減少由POL結構10中之材料吸收及在該結構中之材料之間之界面處吸收之濕氣及氣體之量，並且防止其他污染物與POL子模組14接觸。根據本發明之實施例，擴散阻障層28包括由有機材料、無機材料、陶瓷材料及其任意組合形成之一或多個層，其中此等材料通常為反應電漿物種之反應或再結合產物。形成擴散阻障層28之層或層堆疊具有較低之濕氣及氣體通過其之擴散/傳遞以共同地減少濕氣及氣體進入至POL結構10中。可經由許多合適程序之任一者 (諸如一電漿增強化學氣相沈積程序)施加擴散阻障層28，且擴散阻障層28具有所要厚度(諸如，在一個原子層直至25微米至100微米之範圍中之厚度)，使得層28不干擾LGA/BGA焊料凸塊17之可焊接性。擴散阻障層28組態為在一低溫(諸如不超過約攝氏250至300度之一溫度)下施加之一非導電層。
參考圖10A，根據本發明之一實施例，在將POL子模組14施加至基板結構18且沈積底部填充材料26之後，將一焊料遮罩層42施加在POL子模組14上之圖案化金屬互連38上以為其銅墊片提供一保護性塗層。作為對焊料之替代，應認識到，層42可由不同於焊料之某種金屬材料組成，諸如Ni或Ni/Au。如圖10A中進一步展示，接著將第二級I/O互連16施加至介電層30之頂部上之焊料遮罩40。在一實施例中，I/O互連16形成為LGA或BGA焊料凸塊17，該等LGA或BGA焊料凸塊17焊接至焊料遮罩42以實現POL結構10至一外部電路之表面安置，其中焊料凸塊17提供在高應力條件下對故障具有抵抗性之一極度可靠之第二級互連結構。在施加焊料遮罩42及第二級I/O互連16之後，接著將擴散阻障層28施加至POL結構10。擴散阻障層28施加在焊料遮罩42及第二級I/O互連16之焊料凸塊17上，而不需要圖案化該層。擴散阻障層28亦沿著POL結構10之側向下延伸且延伸至陶瓷層20或背側DBC層24，使得底部填充材料26亦由擴散阻障層28覆蓋且POL結構10由阻障層28密封。
參考圖10B，根據本發明之另一實施例，在將POL子模組14附接至基板結構18且沈積底部填充材料26之後，直接施加至金屬互連38上而將阻障層28施加至POL結構10。接著，將一焊料遮罩層42施加在擴散阻障層28上以為其銅填隙片提供一保護性塗層，其中焊料遮罩層42亦用於蝕刻擴散阻障層28以在待形成LGA焊料凸塊17之位置處敞開。如圖10B中進一步展示，將第二級I/O互連16施加至介電層30之頂部及 擴散阻障層28之頂部上之焊料遮罩42，其中該等互連呈LGA或BGA焊料凸塊17之形式，該等LGA或BGA焊料凸塊17焊接至焊料遮罩42以實現POL結構10與一外部電路之表面安置。擴散阻障層28沿著POL結構10之側向下延伸且延伸至陶瓷層20或背側DBC層24，使得底部填充材料26亦由擴散阻障層28覆蓋且POL結構10由該阻障層密封。
參考圖10C，根據本發明之另一實施例，在該製程之各種階段將多個擴散阻障層28施加至POL結構10上。即，直接施加至金屬互連38上而將一第一擴散阻障層28A施加至POL結構10。接著，將一焊料遮罩層42施加在擴散阻障層28A上以為其銅填隙片提供一保護性塗層，其中，接著將第二級I/O互連16施加至介電層30之頂部及第一擴散阻障層28A之頂部上之焊料遮罩42，其中該等互連呈LGA或BGA焊料凸塊17之形式。在施加焊料遮罩42及第二級I/O互連16之後，接著將一第二擴散阻障層28B施加至該子模組，其中該第二擴散阻障層28B施加在焊料遮罩42及第二級I/O互連16之焊料凸塊17上，而不需要圖案化該層。該第二擴散阻障層28B經組態使得該層不干擾LGA/BGA焊料凸塊17之可焊接性。此外，第一擴散阻障層28A及/或第二擴散阻障層28B沿著POL結構之側向下延伸且延伸至陶瓷層20或背側DBC層24，使得底部填充材料26亦由擴散阻障層覆蓋且POL結構10由該阻障層密封。
參考圖10D，根據本發明之另一實施例，在將POL子模組14附接至基板結構18且沈積底部填充材料26之後，直接施加至金屬互連38上而將擴散阻障層28施加至POL結構10且擴散阻障層28經組態以用作一焊料遮罩。代替傳統焊料遮罩之功能，增加擴散阻障層28之厚度使得該阻障層提供對金屬互連38之充分保護。在施加擴散阻障層28之後，在其上形成第二級I/O互連16，其中該等互連呈LGA或BGA焊料凸塊17之形式。
現在參考圖11A至圖11C，展示根據本發明之實施例之擴散阻障層28之各種預想建構。如上文闡述，擴散阻障層28包括由有機材料、無機材料、陶瓷材料及其任意組合形成之一或多個層，其中此等材料通常為反應電漿物種之反應或再結合產物。
如圖11A中展示，擴散阻障層28可建構為一單一層50，該單一層50在各個部分都具有一致組合物。根據一實施例，該單一層50可僅由無機及/或陶瓷材料形成，其中無機/陶瓷材料包含由IIA、IIIA、IVA、VA、VIA、VIIA、IB、IIB族元素形成之氧化物、氮化物、碳化物及硼化物、IIIB、IVB、VB族之金屬、稀土元素或其任意組合中之任一者。
如圖11B中所展示，擴散阻障層28可替代地建構為層52、54之一堆疊(即，一多層建構)，諸如一第一層52及一第二層54，然而應認識到，可建構額外層。根據一實施例，取決於與其一起使用之反應物之類型，第一層52可由一或多種有機材料(諸如，碳、氫、氧及(視需要)其他微量元素(諸如硫磺、氮、矽等等))形成，其中產生該塗層中之有機組成物之合適反應物為具有多達15個碳原子之直鏈或支鏈烷烴、烯烴、炔烴、乙醇、乙醛、乙醚、環氧烷烴、芳香族化合物等等。第二層54可由無機及/或陶瓷材料形成，其中該等無機/陶瓷材料包含由IIA、IIIA、IVA、VA、VIA、VIIA、IB、IIB族元素形成之氧化物、氮化物、碳化物及硼化物、IIIB、IVB、VB族之金屬、稀土元素或其任意組合中之任一者。
如圖11C中所展示，根據又另一實施例，擴散阻障層28可建構為具有一分級組成物之一層56，即，層56之組成物跨越該層之厚度而變化，使得層56可稱為具有複數個區域58、60、62。跨越層56之厚度之區域58、60、62之合適塗層組成物為有機、無機或陶瓷材料，諸如上文闡述之有機、無機陶瓷材料。舉例而言，可藉由自矽烷(SiH4)及一 有機材料(諸如，甲烷或二甲苯)產生之電漿之再結合來將碳化矽沈積至一基板上。可自由矽烷、甲烷及氧氣或矽烷及氧化丙烯產生之電漿來沈積碳氧化矽。亦可自由有機矽化合物前體(諸如，四乙氧基矽烷(TEOS)、六甲基二矽氧烷(HMDSO)、六甲基二矽氮烷(HMDSN)、八甲基環四矽氧烷(D4))產生之電漿來沈積碳氧化矽。可自由矽烷及氨產生之電漿沈積氮化矽。可自由酒石酸鋁與氨之一混合物產生之一電漿來沈積氮碳氧化鋁。可選擇其他反應物組合以獲得層56之一所要組成物。藉由改變在反應產物之沈積期間饋送至反應腔以形成該層之反應物之組成物來獲得層56之一分級組成物。
有利的是，本發明之實施例因此提供一POL封裝及互連結構10，其具有提供在POL子模組14之翹曲側上(即，在介電層30之頂部上)之第二級封裝I/O 16，以用於連至一外部電路之一第二級互連，且整個非晶粒側DBC層24可用於熱連接。該POL結構10包括一擴散阻障層28，其經組態以減少濕氣及氣體進入該封裝，以便提供濕氣及氣體相關故障機構之增強可靠性。擴散阻障層28經進一步組態使得其不干擾第二級I/O互連16與一PCB或其他外部電路之可焊接性。
因此，根據本發明之一實施例，一種表面安置結構包括一子模組，該子模組具有：一介電層；至少一個半導體裝置，其附接至該介電層，該至少一個半導體裝置包括由一半導體材料組成之一基板；一第一級金屬互連結構，其電耦合至該至少一個半導體裝置，該第一級金屬互連延伸通過經形成穿過該介電層之介層孔以連接至該至少一個半導體裝置；及一第二級輸入/輸出(I/O)連接件，其電耦合至該第一級金屬互連結構且在與該至少一個半導體裝置相對之一側上形成在該介電層上，其中該第二級I/O連接件經組態以將該子模組連接至一外部電路。該表面安置結構亦包括一多層基板結構，該多層基板結構具有一第一表面及一第二表面，其中該子模組之該至少一個半導體裝置 附接至該多層基板之該第一表面。該表面安置結構進一步包括：一介電材料，該介電材料定位在該介電層與該多層基板結構之第一表面之間且至少部分地圍繞該子模組之至少一個半導體裝置而定位；及一擴散阻障層，其施加在該子模組上、鄰近該第一級I/O連接件及該第二級I/O連接件且向下延伸至該多層基板結構)，其中該擴散基板層經組態以減少濕氣及氣體自一周圍環境進入至該表面安置結構中。
根據本發明之另一實施例，一種製造一表面安置封裝及互連結構之方法包括以下步驟：建構一子模組，該子模組包括至少一個半導體裝置及圍繞該至少一個半導體裝置形成之一封裝結構，其中建構該子模組之步驟進一步包括以下步驟：將該至少一個半導體裝置附接至一介電層；在該介電層上形成一第一級金屬互連結構，該第一級金屬互連結構延伸通過該介電層中之介層孔以電連接至該至少一個半導體裝置；及在與該至少一個半導體裝置相對之一側上在該介電層上形成一第二級輸入/輸出(I/O)連接件，其中該第二級I/O連接件經組態以將該子模組連接至一外部電路。該方法亦包括以下步驟：形成一基板結構，該基板結構包括一中心基板層及位於該中心基板層之相對側上之第一金屬層及第二金屬層，使得該第一金屬層及該第二金屬層分別形成該基板結構之一第一表面及一第二表面；將該子模組附接至該基板結構之第一表面；及在該介電層與該基板結構之第一表面之間提供一介電材料，其中該介電材料至少部分地囊封該子模組之至少一個半導體裝置。該方法進一步包括以下步驟：施加一擴散阻障層，該擴散阻障層施加在該子模組上、鄰近該第二級I/O連接件且向下延伸至該多層基板結構，其中該擴散阻障層經組態以減少濕氣及氣體自一周圍環境進入至該表面安置封裝及互連結構中。
根據本發明之又另一實施例，一種POL封裝結構包括一POL子模組，該POL子模組具有：一介電層；複數個半導體裝置，其附接至該 介電層；第一級互連結構，其電耦合至該複數個半導體裝置，該第一級互連結構延伸通過經形成穿過該介電層之介層孔以連接至該複數個半導體裝置；及一第二級互連結構，其將該POL子模組電耦合至一外部電路結構，其中該第二級互連結構包含複數個焊料凸塊，該複數個焊料凸塊形成在該介電層及第一級互連結構上且經組態以製造與該外部電路結構之一互連。該POL封裝結構亦包括一多層基板結構，該多層基板結構具有一第一表面及一第二表面，其中該POL子模組之該複數個半導體裝置附接至該多層基板結構之該第一表面。該多層基板結構進一步包括：一第一直接接合銅(DBC)層，其形成該多層基板結構之第一表面；第二DBC層，其形成該多層基板結構之第二表面；及一陶瓷層，其夾在該第一DBC層與該第二DBC層之間。該POL封裝結構進一步包括：一囊封材料，其定位在該介電層與該多層基板結構之該第一表面之間且至少部分地圍繞該子模組之該複數個半導體裝置而定位；及一擴散阻障層，其施加在該POL子模組上、鄰近該第二級互連結構且向下延伸至該多層基板結構，其中該擴散阻障層經組態以減少濕氣及氣體自一周圍環境進入至POL封裝結構中。
雖然已僅結合有限數目之實施例詳細描述本發明，但應容易地理解，本發明不限於此等所揭示之實施例。相反，本發明可經修改以併入本文中未描述但與本發明之精神及範圍相稱之任意數目之變型、變更、替代或等效配置。此外，雖然已描述本發明之各種實施例，但應理解，本發明之態樣可僅包括所描述之實施例中之一些。因此，本發明不視為由以上描述限制，而僅由隨附申請專利範圍之範疇限制。
10‧‧‧POL結構
12‧‧‧半導體裝置
14‧‧‧POL子模組14
16‧‧‧第二級I/O連接件/第二級I/O互連
17‧‧‧焊料凸塊
18‧‧‧基板結構
20‧‧‧陶瓷磚/陶瓷層
22‧‧‧直接接合銅(DBC)層/頂DBC層/晶粒側DBC層/金屬材料片
24‧‧‧直接接合銅(DBC)層/底DBC層24/非晶粒側DBC層/背側DBC層/金屬材料片
26‧‧‧介電材料/聚合物底部填充材料/囊封材料/模製化合物
28‧‧‧擴散阻障層

Claims (20)

  1. 一種表面安置結構，其包含：一子模組，該子模組包含：一介電層；至少一個半導體裝置，其附接至該介電層，其中該至少一個半導體裝置之各者包括由一半導體材料組成之一基板；一第一級金屬互連結構，其電耦合至該至少一個半導體裝置，該金屬互連結構延伸通過經形成穿過該介電層之介層孔以連接至該至少一個半導體裝置；及一第二級輸入/輸出(I/O)連接件，其電耦合至該第一級金屬互連結構且在與該至少一個半導體裝置相對之一側上形成在該介電層上，該第二級I/O連接件經組態以將該子模組連接至一外部電路；一多層基板結構，其具有一第一表面及一第二表面，其中該子模組之該至少一個半導體裝置附接至該多層基板之該第一表面；一介電材料，其定位在該介電層與該多層基板結構之該第一表面之間且至少部分地圍繞該子模組之該至少一個半導體裝置而定位；及一擴散阻障層，其施加在該子模組上、鄰近該第一級I/O連接件及該第二級I/O連接件且向下延伸至該多層基板結構，該擴散阻障層經組態以減少濕氣及氣體自一周圍環境進入至該表面安置結構中。
  2. 如請求項1之表面安置結構，其中該擴散阻障層包含有機材料、無機材料、陶瓷材料及其任意組合。
  3. 如請求項2之表面安置結構，其中該無機材料或陶瓷材料包含由IIA、IIIA、IVA、VA、VIA、VIIA、IB、IIB族元素形成之氧化物、氮化物、碳化物及硼化物、IIIB、IVB、VB族之金屬、稀土元素及其任意組合。
  4. 如請求項1之表面安置結構，其中該擴散阻障層包含一單一層阻障、一多層阻障及一分級組成物阻障之一者，該分級組成物阻障具有跨越在有機材料與無機材料間之該擴散阻障層之一厚度而變化之一組成物。
  5. 如請求項1之表面安置結構，其進一步包含施加在該第一級金屬互連結構上之一焊料遮罩；且其中該第二級I/O連接件包含平台格柵陣列(LGA)焊料凸塊及球格柵陣列(BGA)焊料凸塊中之一者，該等焊料凸塊經組態以在所要位置穿過該焊料遮罩以電耦合至該第一級金屬互連結構。
  6. 如請求項5之表面安置結構，其中該擴散阻障層施加在該第一級金屬互連結構與該焊料遮罩之間。
  7. 如請求項5之表面安置結構，其中該擴散阻障層施加在該焊料遮罩上且施加在該第二級I/O連接件之焊料凸塊上或周圍。
  8. 如請求項1之表面安置結構，該擴散阻障層施加在該第一級金屬互連結構上且經進一步組態以用作一焊料遮罩。
  9. 如請求項1之表面安置結構，其中該擴散阻障層具有在一個原子層與100微米之間之一厚度。
  10. 如請求項1之表面安置結構，其中該多層基板結構包含：一陶瓷絕緣層；一第一金屬層，其定位在該絕緣層之一側上以形成該多層基板結構之該第一表面；及一第二金屬層，其定位在該絕緣層之另一側上以形成該多層 基板結構之該第二表面；其中該第一金屬層及該第二金屬層包含第一及第二直接接合銅(DBC)層。
  11. 如請求項1之表面安置結構，其中該子模組包含一電力覆疊(POL)子模組。
  12. 一種製造一表面安置封裝及互連結構之方法，其包含：建構一子模組，該子模組包括至少一個半導體裝置及圍繞該至少一個半導體裝置形成之一封裝結構，其中建構該子模組包含：將該至少一個半導體裝置附接至一介電層；在該介電層上形成一第一級金屬互連結構，該第一級金屬互連結構延伸通過該介電層中之介層孔以電連接至該至少一個半導體裝置；及在與該至少一個半導體裝置相對之一側上在該介電層上形成一第二級輸入/輸出(I/O)連接件，該第二級I/O連接件經組態以將該子模組連接至一外部電路；形成一基板結構，該基板結構包含一中心基板層及位於該中心基板層之相對側上之該第一金屬層及該第二金屬層，使得該第一金屬層及該第二金屬層分別形成該基板結構之一第一表面及一第二表面；將該子模組附接至該基板結構之該第一表面；在該介電層與該基板結構之該第一表面之間提供一介電材料，該介電材料至少部分地囊封該子模組之該至少一個半導體裝置；及施加一擴散阻障層，其施加在該子模組上、鄰近該第二級I/O連接件且向下延伸至該多層基板結構，該擴散阻障層經組態以 減少濕氣及氣體自一周圍環境進入至該表面安置封裝及互連結構中。
  13. 如請求項12之方法，其進一步包含在該第一級金屬互連結構上施加一焊料遮罩，其中該第二級I/O連接件在預定位置處延伸通過該焊料遮罩。
  14. 如請求項13之方法，其中施加該擴散阻障層包含：在該第一級金屬互連結構與該焊料遮罩之間施加該擴散阻障層。
  15. 如請求項13之方法，其中施加該擴散阻障層包含：在該焊料遮罩上且在該第二級I/O連接件上或周圍施加該擴散阻障層。
  16. 如請求項12之方法，其中施加該擴散阻障層包含：施加一有機材料、一無機材料、一陶瓷材料或其任意組合之一或多個層。
  17. 如請求項12之方法，其中該擴散阻障層經施加以具有在一個原子層與100微米之間之一厚度。
  18. 一種電力覆疊(POL)封裝結構，其包含：一POL子模組，該POL子模組包含：一介電層；複數個半導體裝置，其附接至該介電層；一第一級互連結構，其電耦合至該複數個半導體裝置，該第一級互連結構延伸通過經形成穿過該介電層之介層孔以連接至該複數個半導體裝置；及一第二級互連結構，其將該POL子模組電耦合至一外部電路結構，該第二級互連結構包含複數個焊料凸塊，該複數個焊料凸塊形成在該介電層及該第一級互連結構上且經組態以製造與該外部電路結構之一互連；一多基板結構，其具有一第一表面及一第二表面，其中該POL子模組之該複數個半導體裝置附接至該多層基板結構之該第一 表面，且其中該多層基板結構包括：一第一直接接合銅(DBC)層，其形成該多層基板結構之該第一表面；一第二DBC層，其形成該多層基板結構之該第二表面；及一陶瓷層，其夾在該第一DBC層與該第二DBC層之間；一囊封材料，其定位在該介電層與該多層基板結構之該第一表面之間且至少部分地圍繞該子模組之該複數個半導體裝置而定位；及一擴散阻障層，其施加在該POL子模組上、鄰近該第二級互連結構且向下延伸至該多層基板結構，該擴散阻障層經組態以減少濕氣及氣體自一周圍環境進入至該POL封裝結構中。
  19. 如請求項18之POL封裝結構，其進一步包含施加在該第一級金屬互連結構上之一焊料遮罩，其中該擴散阻障層施加在該第一級金屬互連結構與該焊料遮罩之間之一位置及在該焊料遮罩上方且在該複數個焊料凸塊上方之一位置之至少一者中。
  20. 如請求項18之POL封裝結構，其中該擴散阻障層係由有機材料、無機材料、陶瓷材料及其任意組合組成。
TW102125294A 2012-07-30 2013-07-15 用於表面安置模組之擴散阻障 TWI588957B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US13/561,868 US9299630B2 (en) 2012-07-30 2012-07-30 Diffusion barrier for surface mount modules

Publications (2)

Publication Number Publication Date
TW201409635A true TW201409635A (zh) 2014-03-01
TWI588957B TWI588957B (zh) 2017-06-21

Family

ID=48803437

Family Applications (1)

Application Number Title Priority Date Filing Date
TW102125294A TWI588957B (zh) 2012-07-30 2013-07-15 用於表面安置模組之擴散阻障

Country Status (7)

Country Link
US (1) US9299630B2 (zh)
EP (1) EP2693470B1 (zh)
JP (1) JP6266251B2 (zh)
KR (1) KR102089926B1 (zh)
CN (1) CN103579136B (zh)
SG (2) SG196754A1 (zh)
TW (1) TWI588957B (zh)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8987876B2 (en) * 2013-03-14 2015-03-24 General Electric Company Power overlay structure and method of making same
US10269688B2 (en) 2013-03-14 2019-04-23 General Electric Company Power overlay structure and method of making same
KR102117477B1 (ko) * 2015-04-23 2020-06-01 삼성전기주식회사 반도체 패키지 및 반도체 패키지의 제조방법
US9711713B1 (en) 2016-01-15 2017-07-18 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure, electrode structure and method of forming the same
US10453786B2 (en) * 2016-01-19 2019-10-22 General Electric Company Power electronics package and method of manufacturing thereof
CN205807211U (zh) * 2016-06-20 2016-12-14 冯霞 用于容器的发光装置
FR3061404B1 (fr) * 2016-12-27 2022-09-23 Packaging Sip Procede de fabrication collective de modules electroniques hermetiques
US10804115B2 (en) 2017-08-03 2020-10-13 General Electric Company Electronics package with integrated interconnect structure and method of manufacturing thereof
US10541153B2 (en) 2017-08-03 2020-01-21 General Electric Company Electronics package with integrated interconnect structure and method of manufacturing thereof
US10541209B2 (en) 2017-08-03 2020-01-21 General Electric Company Electronics package including integrated electromagnetic interference shield and method of manufacturing thereof
US10332832B2 (en) 2017-08-07 2019-06-25 General Electric Company Method of manufacturing an electronics package using device-last or device-almost last placement
US10685935B2 (en) * 2017-11-15 2020-06-16 Taiwan Semiconductor Manufacturing Company, Ltd. Forming metal bonds with recesses
CN108098093B (zh) * 2017-12-01 2020-04-03 温州宏丰电工合金股份有限公司 一种用于不锈钢真空钎焊的阻流剂
CN108044259B (zh) * 2017-12-01 2020-04-03 温州宏丰电工合金股份有限公司 一种用于不锈钢真空钎焊的阻流剂的制备方法
EP4401126A3 (en) 2018-01-30 2024-09-25 Infineon Technologies AG Power semiconductor module and method for producing the same
EP3780087A4 (en) * 2018-03-26 2022-01-12 Mitsubishi Materials Corporation METHOD OF MANUFACTURE OF CONNECTED BODY FOR INSULATION OF A CIRCUIT BOARD AND CONNECTED BODY FOR INSULATION OF A CIRCUIT BOARD
US11538769B2 (en) 2018-12-14 2022-12-27 General Electric Company High voltage semiconductor devices having improved electric field suppression
US10892237B2 (en) * 2018-12-14 2021-01-12 General Electric Company Methods of fabricating high voltage semiconductor devices having improved electric field suppression
US11398445B2 (en) 2020-05-29 2022-07-26 General Electric Company Mechanical punched via formation in electronics package and electronics package formed thereby
WO2023190106A1 (ja) * 2022-03-31 2023-10-05 株式会社Flosfia 半導体装置
WO2023190107A1 (ja) * 2022-03-31 2023-10-05 株式会社Flosfia 半導体装置

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5250843A (en) 1991-03-27 1993-10-05 Integrated System Assemblies Corp. Multichip integrated circuit modules
TW272311B (zh) * 1994-01-12 1996-03-11 At & T Corp
US7653215B2 (en) * 1997-04-02 2010-01-26 Gentex Corporation System for controlling exterior vehicle lights
US6306680B1 (en) 1999-02-22 2001-10-23 General Electric Company Power overlay chip scale packages for discrete power devices
US6154366A (en) 1999-11-23 2000-11-28 Intel Corporation Structures and processes for fabricating moisture resistant chip-on-flex packages
US6551148B1 (en) * 2001-10-19 2003-04-22 Hewlett-Packard Development Company, L.P. Electrical connector with minimized non-target contact
US7015640B2 (en) 2002-09-11 2006-03-21 General Electric Company Diffusion barrier coatings having graded compositions and devices incorporating the same
US7169345B2 (en) * 2003-08-27 2007-01-30 Texas Instruments Incorporated Method for integrated circuit packaging
WO2005051525A1 (en) 2003-11-25 2005-06-09 Polyvalor, Limited Partnership Permeation barrier coating or layer with modulated properties and methods of making the same
US7262444B2 (en) * 2005-08-17 2007-08-28 General Electric Company Power semiconductor packaging method and structure
US8018056B2 (en) * 2005-12-21 2011-09-13 International Rectifier Corporation Package for high power density devices
US7733554B2 (en) 2006-03-08 2010-06-08 E Ink Corporation Electro-optic displays, and materials and methods for production thereof
US20070295387A1 (en) 2006-05-05 2007-12-27 Nanosolar, Inc. Solar assembly with a multi-ply barrier layer and individually encapsulated solar cells or solar cell strings
US7688497B2 (en) 2007-01-22 2010-03-30 E Ink Corporation Multi-layer sheet for use in electro-optic displays
US9953910B2 (en) * 2007-06-21 2018-04-24 General Electric Company Demountable interconnect structure
JP5241177B2 (ja) * 2007-09-05 2013-07-17 株式会社オクテック 半導体装置及び半導体装置の製造方法
US20100308468A1 (en) * 2008-03-14 2010-12-09 Noriyuki Yoshikawa Semiconductor device and semiconductor device fabrication method
DE102008028757B4 (de) * 2008-06-17 2017-03-16 Epcos Ag Verfahren zur Herstellung einer Halbleiterchipanordnung
US8358000B2 (en) * 2009-03-13 2013-01-22 General Electric Company Double side cooled power module with power overlay
WO2011103341A1 (en) 2010-02-18 2011-08-25 Alliance For Sustainable Energy, Llc Moisture barrier
JP2010212698A (ja) * 2010-04-01 2010-09-24 Sony Chemical & Information Device Corp 接続構造体及びその製造方法
US8531027B2 (en) * 2010-04-30 2013-09-10 General Electric Company Press-pack module with power overlay interconnection
US8114712B1 (en) * 2010-12-22 2012-02-14 General Electric Company Method for fabricating a semiconductor device package

Also Published As

Publication number Publication date
US20140029210A1 (en) 2014-01-30
US9299630B2 (en) 2016-03-29
JP6266251B2 (ja) 2018-01-24
KR102089926B1 (ko) 2020-04-14
CN103579136A (zh) 2014-02-12
KR20140016192A (ko) 2014-02-07
EP2693470A2 (en) 2014-02-05
CN103579136B (zh) 2018-03-06
EP2693470B1 (en) 2020-10-28
EP2693470A3 (en) 2015-07-22
SG196754A1 (en) 2014-02-13
TWI588957B (zh) 2017-06-21
SG10201508888UA (en) 2015-11-27
JP2014027277A (ja) 2014-02-06

Similar Documents

Publication Publication Date Title
TWI588957B (zh) 用於表面安置模組之擴散阻障
US9184124B2 (en) Reliable surface mount integrated power module
US10186477B2 (en) Power overlay structure and method of making same
US8653635B2 (en) Power overlay structure with leadframe connections
KR102295990B1 (ko) 임베딩된 반도체 디바이스 패키지 및 그 제조 방법
KR100851072B1 (ko) 전자 패키지 및 그 제조방법
TW201620074A (zh) 用於嵌入式半導體裝置封裝的電性互連結構及其製造方法
JP2018120902A (ja) 電力用電子回路パッケージおよびその製造方法
TWI657546B (zh) 設有電隔離件及基底板之線路板、其半導體組體及其製法
TWI447882B (zh) 包括混合框架面板的互連構造
CN108428689B (zh) 功率电子设备组件及其制造方法
TWI697077B (zh) 功率電子封裝及其製造方法
KR100836657B1 (ko) 전자 패키지 및 그 제조방법
KR20180092379A (ko) 전력 전자 패키지 및 그 제조 방법