TW201409571A - 三維半導體電路結構及其製法 - Google Patents

三維半導體電路結構及其製法 Download PDF

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TW201409571A
TW201409571A TW101130435A TW101130435A TW201409571A TW 201409571 A TW201409571 A TW 201409571A TW 101130435 A TW101130435 A TW 101130435A TW 101130435 A TW101130435 A TW 101130435A TW 201409571 A TW201409571 A TW 201409571A
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semiconductor
circuit structure
circuit layer
metal circuit
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TWI532100B (zh
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Yang-Kuo Kuo
Chia-Yi Hsiang
Hung-Tai Ku
Ruei-Fong Jiang
Ming-Cheng Liu
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Chung Shan Inst Of Science
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Abstract

一種三維半導體電路結構及其製法，其結構係包括：一上方具有第一金屬電路層之基板、一設置於該第一金屬電路層上，並與該第一金屬電路層電性之中介層、及設置於該中介層上之至少一半導體元件，藉由該中介層排除各該半導體元件作動時所產生之溫度，以達到提高半導體元件壽命之目的。

Description

三維半導體電路結構及其製法
本發明係有關於一種三維半導體電路結構及其製法，特別是指一種利用一氮化鋁作為中介層之三維半導體電路結構。
電子產品朝向輕薄短小、高效能發展，高度系統整合與無線化的設計方式，會成為日後電子產業所發展之方向，三維積體電路為晶片三維堆疊整合模式，不僅可以縮短金屬導線長度及導線電阻，更能減少晶片面積，具有縮小體積、提高整合度、降低耗電量、及減少製作成本的目的，然而，於半導體體積縮小或多層堆疊後，容易發生半導體結構溫度提高，且於長時間高溫情況下，易使半導體元件因高溫而降低元件使用壽命，與效能降低。以往使用矽基板需製造一層二氧化矽絕緣層，但此絕緣層容易發生漏電現象，而影響半導體元件之壽命。
有鑑於此，如何解決半導體結構溫度提高及漏電現象，進而影響半導體元件壽命之問題，亟待解決之課題。
本發明主要之目的，在於提供一種三維半導體電路結構及其製法，以一氮化鋁作為三維半導體電路結構之中介層，排除半導體元件作動時所產生之溫度，藉以達到提高半導體元件壽命之目的。
本發明之另一目的，在於提供一種三維半導體電路結構及其製法，透過一氮化鋁製作成一中介層降低三維半導體電路結構之溫度，避免半導體元件於高溫狀態而降低壽命，該氮化鋁製作之中介層為絕緣材料，可有效阻絕電能，及解決漏電問題。
為達上述之目的，本發明提供一種三維半導體電路結構，其結構係包括，一基板、一中介層及至少一半導體元件，其中，該基板上方形成有一第一金屬電路層，於該第一金屬電路層上設置一中介層，該中介層係具有複數貫穿開孔，於該貫穿開孔內填滿導體，該中介層一側形成有複數導電墊，另一側形成有一第二金屬電路層，透過該導電墊電性連接於該第一金屬電路層，於該中介層上電性連接有至少一半導體元件，其中，該中介層係由一氮化鋁製作而成，藉由該中介層排除各該半導體元件作動時所產生之溫度，及避免各該半導體元件產生高溫狀態及漏電現象，進而提高各該半導體元件之壽命。
以下藉由特定的具體實例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點與功效。
氮化鋁基板可製造成一晶圓，該晶圓可製作成2吋、4吋、6吋、8吋、12吋與18吋等標準尺寸，或其他規格之非標準尺吋，該晶圓除可製成圓形外亦可製成方形與長方形， 並利用該晶圓使用半導體設備與製程方法製造本案之中介層。
請參閱第1圖，如圖所示，係為本發明之三維半導體電路結構第一實施態樣示意圖。
本發明三維半導體電路結構在一較佳實施例，係包括一具有第一金屬電路層101之基板10、一電性連接於該第一金屬電路層101上之中介層11，以及至少一半導體元件12，其中，該中介層11係由一氮化鋁製做而成，該中介層11亦可選自一氮化矽、一氧化鋁、一碳化矽或一氮化鎵製作而成，並利用雷射穿孔、半導體蝕刻或噴砂噴孔方式，於該中介層11上形成複數貫穿開孔111。
而在該中介層11之一側形成複數導電墊112，另一側形成有一第二金屬電路層113，於該貫穿開孔111內填滿有導體，並透過該第二金屬電路層113與各該半導體元件12之周緣電性連接區電性連接，藉由該中介層11排除各該半導體元件12作動時所產生之溫度，及避免各該半導體元件12於高溫狀態下產生之漏電現象，進而提高各該半導體元件12之壽命。
請參閱第2圖，如圖所示，係為本發明一種三維半導體電路結構另一實施態樣示意圖。
該三維半導體電路結構在另一較佳實施例，係包括一上方形成有第一金屬電路層201之基板20，設置於該第一金屬電路層201上之中介層21，設置於該中介層21上之至少一半導體元件22，及形成於該中介層21及各該半導體元件22 上之保護層23，其中，該中介層21係具有複數貫穿開孔211，該中介層21一側形成有複數導電墊212，另一側形成有一第二金屬電路層213，於該複數貫穿開孔211內填滿導體，藉以電性連接該基板20及該第二金屬電路層213，而各該半導體元件22係透過周緣之電性連接區電性連接於該第二金屬電路層213，藉由形成於該中介層21及各該半導體元件22上之保護層23，達到降低外部水氣等物質影響，並利用該中介層21，排除各該半導體元件22作用時所產生之溫度，以防止高溫狀態下，各該半導體元件22所產生之漏電現象，更進一步達到提高各該半導體元件22壽命之目的。
請參閱第3圖，如圖所示，係為本發明三維半導體電路結構之製作法流程圖，其步驟包括：步驟一S1：提供一基板10、20，該基板10、20之一側形成有一第一金屬電路層101、201；步驟二S2：提供一具有複數貫穿開孔之中介層11、21，該中介層11、21之一側形成有一第二金屬電路層113、213，另一側形成有複數導電墊112、212，於該貫穿開孔內填滿導體；步驟三S3：將該中介層11、21置於該基板10、2上，並透過該等導電墊112、212電性連接該第一金屬電路層101、201；步驟四S4：於該第二金屬電路層113、213上，設置至少一半導體元件12、22，且各該半導體元件12、22係電性連接於該中介層11、21，藉由該中介層11、21排除各該半導 體元件12、22所產生之溫度，以降低各該半導體元件12、22在高溫狀態下所產生之漏電現象。
再者，於該步驟四S4中，各該半導體元件12、22電性連接於該中介層11、21後，在該中介層11、21及各該半導體元件12、22上形成一保護層23，同樣藉由該中介層11、21排除各該半導體元件12、22所產生之溫度，降低各該半導體元件12、22在高溫狀態下所產生之漏電。
上列詳細說明係針對本發明之一可行實施例之具體說明，惟該實施例並非用以限制本發明之專利範圍，凡未脫離本發明技藝精神所為之等效實施或變更，例如：等變化之等效性實施例，均應包含於本案之專利範圍中。
10、20‧‧‧基板
11、21‧‧‧中介層
12、22‧‧‧半導體元件
23‧‧‧保護層
101、201‧‧‧第一金屬電路層
111、211‧‧‧貫穿開孔
112、212‧‧‧導電墊
113、213‧‧‧第二金屬電路層
S1~S4‧‧‧步驟
第1圖係為本發明之三維半導體電路結構第一實施態樣示意圖；第2圖係為本發明三維半導體電路結構另一實施態樣示意圖；以及第3圖係為本發明三維半導體電路結構之製作法流程圖。
10‧‧‧基板
11‧‧‧中介層
12‧‧‧半導體元件
101‧‧‧第一金屬電路層
111‧‧‧貫穿開孔
112‧‧‧導電墊
113‧‧‧第二金屬電路層

Claims (20)

  1. 一種三維半導體電路結構，係包括：一基板，其上方形成有一第一金屬電路層；一中介層，設置於該第一金屬電路層上，且該中介層具有複數貫穿開孔，於該中介層一側形成有複數導電墊，另一側形成有一第二金屬電路層，於該等貫穿開孔內填滿導體，透過該導體電性連接該基板之第一金屬電路層；以及至少一半導體元件，係設置於該中介層上，與該第二金屬電路層電性連接，藉由該中介層排除半導體元件作動時所產生之溫度，及避免半導體元件於高溫狀態下產生之漏電現象。
  2. 如申請專利範圍第1項所述之三維半導體電路結構，其中該中介層，係為一氮化鋁、一氮化矽、一氧化鋁、一碳化矽及一氮化鎵之其中一者。
  3. 如申請專利範圍第1項所述之三維半導體電路結構，其中該等貫穿開孔，係透過雷射穿孔、半導體蝕刻及噴砂噴孔方式之其中一者形成。
  4. 如申請專利範圍第1項所述之三維半導體電路結構，其中該半導體元件之周緣，係具有電性連接區。
  5. 如申請專利範圍第4項所述之三維半導體電路結構，其中該電性連接區，係為複數導電墊。
  6. 一種三維半導體電路結構，係包括：一基板，其上方形成有一第一金屬電路層；一中介層，設置於該第一金屬電路層上，且該中介層具有複 數貫穿開孔，於該中介層一側形成有複數導電墊，另一側形成有一第二金屬電路層，於該貫穿開孔內填滿一導體，透過該導體電性連接該基板之第一金屬電路層；至少一半導體元件，係設置於該中介層上，與該第二金屬電路層電性連接；以及一保護層，係形成於該中介層及該等半導體元件，藉由該中介層排除該等半導體元件作動時所產生之溫度，及避免該等半導體元件於高溫狀態下產生之漏電現象，進而提高半導體元件之壽命。
  7. 如申請專利範圍第6項所述之三維半導體電路結構，其中該中介層，係為氮化鋁、氮化矽、氧化鋁、碳化矽及氮化鎵之其中一者。
  8. 如申請專利範圍第6項所述之三維半導體電路結構，其中該貫穿開孔，係透過雷射穿孔、半導體蝕刻及噴砂噴孔方式形成其中之一者。
  9. 如申請專利範圍第6項所述之三維半導體電路結構，其中該半導體元件周緣，係具有電性連接區。
  10. 如申請專利範圍第9項所述之三維半導體電路結構，其中該電性連接區，係為複數導電墊。
  11. 一種三維半導體電路結構之製法，係包括：提供一基板，於該基板一側形成第一金屬電路層；提供一具有複數貫穿開孔之中介層，於該貫穿開孔內填滿導體； 於該中介層之一側形成複數導電墊，另一側形成第二金屬電路層，透過該導體電性連接第一金屬電路層；提供至少一半導體元件；以及將該等半導體元件設置於該中介層上，並電性連接該第二金屬電路層，藉由該中介層排除半導體元件作動時所產生之溫度，及避免半導體元件於高溫狀態下產生之漏電現象。
  12. 如申請專利範圍第11項所述之三維半導體電路結構之製法，其中該中介層，係為氮化鋁、氮化矽、氧化鋁、碳化矽及氮化鎵之其中一者。
  13. 如申請專利範圍第11項所述之三維半導體電路結構之製法，其中該貫穿開孔，係透過雷射穿孔、半導體蝕刻及噴砂噴孔方式之其中一者形成。
  14. 如申請專利範圍第11項所述之三維半導體電路結構之製法，其中該半導體元件周緣，係具有電性連接區。
  15. 如申請專利範圍第14項所述之三維半導體電路結構之製法，其中該電性連接區，係為複數導電墊。
  16. 一種三維半導體電路結構之製法，係包括：提供一基板，於該基板一側形成第一金屬電路層；提供一具有複數貫穿開孔之中介層，於該貫穿開孔內填滿導體；於該中介層之一側形成複數導電墊，另一側形成第二金屬電路層，透過該導體電性連接第一金屬電路層；提供至少一半導體元件； 將該等半導體元件設置於該中介層上，並電性連接該第二金屬電路層；以及於該中介層及各該半導體元件上形成一保護層，藉由該中介層排除半導體元件作動時所產生之溫度，及避免半導體元件於高溫狀態下產生之漏電現象。
  17. 如申請專利範圍第16項所述之三維半導體電路結構之製法，其中該中介層，係為氮化鋁、氮化矽、氧化鋁、碳化矽及氮化鎵之其中一者。
  18. 如申請專利範圍第16項所述之三維半導體電路結構之製法，其中該貫穿開孔，係透過雷射穿孔、半導體蝕刻及噴砂噴孔方式之其中一者形成。
  19. 如申請專利範圍第16項所述之三維半導體電路結構之製法，其中該半導體元件周緣，係具有電性連接區。
  20. 如申請專利範圍第19項所述之三維半導體電路結構之製法，其中該電性連接區，係為複數導電墊。
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