TW201349420A - 半導體裝置及其製作方法 - Google Patents

半導體裝置及其製作方法 Download PDF

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Publication number
TW201349420A
TW201349420A TW102119062A TW102119062A TW201349420A TW 201349420 A TW201349420 A TW 201349420A TW 102119062 A TW102119062 A TW 102119062A TW 102119062 A TW102119062 A TW 102119062A TW 201349420 A TW201349420 A TW 201349420A
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Taiwan
Prior art keywords
layer
diameter
bump
microns
contact pad
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TW102119062A
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English (en)
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TWI625835B (zh
Inventor
Yao-Chun Chuang
Chi-Ta Chuang
Hao-Juin Liu
Chen-Cheng Kuo
Chen-Shien Chen
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Taiwan Semiconductor Mfg
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Publication of TW201349420A publication Critical patent/TW201349420A/zh
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Publication of TWI625835B publication Critical patent/TWI625835B/zh

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Abstract

本發明提供一種系統及方法，以防止鈍化保護層中的裂縫發生。在一實施例中，一接觸墊具有第一直徑，穿透鈍化保護層之一開口具有第二直徑，其中第一直徑比第二直徑大上一第一距離，其約為10微米。在另一實施例中，一凸塊底層金屬層穿過上述開口且具有一第三直徑，其中第三直徑比第一直徑大上一第二距離，其為5微米。在又一實施例中，第一距離及第二距離的總和大於15微米。

Description

半導體裝置及其製作方法
本發明提供一種半導體裝置及其製作方法，且特別是關於一種用以減少鈍化保護層中裂縫數目之半導體裝置及其製作方法。
一般而言，半導體晶粒可藉由使用外部連接元件之封裝連接至半導體晶粒外部之其它裝置。外部連接元件可藉由先形成一凸塊底層金屬層以電性連接至半導體晶粒中的一接觸墊，隨後於凸塊底層金屬層上設置額外導電性材料。在凸塊底層金屬層與接觸墊之間可具有一鈍化保護層，用以保護及支持半導體晶粒的結構。設置完成後，額外導電材料可與外部裝置物理性接觸，且隨後半導體裝置可接合至外部裝置。在這樣的方式中，可於半導體晶粒與外部裝置之間形成一物理性及電性連接，例如印刷電路板、另一半導體晶粒等等。
然而，凸塊底層金屬層、鈍化保護層、及接觸墊的材料包括不同類型的材料，並以不同製程形成及製作於包括不同類型材料之另一者上方，例如介電材料、金屬材料、蝕刻停止材料、阻擋層材料、及用於半導體晶粒形成之其他材料。這些不同材料每個具有不同性質，可能導致顯著應力施加於各層材料中。若不加以控制，這些應力可能造成裂縫形成，例如 在接觸墊與凸塊底層金屬層之間的鈍化保護層。此裂縫可能在製作過程中或其預定用途中損傷甚至摧毀半導體晶粒。
本發明一實施例提供一種半導體裝置，包括：一接觸墊，具有一第一直徑；一凸塊底層金屬層，電性連接至接觸墊，凸塊底層金屬層具有一第二直徑，其中第二直徑比第一直徑大上一第一距離，其為10微米。
本發明另一實施例提供一種半導體裝置，包括：一接觸墊，位於一基板上，接觸墊包括一第一尺寸；一鈍化保護層，至少部分位於接觸墊上；一開口，穿透鈍化保護層，開口包括一第二尺寸；以及一凸塊底層金屬層，延伸通過開口而連接至接觸墊，凸塊底層金屬層包括一第三尺寸，其中該第三尺寸比第一尺寸大上一第一數值，其大於5微米。
本發明又一實施例提供一種半導體裝置之製作方法，包括：於一基板上形成一接觸墊，接觸墊包括一第一直徑；於接觸墊上沉積一鈍化保護層；圖案化鈍化保護層，以形成穿透鈍化保護層的一開口，開口具有比該第一直徑小之一第二直徑；以及形成一凸塊底層金屬層延伸通過開口，凸塊底層金屬層具有一第三直徑，比第一直徑大上一第一距離，其大於5微米。
100‧‧‧半導體裝置
101‧‧‧半導體基板
102‧‧‧主動裝置
103‧‧‧金屬化層
105‧‧‧接觸墊
107‧‧‧第一鈍化保護層
109‧‧‧第一鈍化保護層之開口
200‧‧‧外部接點
201‧‧‧凸塊底層金屬層
203‧‧‧晶種層
205‧‧‧聚合物層
207‧‧‧接點
301‧‧‧第一頂蓋層
303‧‧‧第二頂蓋層
d1‧‧‧第一距離
d2‧‧‧第二直徑
d3‧‧‧第三距離
d4‧‧‧第四直徑
d5‧‧‧第五距離
第1A~1B圖為依據本發明一實施例所繪示之形成接觸墊、鈍化保護層、及穿透鈍化保護層之開口。
第2圖為依據本發明一實施例所繪示之形成一凸塊底層金屬層及外部接點。
第3圖為依據本發明一實施例所繪示之形成第一頂蓋層及第二頂蓋層。
第4圖為依據本發明一實施例所繪示之圖案化的凸塊底層金屬層。
第5圖繪示了實施例的實驗數據。
第6A~6C圖為依據本發明一實施例所繪示之其它實驗數據。
第7圖為依據本發明一實施例所繪示之回焊製程。
以下說明本發明實施例之製作與使用。然而，可輕易了解本發明實施例提供許多合適的發明概念而可實施於廣泛的各種特定背景。所揭示的特定實施例僅僅用於說明以特定方法製作及使用本發明，並非用以侷限本發明的範圍。
實施例係實施於廣泛的各種特定背景，亦即一鈍化保護層、凸塊底層金屬層、及銅柱體形成於一接觸墊上。亦可實施其它實施例，但需其它類型的外部接點。
參考第1圖，其繪示了半導體裝置100之一實施例的一部分。在一實施例中，半導體裝置100可包括半導體基板101、主動裝置102、金屬化層103、接觸墊105、及第一鈍化保護層107。半導體基板101可包括摻雜或不摻雜之矽塊材或絕緣層上覆矽(silicon-on-insulator，SOI)基板。一般而言，絕緣層上覆矽基板包括一層半導體材料，例如矽、鍺、矽化鍺、絕 緣層上矽、絕緣層上覆矽化鍺(silicon germanium on insulator，SGOI)或前述之組合。其它可使用的基板包括：多層基板、漸變基板或混晶向基板。
主動裝置102可形成於半導體基板101上(在第1A圖中繪示為一單一電晶體)。本發明所屬技術領域中具有通常知識者應知亦可使用不同主動裝置及被動裝置，例如電容、電阻、電感等，以得到具有所需結構及功能需求之半導體裝置100的設計。主動裝置102可使用任何適當方法形成於半導體基板101中或其表面上。
然而，本發明所屬技術領域中具有通常知識者應知上述具有主動裝置102之半導體基板101並非唯一可用基板。亦可選用其它基板，例如不具有主動裝置之一封裝基板或轉接板(interposer)。可選用這些基板及任何其它適當基板，且其包括於本發明實施例的範圍之內。
金屬化層103形成於半導體基板101及主動裝置102上，並設計為連接各種主動裝置以形成功能電路。雖然第1圖將金屬化層103繪示為一單一層，金屬化層103可以介電層(例如，低介電常數介電材料)及導電材料(例如，銅)交替形成，並可以藉由任何適當製程形成(例如沉積、鑲嵌、雙重鑲嵌等)。在一實施例中，可具有四層金屬化層，其藉由至少一層間介電層(interlayer dielectric layer，ILD)而與半導體基板101分離，但金屬化層103的精確層數取決於半導體裝置100的設計。
接觸墊105可形成於金屬化層103上且與金屬化層 103電性接觸。接觸墊105可包括鋁，亦可使用其它材料(例如銅)。接觸墊105可利用沉積製程(例如濺射)以形成膜層材料(未繪示於圖中)，且部分材料層隨後可藉由適當製程(例如光罩及蝕刻)移除，以形成接觸墊105。然而，任何其它適當製程可用以形成接觸墊105。接觸墊105可形成為具有厚度為介於約0.5微米至約4微米之間，例如約1.45微米。
另外，接觸墊105可以這種方式形成，以減少或消除第一鈍化保護層107中之接觸墊105周圍裂縫發生。特別是，藉由製作與穿透第一鈍化保護層107之開口109(詳述如下)具有特定關係及/或與凸塊底層金屬層201(未繪示於第1圖，繪示並討論於下方參照第2~4圖之討論)具有特定關係之接觸墊105，可大幅減少或甚至消除形成於第一鈍化保護層107中的裂縫數目。在一實施例中，接觸墊105可形成為具有直徑介於約35微米至約100微米之間的第一距離d1，例如約74微米。
可於半導體基板101上形成金屬化層103、接觸墊105、第一鈍化保護層107。第一鈍化保護層107可藉由例如氧化矽、氮化矽、低介電常數介電質(例如摻碳氧化物)、極低介電常數介電材料(例如多孔碳摻雜之二氧化矽)、前述之組合。第一鈍化保護層107可藉由例如化學氣相沉積(chemical vapor deposition，CVD)等方法形成，但可使用任何適當製程，且可具有厚度介於約0.5微米至約5微米之間，例如約9.25KÅ。
形成第一鈍化保護層107之後，可藉由移除部分第一鈍化保護層107以露出下方接觸墊105的至少一部分而形成穿透第一鈍化保護層107之開口109。開口109允許接觸墊105與 凸塊底層金屬層201(詳述如下並參照第2圖)之間的接觸。可使用一適當光罩及蝕刻製程形成開口109，亦可以使用任何適當製程，以露出部分的接觸墊105。
開口亦可製作為具有第二直徑d2，其可與接觸墊105的第一距離d1一同用於減少或消除第一鈍化保護層107中裂縫的發生。在一實施例中，第一開口及接觸墊105(第1圖中以第三距離d3表示)之間的直徑差可保持大於約10微米(每邊為5微米)，例如約11微米。藉由將直徑保持在大於約10微米這樣的差異，可較佳地處理鈍化保護層107中接觸墊105周圍的應力而不產生裂縫，其可能損壞半導體裝置100。
第1B圖繪示了僅增加第三距離d3時，裂縫減少的圖表(圖表中標記之第五距離d5未繪示於第1A圖中，但繪示並討論於下方參照第2~4圖之討論)。特別地，在一實施例中，該實施例之半導體裝置100具有一外部接點200(未繪示於第1A圖，但繪示並討論於下方第2圖)，其具有45/0/0凸塊結構(bump scheme，其中外部接點200具有約45微米之銅層，且沒有額外膜層例如鎳層或無鉛焊料頂蓋)，並在其它所有變量保持恆定時，將第二直徑d2由65微米降低至55微米，這也導致將第三距離d3由9微米增加至19微米。因為此增加之第三距離d3，發生的裂縫數目由74減少至20。如此，藉由控制第三距離d3，可大幅減少第一鈍化保護層107中裂縫的數目，且可改善半導體裝置100的整體效率。
第2圖繪示了形成穿透第一鈍化保護層107且電性連接至接觸墊105的外部接點200。在一實施例中，外部接點200 可為例如銅柱體(pillar/post)，然而實施例不限於此，亦可為焊料凸塊、銅凸塊、或其他可用以提供電性連接之適當外部接點200(未逐一繪示於第2圖中)。所有這樣的外部接點皆包括於實施例的範圍內。
在一實施例中，外部接點200為一銅柱體，外部接點200可藉由先形成一凸塊底層金屬層(under-bump-metallurgy，UBM)201、晶種層203、及具有一開口之聚合物層205而形成。接點207可形成於聚合物層205之開口內。可形成與接觸墊105電性接觸的凸塊底層金屬層201。凸塊底層金屬層201可包括單一層之導電材料，例如鈦層或鎳層。或者，凸塊底層金屬層201可包括複數子層，其未繪示於圖中。本發明所屬技術領域中具有通常知識者應知許多適當材料及膜層排列，例如鉻/鉻銅合金/銅/金之排列、鈦/鈦鎢合金/銅之排列、或銅/鎳/金之排列亦適用於形成凸塊底層金屬層201。任何適當材料或材料層可用於凸塊底層金屬層201，且其完全包括於實施例的範圍之內。可使用例如濺射、蒸鍍、或電漿輔助化學氣相沈積法等製程建立凸塊底層金屬層201，取決於所需的材料。凸塊底層金屬層201可形成為具有介於約0.7微米至約10微米之間的厚度，例如約5微米。
可形成與凸塊底層金屬層201電性接觸於接觸墊105的頂部的晶種層203。晶種層203為一薄層之導電材料，其有助於在隨後的處理步驟中形成較厚層。晶種層203可包括厚度為約1000埃的鈦，隨後形成約5000埃厚的銅，其用以進一步連接至接點207。晶種層203可使用製程例如濺射、蒸鍍、或電 漿輔助化學氣相沈積法，取決於其所需的材料。晶種層203可形成為介於約0.7微米至約10微米之間的厚度，例如約5微米。
可使用塗佈法於晶種層203上形成聚合物層205。聚合物層205可包括苯系聚合物(benzene-based polymers)、二氧陸圜系聚合物(dioxane-based polymers)、甲苯基聚合物(toluene-based polymers)、苯基硫醚類聚合物(phenylthiol-based polymers)、酚系聚合物(phenol-based polymers)、環己烷基聚合物(cyclohexane-based polymers)、p-甲酚系聚合物(p-cresol-based polymers)、前述之組合等，其形成方法包括旋塗法或其他常用方法。聚合物層205的厚度可為介於約5微米至約30微米之間。可使用微影技術形成聚合物層205的開口部，以露出晶種層203預定形成接點207的部分。
接點207包括一種或多種導電性材料，例如銅、鎢、其它導電金屬等等，並可藉由例如電鍍、無電解電鍍等等形成。在一實施例中，使用電鍍製程，其中半導體裝置100浸入或沒入於電鍍液中。半導體裝置100的表面電性連接至一個外部直流電源的負極，以使半導體裝置100在電鍍製程中作為陰極。一固體導電性陽極也浸泡於溶液中，例如一銅陽極，且被連接至電源的正極。陽極原子溶解於溶液中，陰極(例如，半導體裝置100)由此獲得溶解的原子，從而電鍍半導體裝置100露出之導電區域(例如，聚合物層205的開口內之晶種層203的露出部分)。
第3圖繪示了第一頂蓋層301及位於接點207上的第二頂蓋層303。在一實施例中，第一頂蓋層301可形成於接點 207上。例如，在一實施例中，接點207可由銅形成，第一頂蓋層301可由鎳形成，但亦可使用其它材料例如鉑、金、銀、鎳、鈷、釩、鉻、錫、鈀、鉍、鎘、鋅、前述之組合等等。第一頂蓋層301可藉由任何數量之適當技術形成，包括物理氣相沈積法(PVD)、化學氣相沈積法(CVD)、電化學沈積法(ECD)、分子束磊晶法(MBE)、原子層沈積法(ALD)、電鍍法等等。
第二頂蓋層303可形成於第一頂蓋層301上。第二頂蓋層303可包含錫金合金、錫鉛合金、高鉛材料、錫系焊料、無鉛焊料、錫銀焊料、錫銀銅焊料，或其他適當導電材料。第二頂蓋層303可藉由任何數量之適當技術形成，物理氣相沈積法、化學氣相沈積法、電化學沈積法、分子束磊晶法、原子層沈積法、電鍍法等等。
接點207上的膜層數目，例如第一頂蓋層301及第二頂蓋層303，僅用於說明且本發明並不限於此。可具有不同數目的膜層形成於接點207上。接點207上的不同膜層可以不同的材料或形狀形成。接點207、第一頂蓋層301、及第二頂蓋層303可共同視為金屬接點120。
第4圖繪示了聚合物層205的移除及晶種層203與凸塊底層金屬層201的圖案化。在一實施例中，電漿灰化製程可用以移除聚合物層205，其中可增加聚合物層205的溫度，使聚合物層205熱分解而移除。然而，亦可選用任何其它適當製程，例如濕式剝除(wet strip)。移除聚合物層205可露出晶種層203下方的部分。
可移除露出之晶種層203部分，例如藉由濕式或乾 式蝕刻製程。例如，在乾式蝕刻製程中，可將反應物導向晶種層203並使用第一頂蓋層301及第二頂蓋層303作為罩幕。此外，可噴灑蝕刻劑或使其與晶種層203接觸以移除晶種層203的露出部分。蝕刻掉晶種層203的露出部分之後，會露出凸塊底層金屬層201的一部分。
隨後可移除凸塊底層金屬層201的露出部分，例如藉由一乾式蝕刻製程。乾式蝕刻可使用化學藥劑例如CF4或CHF3。可使用任何現有的蝕刻技術或將來開發的蝕刻技術。蝕刻凸塊底層金屬層109之後，會露出第一鈍化保護層107的一部分。
一旦移除凸塊底層金屬層201的露出部分，凸塊底層金屬層201可具有一第四直徑d4，其可與接觸墊105之第一距離d1一同用於協助減少或消除形成於第一鈍化保護層107之內的裂縫。特別地，凸塊底層金屬層201及接觸墊105直徑之間的第二差值(在第4圖中以第五距離d5表示)可保持於特定範圍或比率內以協助防止裂縫形成於第一鈍化保護層107內。
例如，第5圖繪示了第一鈍化保護層107中發生裂縫的數目對不同的第五距離d5的關係。顯然地，在第五距離d5小於約8微米時，大量裂縫會形成於第一鈍化保護層107內。然而，當第五距離d5大於約5微米時，第一鈍化保護層107中的裂縫數目大幅減少，在約10微米或更大時其裂縫減少數目達至飽和。藉由減少裂縫數目，可改進半導體裝置100整體的可靠性，從而提高效能及良率。
在另一實施例中，除了單純改變第三距離d3(如 上述參照第1A~1B圖之說明)或單純改變第五距離d5(如上述參照第4~5圖之說明)，亦可同時改變第三距離d3及第五距離d5以產生更大效果。例如，在一實施例中，第三距離d3可保持大於10微米，而第五距離d5可保持大於約5微米。此外，第三距離d3與第五距離d5的總和(d3+d5)可保持大於約15微米。
第6A~6B圖繪示了結合改變第三距離d3與第五距離d5的比較結果。例如，在第6A圖中，該實施例之凸塊結構為45/0/0(類似於上述第1B圖)並接合至一犧牲層，其可包括錫、銀、及/或銅。當第三距離d3為24微米(第三距離d3的每一側邊為12微米)，第五距離d5為24微米(11.5微米/側邊)，其總和為47微米(23.5微米/側邊)時，第一鈍化保護層107中的裂縫數目可減少至低於20。
第6B圖以曲線圖形式繪示了第6A圖之表格的結果。由此可見，藉由控制第三距離d3及第五距離d5，可減少第一鈍化保護層107中的裂縫數目。
第6C圖以另一表格顯示了不同凸塊結構之結果，其中外部接點200具有35/0/15+錫銅系凸塊結構。例如，外部接點200可具有約35微米之銅層，約15微米之錫銀層位於銅層上。一錫銅合金頂蓋可用於錫銀層上，其可包括約98.2%的錫及約1.8%的銅。由此可見，藉由保持第三距離d3大於10微米(5微米/側邊)且第五距離d5大於5微米(2.5微米/側邊)，可將第一鈍化保護層107中的裂縫數目保持在一小的數目。然而，若不使用這些比率，例如使第三距離d3低於10微米(5微米/側邊)，例如9微米(4.5微米/側邊)，則第一鈍化保護層107中 可能發生的裂縫數目可能改變至更大的數目。
第7圖繪示了一旦第二頂蓋層303形成於第一頂蓋層301上且已移除凸塊底層金屬層201的露出部分，可實施回焊製程以轉換第二頂蓋層303為凸塊狀。在回焊製程中，將第二頂蓋層303升溫至約200℃至約260℃之間(例如約250℃)，保持約10秒至約60秒之間(例如約35秒)。此回焊處理可部分液化第二頂蓋層303，隨後藉由第二頂蓋層303的表面張力將其本身拉成所需之凸塊形狀。
藉由製作此處所述之接觸墊105、穿透第一鈍化保護層107的開口、及凸塊底層金屬層201，可減少或消除形成於第一鈍化保護層107中的裂縫數目。藉由減少第一鈍化保護層107中不希望的裂縫數目，可在半導體裝置100進一步處理及使用中維持第一鈍化保護層107所提供的保護。這樣的保護可提高製程整體效率並為每一個半導體裝置帶來更大的良率及改善。
在本發明一實施例中，提供一種半導體裝置，包括：一接觸墊，具有一第一直徑；以及一凸塊底層金屬層，電性連接至接觸墊，凸塊底層金屬層具有一第二直徑，其中第二直徑比第一直徑大上一第一距離，其為10微米。
在本發明另一實施例中，提供一種半導體裝置，包括：一接觸墊，位於一基板上，接觸墊包括一第一尺寸；一鈍化保護層，至少部分位於接觸墊上；一開口，穿透鈍化保護層，開口包括一第二尺寸；以及一凸塊底層金屬層，延伸通過開口而連接至接觸墊，凸塊底層金屬層包括一第三尺寸，其中 第三尺寸比第一尺寸大上一第一數值，其大於5微米。
在本發明又一實施例中，提供一種半導體裝置之製作方法，包括：於一基板上形成一接觸墊，接觸墊包括一第一直徑；於接觸墊上沉積一鈍化保護層；圖案化鈍化保護層，以形成穿透鈍化保護層的一開口，開口具有比該第一直徑小之一第二直徑；形成一凸塊底層金屬層延伸通過開口，凸塊底層金屬層具有一第三直徑，比第一直徑大上一第一距離，其大於5微米。
雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作更動、替代與潤飾。舉例來說，任何所屬技術領域中具有通常知識者可輕易理解此處所述的許多特徵、功能、製程及材料可在本發明的範圍內作更動。再者，本發明之保護範圍並未侷限於說明書內所述特定實施例中的製程、機器、製造、物質組成、裝置、方法及步驟，任何所屬技術領域中具有通常知識者可從本發明揭示內容中理解現行或未來所發展出的製程、機器、製造、物質組成、裝置、方法及步驟，只要可以在此處所述實施例中實施大體相同功能或獲得大體相同結果皆可使用於本發明中。因此，本發明之保護範圍包括上述製程、機器、製造、物質組成、裝置、方法及步驟。另外，每一申請專利範圍構成個別的實施例，且本發明之保護範圍也包括各個申請專利範圍及實施例的組合。
100‧‧‧半導體裝置
101‧‧‧半導體基板
102‧‧‧主動裝置
103‧‧‧金屬化層
105‧‧‧接觸墊
107‧‧‧第一鈍化保護層
201‧‧‧凸塊底層金屬層
203‧‧‧晶種層
207‧‧‧接點
301‧‧‧第一頂蓋層
303‧‧‧第二頂蓋層
d4‧‧‧第四直徑
d5‧‧‧第五距離

Claims (10)

  1. 一種半導體裝置，包括：一接觸墊，具有一第一直徑；以及一凸塊底層金屬層，電性連接至該接觸墊，該凸塊底層金屬層具有一第二直徑，其中該第二直徑比該第一直徑大上一第一距離，其為10微米。
  2. 如申請專利範圍第1項所述之半導體裝置，更包括至少部分位於該接觸墊與該凸塊底層金屬層之間的一第一鈍化保護層，其中該凸塊底層金屬層延伸通過該開口而連接至該接觸墊，該開口具有一第三直徑，其中該第三直徑比該第一直徑大上一第二距離，其為5微米。
  3. 如申請專利範圍第2項所述之半導體裝置，其中該第一距離及該第二距離的總和大於15微米。
  4. 如申請專利範圍第1項所述之半導體裝置，更包括一外部接點，形成於該凸塊底層金屬層上，其中該外部接點為一銅柱體，該接觸墊為鋁。
  5. 一種半導體裝置，包括：一接觸墊，位於一基板上，該接觸墊包括一第一尺寸；一鈍化保護層，至少部分位於該接觸墊上；一開口，穿透該鈍化保護層，該開口包括一第二尺寸；以及一凸塊底層金屬層，延伸通過該開口而連接至該接觸墊，該凸塊底層金屬層包括一第三尺寸，其中該第三尺寸比該第一尺寸大上一第一數值，其大於5微米。
  6. 如申請專利範圍第5項所述之半導體裝置，其中該第一尺寸比該第二尺寸大上一第二數值，其大於10微米，該第一數值及該第二數值的總和大於15微米。
  7. 一種半導體裝置之製作方法，包括：於一基板上形成一接觸墊，該接觸墊包括一第一直徑；於該接觸墊上沉積一鈍化保護層；圖案化該鈍化保護層，以形成穿透該鈍化保護層的一開口，該開口具有比該第一直徑小之一第二直徑；以及形成一凸塊底層金屬層延伸通過該開口，該凸塊底層金屬層具有一第三直徑，比該第一直徑大上一第一距離，其大於5微米。
  8. 如申請專利範圍第7項所述之半導體裝置之製作方法，其中該第一直徑比該第二直徑大上一第二距離，其大於10微米。
  9. 如申請專利範圍第8項所述之半導體裝置之製作方法，其中該第一距離及該第二距離的總和大於15微米。
  10. 如申請專利範圍第7項所述之半導體裝置之製作方法，其中該凸塊底層金屬化的形成更包括：毯覆式沈積一凸塊底層金屬層；於該凸塊底層金屬層上形成一外部接點；以及使用該外部接點作為罩幕，移除凸塊底層金屬層之部分。
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Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9024431B2 (en) 2009-10-29 2015-05-05 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor die contact structure and method
US9099318B2 (en) 2010-10-15 2015-08-04 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor chip having different pad width to UBM width ratios and method of manufacturing the same
US9190348B2 (en) 2012-05-30 2015-11-17 Taiwan Semiconductor Manufacturing Company, Ltd. Scheme for connector site spacing and resulting structures
US9472521B2 (en) 2012-05-30 2016-10-18 Taiwan Semiconductor Manufacturing Company, Ltd. Scheme for connector site spacing and resulting structures
US8802556B2 (en) * 2012-11-14 2014-08-12 Qualcomm Incorporated Barrier layer on bump and non-wettable coating on trace
CN104241148B (zh) * 2013-06-19 2017-08-25 中芯国际集成电路制造(上海)有限公司 一种在cpi测试中防止衬垫剥离的方法以及产生的器件
KR101683975B1 (ko) * 2014-08-05 2016-12-07 앰코 테크놀로지 코리아 주식회사 반도체 디바이스, 반도체 패키지, 반도체 디바이스 및 반도체 패키지의 제조 방법
DE102014111435B4 (de) * 2014-08-11 2024-09-26 Infineon Technologies Ag Chip-Anordnung
JP2016213238A (ja) * 2015-04-30 2016-12-15 ルネサスエレクトロニクス株式会社 半導体装置および半導体装置の製造方法
JP2017041566A (ja) * 2015-08-20 2017-02-23 セイコーエプソン株式会社 半導体装置及びその製造方法、電子機器並びに移動体
US9875979B2 (en) 2015-11-16 2018-01-23 Taiwan Semiconductor Manufacturing Company, Ltd. Conductive external connector structure and method of forming
DE102016117389B4 (de) 2015-11-20 2020-05-28 Semikron Elektronik Gmbh & Co. Kg Leistungshalbleiterchip und Verfahren zur Herstellung eines Leistungshalbleiterchips und Leistungshalbleitereinrichtung
CN106783756B (zh) * 2016-11-29 2019-06-04 武汉光迅科技股份有限公司 一种带金属凸点的陶瓷载片及其制作方法
US10453817B1 (en) 2018-06-18 2019-10-22 Texas Instruments Incorporated Zinc-cobalt barrier for interface in solder bond applications
US11908790B2 (en) * 2021-01-06 2024-02-20 Taiwan Semiconductor Manufacturing Company, Ltd. Chip structure with conductive via structure and method for forming the same

Family Cites Families (48)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3078646B2 (ja) 1992-05-29 2000-08-21 株式会社東芝 インジウムバンプの製造方法
JPH0997791A (ja) 1995-09-27 1997-04-08 Internatl Business Mach Corp <Ibm> バンプ構造、バンプの形成方法、実装接続体
JP3654485B2 (ja) * 1997-12-26 2005-06-02 富士通株式会社 半導体装置の製造方法
US6642136B1 (en) 2001-09-17 2003-11-04 Megic Corporation Method of making a low fabrication cost, high performance, high reliability chip scale package
US5943597A (en) 1998-06-15 1999-08-24 Motorola, Inc. Bumped semiconductor device having a trench for stress relief
JP4131595B2 (ja) 1999-02-05 2008-08-13 三洋電機株式会社 半導体装置の製造方法
JP2000243876A (ja) 1999-02-23 2000-09-08 Fujitsu Ltd 半導体装置とその製造方法
US6322903B1 (en) 1999-12-06 2001-11-27 Tru-Si Technologies, Inc. Package of integrated circuits and vertical integration
JP2001257226A (ja) 2000-03-10 2001-09-21 Hitachi Ltd 半導体集積回路装置
US6578754B1 (en) 2000-04-27 2003-06-17 Advanpack Solutions Pte. Ltd. Pillar connections for semiconductor chips and method of manufacture
US6592019B2 (en) 2000-04-27 2003-07-15 Advanpack Solutions Pte. Ltd Pillar connections for semiconductor chips and method of manufacture
JP3968554B2 (ja) 2000-05-01 2007-08-29 セイコーエプソン株式会社 バンプの形成方法及び半導体装置の製造方法
US6818545B2 (en) 2001-03-05 2004-11-16 Megic Corporation Low fabrication cost, fine pitch and high reliability solder bump
US6605524B1 (en) * 2001-09-10 2003-08-12 Taiwan Semiconductor Manufacturing Company Bumping process to increase bump height and to create a more robust bump structure
US6853076B2 (en) 2001-09-21 2005-02-08 Intel Corporation Copper-containing C4 ball-limiting metallurgy stack for enhanced reliability of packaged structures and method of making same
JP4571781B2 (ja) 2003-03-26 2010-10-27 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JP2005175128A (ja) 2003-12-10 2005-06-30 Fujitsu Ltd 半導体装置及びその製造方法
US6995411B2 (en) 2004-02-18 2006-02-07 Taiwan Semiconductor Manufacturing Co., Ltd. Image sensor with vertically integrated thin-film photodiode
JP4072523B2 (ja) 2004-07-15 2008-04-09 日本電気株式会社 半導体装置
US7452803B2 (en) 2004-08-12 2008-11-18 Megica Corporation Method for fabricating chip structure
US6977213B1 (en) 2004-08-27 2005-12-20 Taiwan Semiconductor Manufacturing Company, Ltd. IC chip solder bump structure and method of manufacturing same
US8294279B2 (en) 2005-01-25 2012-10-23 Megica Corporation Chip package with dam bar restricting flow of underfill
TW200638497A (en) 2005-04-19 2006-11-01 Elan Microelectronics Corp Bumping process and bump structure
TWI330863B (en) 2005-05-18 2010-09-21 Megica Corp Semiconductor chip with coil element over passivation layer
US7391112B2 (en) 2005-06-01 2008-06-24 Intel Corporation Capping copper bumps
CN1901162B (zh) 2005-07-22 2011-04-20 米辑电子股份有限公司 连续电镀制作线路组件的方法及线路组件结构
US7397121B2 (en) 2005-10-28 2008-07-08 Megica Corporation Semiconductor chip with post-passivation scheme formed over passivation layer
US8836146B2 (en) 2006-03-02 2014-09-16 Qualcomm Incorporated Chip package and method for fabricating the same
JP2007258438A (ja) 2006-03-23 2007-10-04 Fujitsu Ltd 半導体装置及びその製造方法
JP2007273624A (ja) 2006-03-30 2007-10-18 Fujitsu Ltd 半導体装置及びその製造方法
US8022552B2 (en) 2006-06-27 2011-09-20 Megica Corporation Integrated circuit and method for fabricating the same
JP2008016514A (ja) 2006-07-03 2008-01-24 Renesas Technology Corp 半導体装置の製造方法および半導体装置
US7973418B2 (en) 2007-04-23 2011-07-05 Flipchip International, Llc Solder bump interconnect for improved mechanical and thermo-mechanical performance
JP4953132B2 (ja) 2007-09-13 2012-06-13 日本電気株式会社 半導体装置
US8178980B2 (en) 2008-02-05 2012-05-15 Taiwan Semiconductor Manufacturing Company, Ltd. Bond pad structure
JP2009188288A (ja) 2008-02-08 2009-08-20 Seiko Epson Corp 半導体装置およびその製造方法
JP5335313B2 (ja) 2008-08-05 2013-11-06 キヤノン株式会社 Ｘ線画像撮影装置、ｘ線画像撮影システム、ｘ線撮影制御装置、制御方法及びプログラム
US20100044860A1 (en) 2008-08-21 2010-02-25 Tessera Interconnect Materials, Inc. Microelectronic substrate or element having conductive pads and metal posts joined thereto using bond layer
US9859235B2 (en) * 2009-01-26 2018-01-02 Taiwan Semiconductor Manufacturing Company, Ltd. Underbump metallization structure
US8159070B2 (en) 2009-03-31 2012-04-17 Megica Corporation Chip packages
US8039304B2 (en) 2009-08-12 2011-10-18 Stats Chippac, Ltd. Semiconductor device and method of dual-molding die formed on opposite sides of build-up interconnect structures
US8299632B2 (en) * 2009-10-23 2012-10-30 Ati Technologies Ulc Routing layer for mitigating stress in a semiconductor die
US8227926B2 (en) 2009-10-23 2012-07-24 Ati Technologies Ulc Routing layer for mitigating stress in a semiconductor die
US9024431B2 (en) 2009-10-29 2015-05-05 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor die contact structure and method
US20110121438A1 (en) * 2009-11-23 2011-05-26 Xilinx, Inc. Extended under-bump metal layer for blocking alpha particles in a semiconductor device
US8293636B2 (en) * 2010-08-24 2012-10-23 GlobalFoundries, Inc. Conductive connection structure with stress reduction arrangement for a semiconductor device, and related fabrication method
US9472521B2 (en) 2012-05-30 2016-10-18 Taiwan Semiconductor Manufacturing Company, Ltd. Scheme for connector site spacing and resulting structures
US9190348B2 (en) 2012-05-30 2015-11-17 Taiwan Semiconductor Manufacturing Company, Ltd. Scheme for connector site spacing and resulting structures

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