TW201342578A - 低起始電壓互補式金氧半導體元件 - Google Patents

低起始電壓互補式金氧半導體元件 Download PDF

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TW201342578A
TW201342578A TW101145117A TW101145117A TW201342578A TW 201342578 A TW201342578 A TW 201342578A TW 101145117 A TW101145117 A TW 101145117A TW 101145117 A TW101145117 A TW 101145117A TW 201342578 A TW201342578 A TW 201342578A
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work function
layer
region
aluminum
dielectric constant
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Takashi Ando
Chang-Hwan Choi
Ki-Sik Choi
Vijay Narayanan
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Globalfoundries Us Inc
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Abstract

本發明揭示一種半導體元件，其包含：一NMOS區域與一PMOS區域；該NMOS區域具有一閘極結構，該閘極結構包含一第一高介電常數閘極介電質、一第一功函數設定金屬以及一閘極電極填充材料；該PMOS區域具有一閘極結構，該閘極結構包含一第二高介電常數閘極介電質、一第二功函數設定金屬以及一閘極電極填充材料；其中該第一高介電常數閘極介電質異於該第二高介電常數閘極介電質，且該第一功函數設定金屬異於該第二功函數設定金屬。本發明亦揭示該半導體元件的製造方法，其包含後閘極(gate last)製程。

Description

低起始電壓互補式金氧半導體元件
例示性具體實施例有關半導體元件，尤其有關具有雙閘極介電質及雙金屬閘極結構的互補式金氧半導體(CMOS)元件及其製造方法。
半導體元件用於各種電子應用中，舉例而言，諸如個人電腦、行動電話、數位相機、及其他電子設備。通常藉由在半導體基板上相繼沉積絕緣(或介電質)層、導電層、及半導體材料層並使用微影圖案化不同層以在半導體基板上形成電路組件及部件來製造半導體元件。
電晶體是在半導體元件中大量使用的部件。例如，單一積體電路(IC)上有數以百萬計的電晶體。半導體元件製造中常用的電晶體類型係金氧半導體場效電晶體(MOSFET)。
早期的MOSFET製程使用一個摻雜類型產生正通道電晶體或負通道電晶體。比較新近的設計稱為互補式MOS(CMOS)元件，其以互補式配置使用正通道元件及負通道元件，如，正通道金氧半導體(PMOS)電晶體及負通道金氧半導體(NMOS)電晶體。PMOS電晶體又可稱為PMOSFET或PFET，而NMOS電晶體又可稱為NMOSFET或NFET。NMOS元件負充電致使電晶體因電子的移動而開啟或關閉，而PMOS元件則涉及電子空位的移動。儘管製造CMOS元件需要使用更多製造步驟及更多電晶體，但CMOS元件仍是有利的，因為其利用較少電力，且元件可越做越小及速度越快。
雙功函數閘極有利於使用在具有PMOS電晶體及NMOS電晶體的半導體元件中。需要實現PMOS電晶體及NMOS電晶體之最佳操作的一些功函數。金屬閘極電極的最佳功函數將取決於其用以形成NMOS電晶體或PMOS電晶體而有所不同。因此之故，在使用相同材料製作NMOS電晶體及PMOS電晶體的金屬閘極電極時，閘極電極無法顯現兩個元件類型所要的功函數。可藉由分別以第一材料形成NMOS電晶體的金屬閘極電極及以第二材料形成PMOS電晶體的金屬閘極電極來解決這個問題。第一材料可確保NMOS閘極電極的理想功函數，而第二材料則可確保PMOS閘極電極的理想功函數。
根據例示性具體實施例的第一方面，藉由提供一種半導體元件達成上文及下文說明之例示性具體實施例的各種優點及目的。該半導體元件包含：一NMOS區域與一PMOS區域；該NMOS區域具有一閘極結構，該閘極結構包含一第一高介電常數閘極介電質、一第一功函數設定金屬以及一閘極電極填充材料；該PMOS區域具有一閘極結構，該閘極結構包含一第二高介電常數閘極介電質、一第二功函數設定金屬以及一閘極電極填充材料；其中該第一高介電常數閘極介電質異於該第二高介電常數閘極介電質，且該第一功函數設定金屬異於該第二功函數設定金屬。
根據例示性具體實施例的第二方面，提供一種半導體元件的製造方法。該方法包含：提供一基板，該基板具有一NMOS區域與一PMOS區域；於該NMOS區域與該PMOS區域上方形成一高介電常數層；於該NMOS區域與該PMOS區域之至少一個上方，將一金屬加入該高介電常數層，其中，若是加入至該NMOS區域上方之該高介電常數層則該金屬是鑭，且若是加入至該PMOS區域上方之該高介電常數層則該金屬是鋁；於該NMOS區域與該PMOS區域上方沉積一氮化物層或碳化物層；於該氮化物層上方沉積一矽層；於該NMOS區域與該PMOS區域上方將該 氮化物層與該矽層之一閘極結構圖案化；於該NMOS區域上方之該閘極結構與該PMOS區域上方之該閘極結構之間形成一層間介電質；從該NMOS區域上方之該閘極結構與該PMOS區域上方之該閘極結構移除該矽層，以在該些閘極結構留下一開口；於該NMOS區域上方之該開口內沉積一第一功函數設定金屬，且於該PMOS區域上方之該開口內沉積一第二功函數設定金屬，以部分地填充該些開口；以及沉積一填充金屬以部分地填充該些開口。
根據例示性具體實施例的第三方面，提供一種半導體元件的製造方法。該方法包含：提供一基板，該基板具有一NMOS區域與一PMOS區域；於該NMOS區域與該PMOS區域上皆形成一閘極結構；於該NMOS區域上方之該閘極結構與該PMOS區域上方之該閘極結構之間形成一層間介電質；移除該NMOS區域上方之該閘極結構與該PMOS區域上方之該閘極結構，以在該層間介電質內該NMOS區域與該PMOS區域的上方皆留下一開口；沉積至少下列之一：位於該NMOS區域上方之該開口內的鑭氧化物、位於該PMOS區域上方之該開口內的鋁氧化物；於該NMOS區域與該PMOS區域上方之每一個開口內沉積一高介電常數介電質；於該NMOS區域上方之該開口內沉積一第一功函數設定金屬，且於該PMOS區域上方之該開口內沉積一第二功函數設定金屬，以部分地填充該些開口；以及沉積一填充金屬以部分地填充該些開口。
100‧‧‧半導體結構
102‧‧‧半導體基板
104‧‧‧NMOS區域
106‧‧‧PMOS區域
108‧‧‧淺溝渠隔離(STI)區域
110‧‧‧可選矽鍺層
112‧‧‧高介電常數(k)材料
114‧‧‧多層結構
116‧‧‧含鋁層
118‧‧‧含鑭層
120‧‧‧矽層
122‧‧‧富含鋁的高介電常數層部分
124‧‧‧富含鑭的高介電常數層部分
126‧‧‧氮化物或碳化物層
128‧‧‧非晶矽層
130‧‧‧閘極結構
132‧‧‧閘極結構
134‧‧‧間隔物
136‧‧‧層間介電質
138‧‧‧開口
140‧‧‧開口
142‧‧‧功函數設定金屬層
144‧‧‧填充金屬
200‧‧‧半導體結構
202‧‧‧半導體基板
204‧‧‧NMOS區域
206‧‧‧PMOS區域
208‧‧‧淺溝渠隔離(STI)區域
210‧‧‧可選矽鍺層
212‧‧‧虛擬閘極結構
213‧‧‧虛擬氧化物
214‧‧‧絕緣間隔物
216‧‧‧層間介電質
218‧‧‧開口
220‧‧‧開口
222‧‧‧帽蓋層
224‧‧‧帽蓋層
226‧‧‧高介電常數層
228‧‧‧功函數設定金屬層
230‧‧‧功函數設定金屬層
232‧‧‧填充金屬層
240‧‧‧界面層
特別在隨附申請專利範圍中提出據信為新穎之例示性具體實施例的特徵及例示性具體實施例的元件特性。圖式僅用於解說的目的，因而未按比例繪製。結合附圖參考以下詳細說明，可深入瞭解有關組織及操作方法的例示性具體實施例，其中：圖1A至1K為圖解形成第一例示性具體實施例之半導體元件的橫截面，其中：圖1A圖解具有NMOS區域及PMOS區域的起始基 板；圖1B圖解沉積高介電常數層；圖1C圖解改質高介電常數層之組成物的若干沉積層；圖1D圖解具有改質高介電常數層的起始基板；圖1E圖解於起始基板上沉積氮化物層及矽層；圖1F圖解以氮化物層及矽層形成虛擬閘極；圖1G圖解在虛擬閘極周圍形成間隔物及層間介電質層；圖1H圖解移除矽虛擬閘極；圖1I圖解沉積功函數設定金屬；圖1J圖解於功函數設定金屬上方沉積填充金屬；及圖1K圖解平坦化半導體結構。
圖2A至2G為圖解形成第二例示性具體實施例之半導體元件的橫截面，其中：圖2A圖解具有NMOS區域及PMOS區域的起始基板；圖2B圖解形成虛擬閘極；圖2C圖解在虛擬閘極周圍形成間隔物及層間介電質層；圖2D圖解移除虛擬閘極；圖2E圖解沉積帽蓋層及高介電常數層；圖2F圖解沉積功函數設定金屬及填充金屬；及圖2G圖解平坦化半導體結構。
圖3圖解製造第一例示性具體實施例的製程流程。
圖4圖解製造第二例示性具體實施例的製程流程。
可利用「先閘極(gate first)」製程或「後閘極」製程製作CMOS元件。在先閘極製程中，形成及圖案化在NMOS區域 及PMOS區域上方的金屬層以形成閘極結構，接著再進行典型CMOS處理，諸如形成源極及汲極、形成間隔物及沉積層間介電質。在後閘極製程中，形成虛擬閘極結構，接著再進行典型CMOS處理，包含形成源極及汲極、形成間隔物及沉積層間介電質。之後，移除虛擬閘極結構，接著再沉積取代閘極結構。
CMOS元件需要低起始電壓。然而，在先閘極製程下，很難達成PMOS元件的低起始電壓。後閘極製程有利於PMOS元件的起始電壓，但要獲得對應於矽價帶邊緣的有效功函數卻非易事。
本發明人提出半導體元件及其製造方法，其中利用後閘極製程以雙閘極介電質及雙金屬閘極結構形成NMOS元件及PMOS元件。
詳細參考圖式，尤其參考圖1A至1K，其中圖解採用後閘極製程的第一例示性具體實施例。形成半導體結構100，其包含半導體基板102、NMOS區域104及PMOS區域106，如圖1A中圖解。雖對本發明並不重要，但可視半導體設計需要而植入NMOS區域104及PMOS區域106的通道區域。
組成半導體基板102的半導體材料可以是任何半導體材料，包含但不限於：矽、矽鍺、鍺、III-V化合物半導體、或II-VI化合物半導體。例示性具體實施例可應用於絕緣體上矽(SOI)技術及塊體半導體技術。
隔開NMOS區域104及PMOS區域106的可以是淺溝渠隔離(STI)區域108。
半導體結構100在PMOS區域106中亦可包含可選矽鍺層110。可選矽鍺層110後來在處理中可稱為「通道矽鍺」。
現在參考圖1B，照慣例沉積一層高介電常數材料112。以下可將高介電常數(k)材料112稱為「高k材料」。高介電常數材料的一些實例包含但不限於：HfO2、HfON、ZrO2、ZrON、HfSiOx、HfSiON、HfZrO、HfZrON。本發明人偏好使用HfO2作 為高k材料。可將高k材料沉積至約10至30埃的厚度。
在一例示性具體實施例中，可將一或多個所要金屬驅入上覆NMOS區域104及PMOS區域106的高k材料112中。現在參考圖1C，其中顯示多層結構114，其包含含鋁層116、含鑭層118及矽層120。含鋁層116可為約1至10埃厚並可含有鋁、鋁氧化物或鋁及鈦氮化物的混合物。含鑭層118可為約1至10埃厚並可含有鑭、鑭氧化物或鑭及鈦氮化物的混合物。包含多層結構114的半導體結構100可在900-1100℃下退火達5秒，以將鋁驅入在PMOS區域106上方的高介電常數層110中，及將鑭驅入在NMOS區域104上方的高介電常數層110中。矽層120密封多層結構114，以免該多層結構在退火步驟期間氧化。結果是將高介電常數層112改質成兩個部分，因而有富含鋁的高介電常數層部分122及富含鑭的高介電常數層部分124，如圖1D中圖解。
應明白，此處的原則在於具有雙高介電常數層。儘管最佳具體實施例是要具有富含鋁的部分122及富含鑭的部分124，但僅有富含鋁的部分122及富含鑭的部分124之一者亦可達成本發明的優點，只要高介電常數層的另一部分是原來沉積的高介電常數層112。在此後一例示性具體實施例中，將不需要含鋁層116及含鑭層118中的一個。
在如上文所說明的退火後，照慣例藉由蝕刻移除矽層120、含鑭層118及含鋁層116以形成圖1D中顯示的結構。
現在參考圖1E，照慣例沉積10至30埃的鈦氮化物、或鉭氮化物、鈦碳化物或鉭碳化物以形成氮化物或碳化物層126，接著再沉積約60奈米的非晶矽以形成非晶矽層128。
之後，如圖1F所示，圖案化鈦氮化物層126及非晶矽層128以在NMOS區域104上方形成閘極結構130及在PMOS區域106上方形成閘極結構132。
可照慣例將間隔物134(諸如氮化物間隔物)添加至閘極結構130、132，接著再照慣例沉積層間介電質136。至此的半 導體結構100如圖1G中圖解。
源極及汲極活化可在NMOS區域104及PMOS區域106中發生。在源極及汲極活化期間，非晶矽層128轉化成多晶矽。閘極結構130、132內的多晶矽是虛擬閘極且根據此例示性具體實施例必須在後閘極製程中移除並為取代閘極所取代。多晶矽(之前為非晶矽層128)可利用濕蝕刻化學劑(諸如氫氧化四甲銨(TMAH)、氫氧化四乙銨(TEAH)、或氫氧化銨(NH4OH))或反應性離子蝕刻製程移除，致使在閘極結構130中形成開口138及在閘極結構132中形成開口140，如圖1H所示。
然後在開口138、140內沉積大體上以142指示的功函數設定金屬層。為清楚之故，未顯示構成功函數金屬的個別層，如下文說明。開口138中的功函數設定金屬設定在矽導電帶邊緣周圍的功函數，開口140中的功函數金屬則設定在矽價帶邊緣周圍的功函數。在開口138內，沉積10至30埃的鉭氮化物後，接著再沉積10至40埃的鈦鋁。或者，可在開口138內沉積鈦鋁氮化物、鉭鋁、鉭鋁氮化物、鉿矽合金、鉿氮化物、或鉭碳化物而非鈦鋁。在開口140內，沉積10至30埃的鉭氮化物後，接著再沉積30至70埃的鈦氮化物及10至40埃的鈦鋁。或者，可在開口140內沉積鎢、鉭氮化物、釕、鉑、錸、銥、或鈀而非鈦氮化物，及可在開口140內沉積鈦鋁氮化物、鉭鋁、鉭鋁氮化物、鉿矽合金、鉿氮化物、或鉭碳化物而非鈦鋁。功函數金屬可等形地沉積(如圖1I所示)，或可非等形地沉積。
現在參考圖1J，用填充金屬144(諸如鋁、摻雜鈦的鋁、鎢、或銅)填充剩餘的開口138、140。
然後，利用諸如化學機械拋光的製程平坦化半導體結構100，圖1K。
接著可進行其他生產線中間及生產線後段的半導體處理。
在圖3中圖解第一例示性具體實施例的製程流程。製 程流程始於提供基板，其具有NMOS區域及PMOS區域，方塊302。
在NMOS區域及PMOS區域上方形成高k介電質，方塊304。
接著，可將鑭加入在NMOS區域上方的高k介電質、或將鋁加入在PMOS區域上方的高k介電質、或既將鑭加入在NMOS區域上方的高k介電質且將鋁加入在PMOS區域上方的高k介電質，方塊306。
在NMOS區域及PMOS區域上方沉積一層鈦氮化物，方塊308，接著在氮化物層上方沉積矽，方塊310。
將氮化物及矽層圖案化以形成虛擬閘極，方塊312。
視需要，可接著於虛擬閘極形成間隔物，接著再沉積氧化物層間介電質，方塊314。
利用合適的蝕刻製程，從NMOS區域及PMOS區域上方的虛擬閘極移除矽，方塊316。
開始取代閘極製程，其中沉積功函數設定金屬以部分地填充因移除矽所留下的開放區域，方塊318；接著再沉積填充金屬以填充剩餘的開放區域並完成取代閘極製程，方塊320。
在圖2A至2G中圖解採用後閘極製程的第二例示性具體實施例。此例示性具體實施例如圖2A所示的起始結構實質上類似於圖1A顯示的結構。即，形成半導體結構200，其包含半導體基板202、NMOS區域204及PMOS區域206。
組成半導體基板202的半導體材料可以是任何半導體材料，包含但不限於：矽、矽鍺、鍺、III-V化合物半導體、或II-VI化合物半導體。本發明可應用於絕緣體上矽(SOI)技術及塊體半導體技術。
隔開NMOS區域204及PMOS區域206的可以是淺溝渠隔離(STI)區域208。
半導體結構200在PMOS區域206中亦可包含可選矽鍺層210。可選矽鍺層210後來在處理中可稱為「通道矽鍺」。
現在參考圖2B，顯示虛擬閘極結構212，其將在後續製程中移除。虛擬閘極結構212已從虛擬氧化物213及60 nm厚的非晶矽層或多晶矽層(已照慣例全區覆蓋式沉積及接著圖案化)形成。虛擬氧化物可為利用原子層沉積(ALD)或在氧環境下退火(快速熱退火、熔爐退火)所生長的矽氧化物。虛擬氧化物可利用快速熱退火或電漿氮化進行氮化。
如圖2C顯示，已將絕緣間隔物214(諸如氮化物間隔物)添加至虛擬閘極結構212，及接著已將層間介電質216(諸如氧化物)全區式覆蓋沉積並接著藉由停止於虛擬閘極結構212上進行平坦化。
利用濕蝕刻化學劑(諸如氫氧化四甲銨(TMAH)、氫氧化四乙銨(TEAH)、或氫氧化銨(NH4OH))、或利用反應性離子蝕刻製程移除虛擬閘極結構212，接著再使用濕蝕刻化學劑(諸如稀釋氫氟酸(DHF)或緩衝氫氟酸(BHF))移除虛擬氧化物，以在半導體結構200中，在NMOS區域204上方形成開口218及在PMOS區域206上方形成開口220，如圖2D圖解。照慣例藉由例如氧化NMOS區域204及PMOS區域206中的矽，在開口218、220的底部生長矽氧化物的界面層240。
之後，可在開口218或開口220中添加帽蓋層，或在開口218及開口220中皆添加帽蓋層。開口218中的帽蓋層222可為1至10埃厚的鑭氧化物層，開口220中的帽蓋層224則可為1至10埃厚的鋁氧化物層。儘管在圖2E中將帽蓋層222及帽蓋層224顯示為較佳具體實施例，但應明白，可在僅使用帽蓋層222、224中的一個時達成本發明的優點，因為本發明的優點在於具有雙閘極介電質，而這可藉由僅使用帽蓋層222、224中的一個來達成。
帽蓋層222可藉由以下方式形成：在各處沉積帽蓋層222、擋住NMOS區域204及接著利用合適的蝕刻製程(諸如稀釋鹽酸(HCl))從PMOS區域206移除帽蓋層222。同樣地，帽蓋層224 可藉由以下方式形成：在各處全區式覆蓋沉積帽蓋層224、擋住PMOS區域206及接著利用合適的蝕刻製程(諸如稀釋氫氧化銨(NH4OH))從NMOS區域204移除帽蓋層224。沉積帽蓋層222、224的順序並不重要，因此可首先沉積及圖案化帽蓋層224，接著再沉積及圖案化帽蓋層222。
接下來，沉積高k介電質，諸如第一例示性具體實施例中提到的高k介電質。為了圖解而非限制，高介電常數層226是10至30埃厚的鉿氧化物層。高介電常數層226在帽蓋層上方形成，如圖2E所示。
可等形或非等形地形成帽蓋層222、224及高k介電質226。如圖2E顯示，已等形地沉積這些層。
功函數設定金屬層228、230分別必須沉積在開口218及220中。為清楚之故，並未顯示構成功函數設定金屬層228、230的個別功函數金屬，如下文說明。開口218中的功函數設定金屬設定在矽導電帶邊緣周圍的功函數，開口220中的功函數金屬則設定在矽價帶邊緣周圍的功函數。在NMOS區域204上方的開口218中，沉積10至30埃厚之鈦氮化物及10至30埃厚之鉭氮化物的可選層，接著再沉積10至40埃厚之鈦鋁的非可選層，這些層一起組成大體上以228指示的功函數設定金屬層。或者，可在開口218內沉積鈦鋁氮化物、鉭鋁、鉭鋁氮化物、鉿矽合金、鉿氮化物、或鉭碳化物而非鈦鋁。在PMOS區域206上方的開口220中，沉積10至30埃厚之鈦氮化物及10至30埃厚之鉭氮化物的可選層，接著再沉積30至70埃厚之鈦氮化物及10至40埃厚之鈦鋁層的非可選層，這些層一起組成大體上以230指示的功函數設定金屬層。或者，可在開口220內沉積鎢、鉭氮化物、釕、鉑、錸、銥、或鈀而非鈦氮化物，及可在開口220內沉積鈦鋁氮化物、鉭鋁、鉭鋁氮化物、鉿矽合金、鉿氮化物、或鉭碳化物而非鈦鋁。
功函數設定金屬層228、230可沉積如下：在各處沉 積可選的鈦氮化物層、在各處沉積可選的鉭氮化物層、在各處沉積鈦氮化物層、從NMOS區域204移除最後的鈦氮化物層、及在各處沉積鈦鋁。
用填充金屬(諸如鋁、摻雜鈦的鋁、鎢或銅(層232))填充剩餘的開口218、220以形成圖2F顯示的結構。
利用習知化學機械拋光製程移除填充金屬層232、功函數設定金屬228、230及任何高介電常數層226及帽蓋層222、224的覆蓋層以形成圖2G顯示的結構。
可接著進行其他生產線中間及生產線後段的半導體處理。
在圖4中圖解第二例示性具體實施例的製程流程。製程流程始於提供基板，其具有NMOS區域及PMOS區域，方塊402。
然後形成虛擬閘極結構，方塊404。
視需要，可接著於虛擬閘極形成間隔物，接著再沉積氧化物層間介電質，方塊406。
利用合適的蝕刻製程移除虛擬閘極結構以在虛擬閘極結構原本所在之處留下開放區域，方塊408。
用取代閘極填充因移除虛擬閘極結構而留下的開放區域。取代閘極製程始於在NMOS區域上方的開放區域中沉積鑭氧化物、或在PMOS區域上方的開放區域中沉積鋁氧化物、或既在NMOS區域上方的開放區域中沉積鑭氧化物且在PMOS區域上方的開放區域中沉積鋁氧化物，方塊410。
然後在開放區域中及在鑭氧化物(若存在)及鋁氧化物(若存在)上方沉積高k介電質，方塊412。
然後，沉積功函數設定金屬以部分地填充開放區域，方塊414，接著再沉積填充金屬以填充剩餘的開放區域並完成取代閘極製程，方塊416。
將半導體結構100、200顯示為已平坦化。將例示性具體實施 例應用於非平坦的FinFET結構亦在本例示性具體實施例的範疇內。金屬必須能夠被等形地形成。代替用鈦鋁填充開口，取而代之等形地形成含鋁等形金屬，諸如鈦鋁氮化物或鉭鋁氮化物。
關注本揭示內容的熟習本技術者應明白，可在不脫離本發明的精神下，對例示性具體實施例做出超出本文明確描述之這些具體實施例的其他修改。因此，此類修改被視為在僅由隨附申請專利範圍所定的本發明範疇內。
100‧‧‧半導體結構
102‧‧‧半導體基板
104‧‧‧NMOS區域
106‧‧‧PMOS區域
122‧‧‧富含鋁的高介電常數層部分
124‧‧‧富含鑭的高介電常數層部分
126‧‧‧氮化物或碳化物層
134‧‧‧間隔物
136‧‧‧層間介電質
142‧‧‧功函數設定金屬層
144‧‧‧填充金屬

Claims (23)

  1. 一種半導體元件，包含：一NMOS區域與一PMOS區域；該NMOS區域具有一閘極結構，該閘極結構包含一第一高介電常數閘極介電質、一第一功函數設定金屬以及一閘極電極填充材料；該PMOS區域具有一閘極結構，該閘極結構包含一第二高介電常數閘極介電質、一第二功函數設定金屬以及一閘極電極填充材料；其中該第一高介電常數閘極介電質異於該第二高介電常數閘極介電質，且該第一功函數設定金屬異於該第二功函數設定金屬。
  2. 如申請專利範圍第1項所述之半導體元件，其中該第一高介電常數閘極介電質包含鑭。
  3. 如申請專利範圍第2項所述之半導體元件，其中該第一高介電常數閘極介電質與鑭分別位於上、下層。
  4. 如申請專利範圍第1項所述之半導體元件，其中該第二高介電常數閘極介電質包含鋁。
  5. 如申請專利範圍第4項所述之半導體元件，其中該第二高介電常數閘極介電質與鋁分別位於上、下層。
  6. 如申請專利範圍第1項所述之半導體元件，其中該第一高介電常數閘極介電質包含鑭，且其中該第二高介電常數閘極介電質包含鋁。
  7. 如申請專利範圍第1項所述之半導體元件，其中該第一功函數設定金屬包含鋁、鈦鋁、鈦鋁氮化物、鉭鋁、鉭鋁氮化物、鉿矽合金、鉿氮化物、或鉭碳化物，且該第二功函數設定金屬包含鈦氮化物、鎢、鉭氮化物、釕、鉑、錸、銥、或鈀。
  8. 如申請專利範圍第1項所述之半導體元件，其中該第一功函數設定金屬在矽導帶邊緣設定功函數，且該第二功函數設定金屬在矽價帶邊緣設定功函數。
  9. 如申請專利範圍第1項所述之半導體元件，其中該PMOS區域更包含一矽鍺層，該矽鍺層位於該第二高介電常數閘極介電質下方。
  10. 一種製造半導體元件的方法，包含：提供一基板，該基板具有一NMOS區域與一PMOS區域；於該NMOS區域與該PMOS區域上方形成一高介電常數層；於該NMOS區域與該PMOS區域之至少一個上方，將一金屬加入該高介電常數層，其中，若是加入至該NMOS區域上方之該高介電常數層則該金屬是鑭，且若是加入至該PMOS區域上方之該高介電常數層則該金屬是鋁；於該NMOS區域與該PMOS區域上方沉積一氮化物層或碳化物層；於該氮化物層上方沉積一矽層；於該NMOS區域與該PMOS區域上方將該氮化物層與該矽層之一閘極結構圖案化；於該NMOS區域上方之該閘極結構與該PMOS區域上方之該閘極結構之間形成一層間介電質；從該NMOS區域上方之該閘極結構與該PMOS區域上方之該閘極結構移除該矽層，以在該些閘極結構留下一開口；於該NMOS區域上方之該開口內沉積一第一功函數設定金屬，且於該PMOS區域上方之該開口內沉積一第二功函數設定金屬，以部分地填充該些開口；以及沉積一填充金屬以部分地填充該些開口。
  11. 如申請專利範圍第10項所述之方法，其中該NMOS區域上方之該高介電常數閘極介電層包含鑭。
  12. 如申請專利範圍第10項所述之方法，其中該PMOS區域上方之該高介電常數閘極介電層包含鋁。
  13. 如申請專利範圍第10項所述之方法，其中該NMOS區域上方之該高介電常數閘極介電層包含鑭，且其中該PMOS區域上方之該高介電常數閘極介電層包含鋁。
  14. 如申請專利範圍第10項所述之方法，其中該第一功函數設定金屬包含鋁或鈦鋁，且該第二功函數設定金屬包含鈦氮化物。
  15. 如申請專利範圍第10項所述之方法，其中該第一功函數設定金屬在矽導帶邊緣設定功函數，且該第二功函數設定金屬在矽價帶邊緣設定功函數。
  16. 如申請專利範圍第10項所述之方法，其中該PMOS區域更包含一矽鍺層，該矽鍺層位於該高介電常數閘極介電層下方。
  17. 一種製造半導體元件的方法，包含：提供一基板，該基板具有一NMOS區域與一PMOS區域；於該NMOS區域與該PMOS區域上皆形成一閘極結構；於該NMOS區域上方之該閘極結構與該PMOS區域上方之該閘極結構之間形成一層間介電質；移除該NMOS區域上方之該閘極結構與該PMOS區域上方之該閘極結構，以在該層間介電質內該NMOS區域與該PMOS區域的上方皆留下一開口；沉積至少下列之一：位於該NMOS區域上方之該開口內的鑭氧化物、位於該PMOS區域上方之該開口內的鋁氧化物；於該NMOS區域與該PMOS區域上方之每一個開口內沉積一高介電常數介電質； 於該NMOS區域上方之該開口內沉積一第一功函數設定金屬，且於該PMOS區域上方之該開口內沉積一第二功函數設定金屬，以部分地填充該些開口；以及沉積一填充金屬以部分地填充該些開口。
  18. 如申請專利範圍第17項所述之方法，其中鑭沉積於該NMOS區域上方之該開口內。
  19. 如申請專利範圍第17項所述之方法，其中鋁沉積於該PMOS區域上方之該開口內。
  20. 如申請專利範圍第17項所述之方法，其中鑭沉積於該NMOS區域上方之該開口內，且其中該鋁沉積於該PMOS區域上方之該開口內。
  21. 如申請專利範圍第17項所述之方法，其中該第一功函數設定金屬包含鋁、鈦鋁、鈦鋁氮化物、鉭鋁、鉭鋁氮化物、鉿矽合金、鉿氮化物、或鉭碳化物，且該第二功函數設定金屬包含鈦氮化物、鎢、鉭氮化物、釕、鉑、錸、銥、或鈀。
  22. 如申請專利範圍第17項所述之方法，其中該第一功函數設定金屬在矽導帶邊緣設定功函數，且該第二功函數設定金屬在矽價帶邊緣設定功函數。
  23. 如申請專利範圍第17項所述之方法，其中該PMOS區域更包含一矽鍺層。
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