TW201320299A - 三維積體電路的組裝方法 - Google Patents

三維積體電路的組裝方法 Download PDF

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TW201320299A
TW201320299A TW101103480A TW101103480A TW201320299A TW 201320299 A TW201320299 A TW 201320299A TW 101103480 A TW101103480 A TW 101103480A TW 101103480 A TW101103480 A TW 101103480A TW 201320299 A TW201320299 A TW 201320299A
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interposer
bumps
wafer
semiconductor die
carrier wafer
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TWI474467B (zh
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Chih-Wei Wu
Szu-Wei Lu
Jing-Cheng Lin
Shin-Puu Jeng
Chen-Hua Yu
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Taiwan Semiconductor Mfg
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Abstract

本發明一實施例提供一種三維積體電路的組裝方法，包括：提供一承載晶圓，承載晶圓具有多個凹槽形成於承載晶圓中；提供一中介板，中介板包括：多個第一凸塊，配置於中介板的一第一側上；以及多個第二凸塊，配置於中介板的一第二側上，其中各第一凸塊與各第二凸塊為圓形；將中介板貼附至承載晶圓，且配置第一凸塊以使各第一凸塊位於承載晶圓中的一對應凹槽中；將一半導體晶粒貼附至中介板的第二側上以形成一晶圓堆疊；以及將晶圓堆疊貼附至一基板。

Description

三維積體電路的組裝方法
本發明有關於積體電路，且特別是有關於三維積體電路的組裝方法。
由於各種電子元件(例如，電晶體、二極體、電阻元件、電容元件等)之積集度的增加，半導體工業已經歷快速的成長。積集度大部分之增進是因為半導體製程節點之縮小化(例如，製程節點朝次20奈米節點縮小)。隨著近來對於縮小化、更高速度、更高頻寬、及更低能量損耗與延遲之需求的成長，已有對於更小及更具創造性之半導體晶粒封裝技術的需求形成。
隨著半導體技術之發展，多晶片晶圓級封裝之半導體元件已成為有效率的替代方案之一，以進一步縮減半導體晶片之物理尺寸。在晶圓級封裝之半導體元件中，主動電路(例如是邏輯、記憶體、處理器之電路及其相似物)係製造於不同晶圓之上，且每一晶圓晶粒係使用拾取-及-放置技術堆疊於另一晶圓晶粒之頂部上。藉由採用多晶片半導體元件可獲得更高的密度。再者，多晶片半導體元件可實現更小的形成因子(form factor)、更具成本效益(cost-effectiveness)、更佳的效能、及較低的能量損耗。
三維積體電路可包括頂主動電路層、底主動電路層、及複數個中間層。在三維積體電路中，兩晶粒可透過複數個凸塊而接合在一起，並透過複數個導電通孔(through vias)而彼此電性耦接。凸塊及導電通孔於三維積體電路之垂直軸提供電性連接。因此，兩半導體晶粒之間的訊號路徑短於傳統三維積體電路中之訊號路徑，在傳統三維積體電路中，不同的晶粒係使用內連線技術而接合在一起，例如導線接合的晶片堆疊封裝。三維積體電路可包括各種堆疊在一起之半導體晶粒。數個半導體晶粒於晶圓切割前已封裝完成。晶圓級封裝技術具有一些優點。於晶圓級封裝階段封裝多個半導體晶粒的優點之一為多晶片晶圓級封裝技術可降低製作成本。晶圓級封裝多晶片半導體元件的另一優點為可藉著採用凸塊及導電通孔來降低寄生損失(parasitic losses)。
本發明一實施例提供一種一種三維積體電路的組裝方法，包括：提供一承載晶圓，承載晶圓具有多個凹槽形成於承載晶圓中；提供一中介板，中介板包括：多個第一凸塊，配置於中介板的一第一側上；以及多個第二凸塊，配置於中介板的一第二側上，其中各第一凸塊與各第二凸塊為圓形；將中介板貼附至承載晶圓，且配置第一凸塊以使各第一凸塊位於承載晶圓中的一對應凹槽中；將一半導體晶粒貼附至中介板的第二側上以形成一晶圓堆疊；以及將晶圓堆疊貼附至一基板。
本發明一實施例提供一種三維積體電路的組裝方法，包括：提供一承載晶圓，承載晶圓具有多個凹槽形成於承載晶圓中；提供一中介板，中介板包括：多個第一凸塊，配置於中介板的一第一側上；以及多個第二凸塊，配置於中介板的一第二側上，其中各第一凸塊與各第二凸塊為方形；將中介板貼附至承載晶圓，且配置第一凸塊以使各第一凸塊位於承載晶圓中的一對應凹槽中；利用一第一回焊製程將一半導體晶粒貼附至中介板的第二側上以形成一晶圓堆疊；以及利用一第二回焊製程將晶圓堆疊貼附至一基板。
本發明另一實施例提供一種三維積體電路的組裝方法，包括：將一中介板貼附至一承載晶圓，承載晶圓具有多個凹槽，其中中介板包括：多個第一凸塊，配置於中介板的一第一側上，其中各第一凸塊係位於承載晶圓中的一對應凹槽中；以及多個第二凸塊，配置於中介板的一第二側上；利用一第一回焊製程將一半導體晶粒貼附於中介板的第二側上，以形成一晶圓堆疊；以及利用一第二回焊製程將晶圓堆疊貼附至一基板。
以下將詳細說明本發明實施例之製作與使用方式。然應注意的是，本發明提供許多可供應用的發明概念，其可以多種特定型式實施。文中所舉例討論之特定實施例僅為製造與使用本發明之特定方式，非用以限制本發明之範圍。此外，在不同實施例中可能使用重複的標號或標示。這些重複僅為了簡單清楚地敘述本發明，不代表所討論之不同實施例及/或結構之間具有任何關連性。再者，當述及一第一材料層位於一第二材料層上或之上時，包括第一材料層與第二材料層直接接觸或間隔有一或更多其他材料層之情形。在圖式中，實施例之形狀或是厚度可擴大，以簡化或是方便標示。再者，圖中未繪示或描述之元件，為所屬技術領域中具有通常知識者所知的形式。
本揭露將以特定的情況的實施例加以描述，承載晶圓具有多個凹槽以提供支撐，其於三維積體電路製程中支撐半導體晶圓堆疊。本揭露的實施例亦可應用於多種半導體製程中。
首先，參照第1圖，其繪示本發明一實施例之晶圓堆疊的剖面圖。晶圓堆疊100包括一基板150、一中介板(interposer)130、一第一半導體晶粒110、以及一半導體晶粒120。如第1圖所示，中介板130經由多個第一凸塊(bump)112貼附至基板150。特別是，中介板130的第一側經由多個第一凸塊112耦接至基板150。此外，可有一第一底膠材料層(underfill material layer)140位於中介板130與基板150之間。
第1圖更繪示第一半導體晶粒110與半導體晶粒120經由多個第二凸塊107貼附至中介板130的第二側。同樣地，可有一第二底膠材料層160位於半導體晶粒(例如半導體晶粒110)與中介板130之間。第一半導體晶粒110與第二半導體晶粒120的主動線路(未繪示)係經由一導電路徑耦接至基板150，導電路徑係由一第一重佈線層106、第二凸塊107、一第二重佈線層108、多個導電通孔(例如導電通孔132)、第三重佈線層(例如重佈線層122)、以及第一凸塊112所構成。
第2圖至第5圖繪示本發明一實施例之第1圖的晶圓堆疊100的製程剖面圖。第2圖繪示中介板130位於承載晶圓202上的剖面圖。在一實施例中，承載晶圓202的材質為矽、玻璃、或其相似物。可以適當的方法形成承載晶圓202中的凹槽(例如凹槽212、214、216)，例如濕式蝕刻、乾式蝕刻、及/或其相似方法。值得注意的是，在承載晶圓202的上視圖中，凹槽的開口實質上呈圓形。在不脫離本發明多個實施例的範圍與精神下，凹槽亦可為其他形狀，例如橢圓形、正方形、或矩形，但不限於此。
如承載晶圓202的上視圖所示，可有多個凹槽位於承載晶圓202中。形成多個凹槽(例如凹槽212、214、216)，以使各凹槽對齊與其對應的位於中介板130的第一側上的第一凸塊。此外，各凹槽的開口略大於其對應的凸塊的直徑，以使凸塊可置於凹槽內。在一實施例中，凹槽內壁與第一凸塊的間距係為10微米至20微米。此外，承載晶圓202的凹槽的深度為120微米。如第2圖所示，承載晶圓202可提供支撐，其可於後續的製程中支撐中介板130。
在進行多個凸塊回焊製程(reflow process)之後，中介板130可包括位於第一側上的第一凸塊112以及位於第二側上的第二凸塊107。將凸塊貼附於中介板之兩側的製程係為本領域技術人士所熟知，故於此不再進一步討論細節。在回焊製程之後，中介板130被挑選出來(picked)且位於承載晶圓202上。如第2圖所示，各第一凸塊係對齊於一對應的凹槽且置於對應的凹槽中。因此，中介板130的第一凸塊被其對應的凹槽的內壁圍繞。
第3圖繪示本發明一實施例之將多個半導體晶粒接合至中介板的頂端。多個半導體晶粒(例如半導體晶粒302)被挑選出來且配置於中介板130的頂端上。在一回焊製程之後，半導體晶粒接合至中介板130上經由位於中介板130與半導體晶粒(例如半導體晶粒302)之間的凸塊107。將半導體晶粒接合至中介板上的詳細製程係為本領域技術人士所熟知，故於此不再討論。
如第3圖所示，四個半導體晶粒302、304、306、308具有實質上相同的結構。為簡化起見，只有第一半導體晶粒302的結構詳述如下。值得注意的是，為了有助於對多個實施例之發明概念有基本理解，故繪示了第一半導體晶粒302、第二半導體晶粒304、第三半導體晶粒306、第四半導體晶粒308，但未繪示其細節。然而，值得注意的是，第一半導體晶粒302、第二半導體晶粒304、第三半導體晶粒306、第四半導體晶粒308可包括基本的半導體層，例如主動電路層、基板層、層間介電層(inter-layer dielectric(ILD)layer)、以及金屬間介電層(inter-metal dielectric(IMD)layer)，未繪示。
如第3圖所示，第一半導體晶粒302包括一基板102。基板102可為一矽基板。或者是，基板102可為一絕緣層上矽基板。基板102可更包括多種電路(未繪示)。形成在基板102上的電路可為適用於特定應用之任一類型的電路。
在一實施例中，電路可包括各種n型金氧半導體及/或p型金氧半導體元件，例如電晶體、電容、電阻、二極體、光二極體、保險絲、及其相似物。電路可互連以進行一或多種功能。前述功能可包括記憶體結構、製程結構、感測器、放大器、功率分配器(power distribution)、輸入/輸出電路、或其相似物。本領域具有通常知識者當可知道前述實施例僅用以介紹以進一步解釋本發明，而非用以限定本發明。
一隔離層104形成於基板102上。隔離層(isolation layer)104的材質例如為低介電常數材料，例如氧化矽。可以任何已知的適合的方法形成隔離層104，例如旋轉、化學氣相沉積、以及電漿增強式化學氣相沉積。亦值得注意的是，本領域具有通常知識者當可理解隔離層104可更包括多個介電層。
一重佈線層106係形成在隔離層104上。第一半導體晶粒302的主動電路層(未繪示)可利用重佈線層106橋接，以使第一半導體晶粒302的主動線路層可耦接至半導體晶粒302的輸入及輸出端。多個底凸塊金屬(under bump metal，UBM)結構(未繪示)可形成在重佈線層106上。當提供一低阻抗電性連接時，底凸塊金屬結構可有助於避免互連凸塊(例如第二凸塊107)以及第一半導體晶粒302的積體電路之間的擴散。互連凸塊(例如第二凸塊107)提供一有效的路徑以連接第一半導體晶粒302與中介板130。互連凸塊為第一半導體晶粒302的輸入/輸出端。在一實施例中，互連凸塊(例如第二凸塊107)可為多個焊球。或者是，互連凸塊(例如第二凸塊107)可為多個地柵陣列(land grid array)接墊。
在將半導體晶粒(例如半導體晶粒302)接合至中介板130之後，半導體晶粒(例如第一半導體晶粒302)的主動電路係經由一由中介板130上的重佈線層(例如重佈線層108)所構成的導電通道耦接至中介板130的凸塊(例如凸塊112)，互連凸塊連接於中介板130與半導體晶粒(例如第一半導體晶粒302)之間。
第4圖繪示本發明一實施例之一晶圓堆疊的剖面圖，前述晶圓堆疊具有一底膠材料層形成於半導體晶粒與承載晶圓之間。一底膠材料層160可形成於中介板130與多個位於中介板130的頂面上的半導體晶粒(例如第一半導體晶粒302)之間的間隙中。在一實施例中，底膠材料160可為環氧樹脂，其係位於中介板130與半導體晶粒(例如第一半導體晶粒302)之間的間隙中。環氧樹脂可為液態，且可在進行一固化製程(curing process)之後硬化。
在另一實施例中，底膠材料層160的材質可為可固化的材料，例如高分子基材料(polymer based material)、樹脂基材料(resin based material)、聚亞醯胺、環氧樹脂、以及前述之組合。底膠材料層160的製作方法包括旋轉塗佈製程、乾膜貼合製程(dry film lamination process)、及/或其相似製程。使用底膠材料(例如底膠材料160)的好處在於底膠材料160可有助於使晶圓堆疊400免於在熱循環製程(thermal cycling process)中破裂。此外，使用底膠材料的另外一個好處是底膠材料160可有助於在晶圓堆疊400的製程中減少機械應力與熱應力。
第5圖繪示本發明一實施例之位於一基板上的一晶圓堆疊的堆疊製程。可將第4圖所示之晶圓堆疊400由承載晶圓202上拆下，並透過另一回焊製程將晶圓堆疊400接合至一基板150上。之後，一第二底膠材料層140形成在中介板130與基板150之間。第二底膠材料層140的形成方式相似於底膠材料層160的形成方式，故於此不再詳細討論。
如第5圖所示，在將晶圓堆疊400接合至基板150之後，半導體晶粒(例如第一半導體晶粒302)的主動電路係經由一導電通道耦接至基板150，導電通道係由半導體晶粒上的重佈線層所構成，互連凸塊係連接中介板130、半導體晶粒302、中介板130上的重佈線層、中介板130中的導電通孔、以及位於中介板130與基板150之間的凸塊。
第6圖至第8圖繪示本發明另一實施例之晶圓堆疊的製程剖面圖。第6圖至第8圖相似於第3圖至第5圖，除了可能有一半導體晶粒(例如半導體晶粒602)接合在中介板130上。晶圓堆疊600的製程相似於晶圓堆疊100的製程，因此，於此不再贅述。形成底膠材料層160、將晶圓堆疊600貼附至一基板150、以及形成底膠材料層140的製作流程可參照第3圖至第5圖的描述，故於此不再贅述。
第9圖至第12圖繪示本發明又一實施例之晶圓堆疊的製程剖面圖。第9圖至第12圖係相似於第2圖至第5圖，除了在將中介板130配置於承載晶圓202的頂面上之前，位於中介板130的兩側上的凸塊(例如凸塊912、914)並未經過凸塊回焊(bump reflow)。為避免半導體晶粒在圓形凸塊(例如凸塊107，如第2圖所示)上滑動，可採用一不經凸塊回焊處理的中介板以避免半導體晶粒在中介板上滑動。如第10圖所示，方形凸塊(例如凸塊914)有助於保持半導體晶粒的位置。形成底膠材料層160、將晶圓堆疊貼附至一基板150、以及形成底膠材料層140的製作流程可參照第3圖至第5圖的描述，故於此不再贅述。
本發明雖以較佳實施例揭露如上，然其並非用以限定本發明的範圍，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可做些許的更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
100．．．晶圓堆疊
102．．．基板
104．．．隔離層
106．．．重佈線層
107．．．(第二)凸塊
108．．．第二重佈線層
110．．．第一半導體晶粒
112．．．第一凸塊
120．．．半導體晶粒
122．．．重佈線層
130．．．中介板
132．．．導電通孔
140．．．第一底膠材料層
150．．．基板
160．．．(第二)底膠材料層
202．．．承載晶圓
212、214、216．．．凹槽
302、304、306、308．．．半導體晶粒
400、600．．．晶圓堆疊
602．．．半導體晶粒
912、914．．．凸塊
第1圖繪示本發明一實施例之晶圓堆疊的剖面圖。
第2圖繪示承載晶圓上之複數個中介板之剖面圖。
第3圖繪示本發明一實施例之接合於中介板頂部上之複數個半導體晶粒的剖面圖。
第4圖繪示具有底膠材料形成於複數個半導體晶粒與複數個中介板間之晶圓堆疊的剖面圖。
第5圖繪示本發明一實施例之於基底上堆疊晶圓堆疊之製程。
第6-8圖繪示本發明另一實施例之製作晶圓堆疊的製程剖面圖。
第9-12圖繪示本發明又一實施例之製作晶圓堆疊的製程剖面圖。
107．．．第二凸塊
112．．．第一凸塊
130．．．中介板
202．．．承載晶圓
212、214、216．．．凹槽

Claims (10)

  1. 一種三維積體電路的組裝方法，包括：提供一承載晶圓，該承載晶圓具有多個凹槽形成於該承載晶圓中；提供一中介板，該中介板包括：多個第一凸塊，配置於該中介板的一第一側上；多個第二凸塊，配置於該中介板的一第二側上，其中各該第一凸塊與各該第二凸塊為圓形；將該中介板貼附至該承載晶圓，且配置該些第一凸塊以使各該第一凸塊位於該承載晶圓中的一對應凹槽中；將一半導體晶粒貼附至該中介板的該第二側上以形成一晶圓堆疊；以及將該晶圓堆疊貼附至一基板。
  2. 如申請專利範圍第1項所述之三維積體電路的組裝方法，更包括：形成一第一底膠層於該中介板與該半導體晶粒之間；以及形成一第二底膠層於該中介板與該基板之間。
  3. 如申請專利範圍第1項所述之三維積體電路的組裝方法，其中該中介板包括：多個位於該中介板中的導電通孔；一第一重佈線層，位於該中介板的該第一側上；以及一第二重佈線層，位於該中介板的該第二側上，其中該些第一凸塊經由該第一重佈線層分別連接至該些導電通孔，該些第二凸塊經由該第二重佈線層分別連接至該些導電通孔；由該半導體晶粒形成至該基板的一導電路徑包括該些第一凸塊、該第一重佈線層、該些導電通孔、該第二重佈線層、以及該些第二凸塊。
  4. 如申請專利範圍第1項所述之三維積體電路的組裝方法，更包括：由該承載晶圓上取下該晶圓堆疊。
  5. 如申請專利範圍第1項所述之三維積體電路的組裝方法，其中該些凹槽對應於該中介板的該些第一凸塊的圖案。
  6. 一種三維積體電路的組裝方法，包括：提供一承載晶圓，該承載晶圓具有多個凹槽形成於該承載晶圓中；提供一中介板，該中介板包括：多個第一凸塊，配置於該中介板的一第一側上；以及多個第二凸塊，配置於該中介板的一第二側上，其中各該第一凸塊與各該第二凸塊為方形；將該中介板貼附至該承載晶圓，且配置該些第一凸塊以使各該第一凸塊位於該承載晶圓中的一對應凹槽中；利用一第一回焊製程將一半導體晶粒貼附至該中介板的該第二側上以形成一晶圓堆疊；以及利用一第二回焊製程將該晶圓堆疊貼附至一基板。
  7. 如申請專利範圍第6項所述之三維積體電路的組裝方法，更包括：將該半導體晶粒接合至該中介板；形成一第一底膠層於該中介板與該半導體晶粒之間；將該晶圓堆疊接合至該基板；以及形成一第二底膠層於該中介板與該基板之間。
  8. 如申請專利範圍第6項所述之三維積體電路的組裝方法，更包括：依據該中介板的該些第一凸塊的一圖案圖案化該承載晶圓，以形成該些凹槽。
  9. 一種三維積體電路的組裝方法，包括：將一中介板貼附至一承載晶圓，該承載晶圓具有多個凹槽，其中該中介板包括：多個第一凸塊，配置於該中介板的一第一側上，其中各該第一凸塊係位於該承載晶圓中的一對應凹槽中；以及多個第二凸塊，配置於該中介板的一第二側上；利用一第一回焊製程將一半導體晶粒貼附於該中介板的該第二側上，以形成一晶圓堆疊；以及利用一第二回焊製程將該晶圓堆疊貼附至一基板。
  10. 如申請專利範圍第9項所述之三維積體電路的組裝方法，更包括：成形該承載晶圓以使：各凹槽大於其對應的凸塊；以及各凸塊塞入其對應的凹槽中。
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