TW201246414A - Method for producing package substrate for mounting semiconductor element, package substrate for mounting semiconductor element, and semiconductor package - Google Patents

Method for producing package substrate for mounting semiconductor element, package substrate for mounting semiconductor element, and semiconductor package Download PDF

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Publication number
TW201246414A
TW201246414A TW101108124A TW101108124A TW201246414A TW 201246414 A TW201246414 A TW 201246414A TW 101108124 A TW101108124 A TW 101108124A TW 101108124 A TW101108124 A TW 101108124A TW 201246414 A TW201246414 A TW 201246414A
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Taiwan
Prior art keywords
metal foil
carrier metal
circuit
package substrate
flip chip
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TW101108124A
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Chinese (zh)
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TWI600097B (en
Inventor
Tadashi Tamura
Saori Kawasaki
Akihiko Wakabayashi
Kuniji Suzuki
Yoshiaki Tsubomatsu
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Hitachi Chemical Co Ltd
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Priority claimed from JP2011051378A external-priority patent/JP5769001B2/en
Application filed by Hitachi Chemical Co Ltd filed Critical Hitachi Chemical Co Ltd
Publication of TW201246414A publication Critical patent/TW201246414A/en
Application granted granted Critical
Publication of TWI600097B publication Critical patent/TWI600097B/en

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4682—Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06568—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices decreasing in size, e.g. pyramidical stack
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10674—Flip chip
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/15—Position of the PCB during processing
    • H05K2203/1536—Temporarily stacked PCBs
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0097—Processing two or more printed circuits simultaneously, e.g. made from a common substrate, or temporarily stacked circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Wire Bonding (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

Provided is a method and the like that is for producing a package substrate for mounting a semiconductor element, can support heightened density, and has superior reliability. The method and the like for producing a package substrate for mounting a semiconductor element has: a step for preparing a multi-layer metal foil that laminates a first carrier metal foil, a second carrier metal foil, and a base metal foil, and forming a core substrate by laminating the multi-layer metal foil to a substrate ; a step for physically peeling the first carrier metal foil between the first carrier metal foil and the second carrier metal foil of the multi-layer metal foil; a step for performing a first pattern plating on the second carrier metal foil; a step for forming a laminate by forming an insulating layer, a conductive circuit, and an interlayer connection on the first pattern plating; a step for peeling the laminate together with the carrier metal foil from the core substrate; and a step for forming a 3D circuit or an embedded circuit by means of etching.

Description

201246414 六、發明說明： 【發明所屬之技術領域】 本發明’係有關於可進行高密度化之半導體元件搭載 用封裝基板之製造方法、半導體元件搭載用封裝基板及半 導體封裝，更詳細而言，係有關於具備有與具有突塊之半 導體元件作連接之倒裝晶片連接端子的半導體元件搭載用 封裝基板之製造方法、半導體元件搭載用封裝基板及半導 體封裝。 【先前技術】 作爲將半導體元件和半導體元件搭載用封裝基板（以 下’亦有將「半導體元件搭載用封裝基板」稱作「封裝基 板」的情況）之連接端子作電性連接的方法，係使用有倒 裝晶片連接法。在此倒裝晶片連接中，爲了在其與半導體 元件的突塊之間形成良好之銲錫塡料，多係使用有：在封 裝基板之倒裝晶片連接端子上形成預備銲錫，並經由此預 備銲錫和被形成在半導體元件之突塊處的銲錫之雙方，來 確保銲錫量，並與設置在半導體元件處之突塊作連接的方 法。另一方面’伴隨著電子零件之小型化或高密度化，係 產生有需要將與半導體元件間之連接端子以高密度來作配 置的必要’而對於倒裝晶片連接端子之細微化有所要求。 若是將倒裝晶片連接端子細微化，則由於被形成有預 備銲錫之接觸端子的面積係減少，因此，被形成在倒裝晶 片連接端子上的預備銲錫之量亦會減少，其結果，在與半 -5- 201246414 導體元件之突塊間所形成的銲錫塡料之形成會成爲並不充 分，並有著使連接信賴性降低的問題。又，若是想要在細 微之倒裝晶片連接端子上，形成對於與半導體元件間之連 接而言爲充分之量的預備銲錫，則如圖1中所示一般，在 —般性之製法中，倒裝晶片連接端子26，係會相對於封裝 基板之表面而被形成爲凸狀，因此，預備銲錫19會繞流 到倒裝晶片連接端子26的側面處，而有著在與相鄰接之 倒裝晶片連接端子26之間而產生預備銲錫1 9之架橋的問 題。亦即是，就算是將預備銲錫1 9作爲用以形成在倒裝 晶片連接端子26上之銲錫而作供給，亦會有相當比例之 銲錫覆蓋於倒裝晶片連接端子26之側面處而被耗費，用 以形成在進行連接中所需要的銲錫塡料所能夠使用之預備 銲錫1 9之比例係會減少，不僅如此，還會有與相鄰接之 倒裝晶片連接端子26之間產生架橋的情況。 作爲改善此種問題之方法，係揭示有：將在封裝基板 上之成爲倒裝晶片連接端子的區域處之配線圖案形成爲較 長，以使此區域之銲錫量增加的方法（專利文獻1)，或 者是將成爲倒裝晶片連接端子之區域的配線圖案之寬幅， 相較於其他區域而部分性地設定爲較廣之寬幅，並藉由此 來使倒裝晶片連接端子上之預備銲錫量增加的方法（專利 文獻2)。 〔先前技術文獻〕 〔專利文獻〕 -6 - 201246414 〔專利文獻1〕日本特開2002-329744號公報 〔專利文獻2〕日本特開2005-101137號公報 【發明內容】 〔發明所欲解決之課題〕 若依據上述之專利文獻1、2的方法，則用以與半導 體元件之間作連接之倒裝晶片連接端子上的預備銲錫之量 ，係能夠作某種程度的確保。但是，如圖1中所示一般， 形成倒裝晶片連接端子26之電路圖案，係爲從封裝基板i 之表面而形成爲凸狀之電路圖案（以下，亦有稱作「凸狀 電路」之情況），會與封裝基板1之絕緣層3的表面相密 著者，係僅有此凸狀電路32之底面。並且，此凸狀電路 32，一般而言，由於係藉由半增層法等之伴隨有鈾刻的方 法而被形成，因此，係會產生所謂的基蝕（UNDERCUT) ，其結果’電路圖案之寬幅，係相較於頂部（表面側）， 而在厚度方向之途中或者是底部（底面側）處而變得較爲 狹窄。因此，若是將倒裝晶片連接端子26細微化，則會 起因於倒裝晶片連接端子26和其下方的絕緣層3之間的 密著面積之減少、或者是電路圖案的寬幅之減少，而使密 著力降低，就算是僅在進行倒裝晶片連接時而施加有些許 之外力，亦會有發生倒裝晶片連接端子26之剝離的可能 性。 本發明，係爲有鑑於上述問題點而進行者，其目的， 係在於提供一種：能夠形成就算細微也能夠確保密著力之 201246414 倒裝晶片連接端子，並且具備有能夠在與半導體元件之突 塊間的倒裝晶片連接中確保有必要之預備銲錫量的倒裝晶 片連接端子，而藉由此成爲能夠與高密度化相對應且在信 賴性上亦爲優良之半導體元件搭載用封裝基板之製造方法 、半導體元件搭載用封裝基板、以及半導體封裝。 〔用以解決課題之手段〕 本發明，係有關於下述發明。 1.—種半導體元件搭載用封裝基板之製造方法，其 特徵爲，具備有：準備將第1載體金屬箔和第2載體金屬 箔以及基底金屬箔依此順序作了層積之多層金屬箔，並將 此多層金屬箔之基底金屬箔側和基材作層積而形成核心基 板之工程；和在前述多層金屬箔之第1載體金屬箔和第2 載體金屬箔之間，將第1載體金屬箔作物理性剝離之工程 ;和在前述核心基板之第2載體金屬箔上，進行第1圖案 鍍敷之工程；和在包含有前述第1圖案鍍敷之第2載體金 屬箔上，形成絕緣層和導體電路以及層間連接，而形成層 積體之工程；和在前述多層金屬箔之第2載體金屬箔和基 底金屬箔之間，將前述層積體與前述第2載體金屬箔一同 從核心基板物理性剝離地而分離之工程；和在前述作了剝 離的層積體之第2載體金屬箔上，形成蝕刻阻劑並進行蝕 刻，藉由此來使第1圖案鍍敷從前述層積體表面之絕緣層 露出而形成埋入電路之工程、或者是在前述層積體表面之 第1圖案鍍敷上形成立體電路之工程、或者是在前述層積 -8 - 201246414 體表面之絕緣層上形成立體電路之工程'或者是在前述層 積體表面之第1圖案鍍敷上形成凹陷形狀之工程。 2. —種半導體元件搭載用封裝基板之製造方法’其 特徵爲，具備有：準備將第1載體金屬箱和第2載體金屬 箔以及基底金屬箔依此順序作了層積之多層金屬箔’並將 此多層金屬箔之基底金屬箔側和基材作層積而形成核心基 板之工程；和在前述多層金屬箔之第1載體金屬箔和第2 載體金屬箔之間’將第1載體金屬箔作物理性剝離之工程 :和在前述核心基板之第2載體金屬箔上’進行第1圖案 鍍敷之工程；和在包含有前述第1圖案鍍敷之第2載體金 屬箔上，形成絕緣層和導體電路以及層間連接’而形成層 積體之工程；和在前述多層金屬箔之第2載體金屬箔和基 底金屬箔之間，將前述層積體與第2載體金屬箔一同從核 心基板物理性地剝離而分離之工程；和在前述作了剝離的 層積體之第2載體金屬箔上，進行第2圖案鍍敷之工程； 和在進行了前述第2圖案鍍敷之部分以外的第2載體金屬 箔上，形成蝕刻阻劑並進行蝕刻，而將進行了前述第2圖 案鍍敷之部分以及形成了蝕刻阻劑的部分以外之第2載體 金屬箔藉由蝕刻而除去之，藉由此來使第1圖案鍍敷從前 述層積體表面之絕緣層露出而形成埋入電路之工程、或者 是在前述層積體表面之第1圖案銨敷上形成立體電路之：C 程、或者是在前述層積體表面之絕緣層上形成立體電路;^ 工程、或者是在前述層積體表面之第1圖案鍍敷上形成凹 陷形狀之工程。 -9- 201246414 3. 如第1項或第2項所記載之半導體元件搭載用封 裝基板之製造方法，其中，在包含第1圖案鍍敷之第2載 體金屬箔上，形成絕緣體和導體電路以及層間連接，而形 成層積體之工程、和在多層金屬箔之第2載體金屬箔和基 底金屬箔之間，將前述層積體與第2載體金屬箔一同從核 心基板物理性地剝離並分離之工程，此兩者之工程之間， 係具備有：形成所期望之層數的絕緣層和導體電路之工程 〇 4. 如第1〜3項中之任一項所記載之半導體元件搭載 用封裝基板之製造方法，其中，在使第1圖案鍍敷從層積 體表面之絕緣層露出並形成埋入電路之工程中，係形成倒 裝晶片連接端子，在於層積體表面之第1圖案鍍敷上形成 立體電路之工程中，係形成柱（pillar )或者是在倒裝晶 片連接端子之長邊方向的一部份處形成凸形狀，在於層積 體表面之絕緣層上形成立體電路之工程中，係形成假端子 〇 5. —種半導體元件搭載用封裝基板，係爲藉由如第1 〜4項中之任一項所記載之半導體元件搭載用封裝基板之 製造方法製造出的半導體元件搭載用封裝基板，其特徵爲 ，係具備有：絕緣層；和以使上表面露出於此絕緣層之表 面處的方式而設置之埋入電路；和被設置在前述絕緣層上 以及埋入電路上之銲料阻劑，被配置在此銲料阻劑之開口 內的埋入電路，係形成倒裝晶片連接端子，此倒裝晶片連 接端子’係經由厚度3^m以上之預備銲錫而被覆。 -10- 201246414 6. 如第5項所記載之半導體元件搭載用封裝基板， 其中，在形成倒裝晶片連接端子之埋入電路的底面處’係 連接有通孔。 7. 如第5項或第6項所記載之半導體元件搭載用封 裝基板，其中，在倒裝晶片連接端子之長邊方向的一部份 處，係被形成有凸形狀。 8. 如第5〜7項中之任一項所記載之半導體元件搭載 用封裝基板，其中，在倒裝晶片連接端子之長邊方向的一 部份處，係被形成有凹陷形狀。 9. 如第5〜8項中之任一項所記載之半導體元件搭載 用封裝基板，其中，倒裝晶片連接端子之前端，係被配置 於銲料阻劑之開口內。 10. 如第5〜9項中之任一項所記載之半導體元件搭 載用封裝基板，其中，係設置有具備在倒裝晶片連接端子 之長邊方向的兩側或者是單側處而作了延長的部分之埋入 電路。 11. 如第5〜10項中之任一項所記載之半導體元件搭 載用封裝基板，其中，倒裝晶片連接端子之一部份，係在 短邊方向上被作了擴張。 12. —種半導體封裝，其特徵爲：係在如第5〜11項 中之任一項所記載之半導體元件搭載用封裝基板的倒裝晶 片連接端子上，藉由倒裝晶片連接而搭載有半導體元件之 突塊。 -11 - 201246414 〔發明之效果〕 若依據本發明，則係能夠提供一種：能夠形成就算細 微也能夠確保密著力之倒裝晶片連接端子，並且具備有能 夠在與半導體元件之突塊間的倒裝晶片連接中確保有必要 之預備銲錫量的倒裝晶片連接端子，而藉由此成爲能夠與 高密度化相對應且在信賴性上亦爲優良之半導體元件搭載 用封裝基板之製造方法、半導體元件搭載用封裝基板、以 及半導體封裝。 【實施方式】 以下，使用圖2〜圖9，針對本發明之半導體元件搭 載用封裝基板之例作說明。 作爲本發明之半導體元件搭載用封裝基板（以下，稱 作「封裝基板」）的第1例，係可列舉出：如圖2中所示 一般，具備有絕緣層3;和以使上面露出於此絕緣層3之 表面處的方式而被作設置之埋入電路2;和被設置在前述 絕緣層3上以及埋入電路2上之銲料阻劑4，並且，被配 置在此銲料阻劑4之開口 3 1內的埋入電路2，係形成倒裝 晶片連接端子26，此倒裝晶片連接端子26，係經由厚度3 //m以上之預備銲錫19而被作被覆的半導體元件搭載用 封裝基板1。若依據此構成，則倒裝晶片連接端子26，係 經由使上面露出於絕緣層3之表面的埋入電路2而形成之 。故而，由於倒裝晶片連接端子26之側面和底面，係被 埋入至絕緣層3中並被固定，因此形成倒裝晶片連接端子 -12- 201246414 26之埋入電路2，就算是身爲線/空間爲20/zm/2〇em 以下之水準的細微電路圖案，亦成爲能夠形成對於與絕緣 層3間之密著力作了確保的倒裝晶片連接端子26。由於若 是具備有在倒裝晶片連接端子26之長邊方向的兩側處作 了延長的埋入電路2，則係能夠使埋入電路2亦從兩側來 固定倒裝晶片連接端子26，因此，從密著力之確保的觀點 來看，係爲理想，但是，在本發明中，相較於圖1中所示 一般之凸狀電路32，係能夠形成就算是細微也能夠對於與 絕緣層3之間的密著力作確保之倒裝晶片連接端子26。因 此，亦可如圖3中所示一般，形成僅在倒裝晶片連接端子 26之長邊方向的單側處作了延長的埋入電路2，於此情況 ，由於係能夠將倒裝晶片連接端子26之尺寸縮小，因此 ，在能夠謀求更進一步之高密度化的觀點上，係爲理想。 又，亦可如圖4中所示一般，設置在倒裝晶片連接端子26 之長邊方向的單側以及兩側處作了延長之埋入電路2的雙 方。如此這般，在倒裝晶片連接端子26之長邊方向上作 了延長的埋入電路2，由於不論是設置在倒裝晶片連接端 子26之長邊方向的兩側處或者是僅設置在單側處均可， 因此，係能夠將設計上的自由度增大。又，由於倒裝晶片 連接端子26係經由厚度3 a m以上之預備銲錫1 9而被作 被覆，因此，係成爲能夠確保有在與半導體元件15之突 塊25之間的倒裝晶片連接中所必要之銲錫量。故而，係 可提供一種能夠與高密度化相對應並且在信賴性上亦爲優 良之半導體元件搭載用封裝基板1。 -13- 201246414 本發明之所謂絕緣層，係指使用有機絕緣材料所形成 之絕緣基板、核心基板、薄膜、層間絕緣層、增疊（ build-up )層等。作爲此種絕緣層，係可使用一般性之被 使用於封裝基板中者，並可列舉出在玻璃編織（glass cross)中含浸有環氧樹脂或聚醯亞胺樹脂的預浸體、將環 氧系接著薄片或聚醯亞胺系接著薄片等作加熱、加壓所形 成者。 本發明之所謂埋入電路，係指以至少將底面以及側面 的一部份埋入至絕緣層中並且至少使上面露出於絕緣層之 表面的方式所設置之電路。此種埋入電路，例如，可經由 所謂的轉印.法等來形成：亦即是，係將金屬箔作爲供電層 ，並於其上方藉由圖案鍍敷來形成特定之電路圖案，再於 此電路圖案上形成絕緣層，而將電路圖案埋入至絕緣層中 ，之後，藉由以蝕刻等來將作爲供電層之金屬箔除去，而 使被埋入至圖案絕緣層中之電路圖案的表面從絕緣層露出 本發明之所謂銲料阻劑，係爲以不會使預備銲錫附著 在成爲倒裝晶片連接端子之埋入電路以外之部分處的方式 而對於封裝基板之表面作保護者。又，係爲經由以被設置 在銲料阻劑處之開口來對於埋入電路中之成爲倒裝晶片連 接端子的部分作規定，來使此開口內之埋入電路形成倒裝 晶片連接端子者。作爲銲料阻劑，從能夠以良好之精確度 來形成用以形成倒裝晶片連接端子之縱l〇〇Mmx橫lOOym 以下的水準之微小開口的觀點來看*係以感光性之銲料阻 -14- 201246414 劑爲理想。 本發明之所謂倒裝晶片連接端子，係指用以將半導體 元件經由倒裝晶片連接來搭載在封裝基板上所使用之連接 端子。又，所謂倒裝晶片連接，係指使半導體元件之主動 元件面朝向封裝基板地來作連接之方法，並爲在半導體元 件上形成作爲電極之突塊，再將半導體元件翻轉而與封裝 基板上之搭載位置相合致，之後將半導體元件之突塊和被 形成於封裝基板上之倒裝晶片連接端子作連接的方法》本 發明之倒裝晶片連接端子，實際上係並不僅是指與半導體 元件之突塊作抵接的連接部，而亦指身爲與半導體元件之 突塊作連接之埋入電路的在銲料阻劑之開口內而從絕緣層 之表面露出了的部分。在倒裝晶片連接端子之表面上，係 亦可爲了防止表面之氧化並確保預備銲錫之浸濕性，而設 置鎳/金鍍敷（鎳鍍敷並於其上形成有金鍍敷者）或者是 鎳/鈀/金鍍敷（鎳鍍敷並於其上形成有鈀鍍敷且於其上 形成有金鍍敷者）等之保護鍍敷。 本發明之所謂預備銲錫，係指爲了進行與半導體元件 間之倒裝晶片連接而設置在倒裝晶片連接端子上之銲錫。 預備銲錫，係可經由將銲錫糊作印刷並作回焊之方法、或 者是其他之週知方法，來形成之。作爲銲錫糊之其中一例 ’係可例舉出在電子零件之安裝中所使用的將Sn (錫）-Pb (鉛）系、Sn (錫）-Ag (銀）-Cu (銅）系等之銲錫粒 子混合於松香或者是有機溶劑中者等。在銲錫糊之印刷中 ，係可使用金屬遮罩或絲網版等。回焊，係可藉由在電子 -15- 201246414 零件之安裝中所一般使用的紅外線回焊、熱風回焊 (vapor phase soldering)回焊等來進行之。回焊 雖係依存於銲錫糊而爲相異，但是’例如係可列舉 是Sn-Pb (錫和鉛）系，則峰値溫度係爲240°C程 是Sn (錫）-Ag (銀）-Cu (銅）系’則峰値溫度係 t的條件。 本發明之封裝基板，係將倒裝晶片連接端子經 3//m以上之預備銲錫來作了被覆。若是預備銲錫 未滿3 /z m，則在倒裝晶片連接端子和半導體元件 之間，係無法充分地形成銲錫塡料，而難以確保連 性。另一方面，若是預備銲錫之厚度超過20/zm， 與相鄰接之倒裝晶片連接端子上的預備銲錫之間產 架橋的可能性。因此，預備銲錫之厚度，係以3 β ' 、20 M m以下爲理想。另外，一般而言，由於倒裝 接端子之頂面係爲俯視時成細長之長方形，因此， 錫糊等進行回焊所形成的預備銲錫，係會經由銲錫 張力而形成爲略半圓柱狀（魚板狀故而，預備 厚度，係會在倒裝晶片連接端子之長邊方向（長度 和短邊方向（寬幅方向）的略中央處而形成爲最厚 ，在本發明中，預備銲錫之厚度，係設爲針對在倒 連接端子之長邊方向（長度方向）和短邊方向（寬 )的略中央處，而藉由非接觸式階差測定機來對於 蝕劑表面和銲錫表面間的階差作測定所求取出來者 作爲本發明之封裝基板的第2例，係可列舉出 、VPS 條件， 出：若 度，若 爲260 由厚度 之厚度 的突塊 接信賴 則會有 生銲錫 τι以上 晶片連 對於銲 之表面 銲錫之 方向） 。因此 裝晶片 幅方向 銲料抗 0 如圖5 -16- 201246414 中所示一般，在包含倒裝晶片連接端子26之埋入電路2 的底面處連接有通孔18者。另外，係省略預備銲錫之展 示。在圖5中，雖係於倒裝晶片連接端子26之底面以及 從此倒裝晶片連接端子26而朝向長邊方向作了延長之埋 入電路2的底面之雙方處，均形成有通孔18，但是，亦可 設爲僅在此些之其中一方處形成有通孔18。亦即是，在此 第2例中，係在被埋入於絕緣層3中之倒裝晶片連接端子 26的底面處、或者是在從此倒裝晶片連接端子26而朝向 長邊方向作了延長之埋入電路2的底面處、亦或是此些之 雙方的底面處，而被形成有通孔18。藉由如此這般地在底 面處連接通孔1 8，倒裝晶片連接端子26或者是從倒裝晶 片連接端子26所朝向長邊方向延長之埋入電路2，由於係 經由通孔18而被固定於絕緣層3處，因此，相較於第1 例，係成爲能夠使倒裝晶片連接端子26和絕緣層3之間 的密著更加強固》 在本發明中，所謂通孔，係爲將在封裝基板上而被設 置有多層之配線層的層間作連接者，例如，係可藉由先以 雷射等來形成配線層之層間連接用的孔，之後再對於此孔 內進行鍍敷等，來形成之。另外，爲了獲取更多之倒裝晶 片連接端子的底面或者是從倒裝晶片連接端子而朝向長邊 方向延長之埋入電路的底面之與通孔間的連接面積，較理 想’係藉由所謂的塡孔（filled via)鍍敷來形成通孔" 作爲本發明之封裝基板的第3例，係可列舉出如圖6 中所示一般，在倒裝晶片連接端子26之長邊方向的一部 -17- 201246414 份處形成有凸形狀27者。另外，係省略預備銲錫19之展 示。此凸形狀27，例如，係可藉由形成鍍敷阻劑，並對於 埋入電路之成爲倒裝晶片連接端子26的場所之一部份進 行圖案鍍敷，而形成之。又，雖並未圖示，但是，亦可先 形成從絕緣層3之表面而使側面之一部份和上面作了突出 之埋入電路，之後，形成蝕刻阻劑，並以使作了突出的埋 入電路之一部份維持爲突出地而殘留且使其他部分成爲與 絕緣層3之表面同一平面的方式來進行蝕刻，而形成之。 凸形狀27之高度，係以3/zm〜8/zm程度爲理想，設置 凸形狀27之範圍，係以成爲倒裝晶片連接端子26之短邊 方向（寬幅方向）的尺寸之5 0 %〜1 0 0 °/。且成爲倒裝晶片連 接端子26之長邊方向（長度方向）的尺寸之10%〜70%程 度爲理想。藉由如此這般地在倒裝晶片連接端子26之長 邊方向的一部份處形成凸形狀27，由於在凸形狀27之階 差部分處，銲錫係會積存（未圖示），因此，相較於表面 爲平坦的情況，係能夠使被配置在倒裝晶片連接端子26 之上的銲錫之量增加。又，凸形狀27，由於係成爲使其他 部分之銲錫作集中的契機，而銲錫係以凸形狀27作爲中 心地凝集，因此，係亦能夠將作了突出的銲錫積存部形成 於倒裝晶片連接端子26之長邊方向的特定之位置處。故 而，由於係能夠對應於被搭載在倒裝晶片連接端子26處 的半導體元件之突塊的位置，來設置倒裝晶片連接端子26 上之作突出的部分，因此，係能夠將倒裝晶片連接端子2 6 和半導體元件之突塊確實地作連接。 -18- 201246414 作爲本發明之封裝基板的第4例，係可列舉出如圖7 中所示一般，在倒裝晶片連接端子26之長邊方向的一部 份處形成有凹陷形狀2 8者。另外，係省略預備銲錫之展 示。雖並未圖示，但是，此凹陷形狀2 8，例如亦可先形成 從絕緣層3之表面而使上面作了露出之埋入電路，之後， 形成蝕刻阻劑，並以使將上面作了露出的埋入電路之上面 的一部份成爲較絕緣層3之表面更爲凹陷且使其他部分維 持原樣地殘留的方式來進行蝕刻，而形成之。凹陷形狀28 之深度，係以3 // m〜8 // m程度爲理想，設置凹陷形狀2 8 之範圍，係以成爲倒裝晶片連接端子26之短邊方向（寬 幅方向）的尺.寸之50%〜100%且成爲倒裝晶片連接端子 26之長邊方向（長度方向）的尺寸之10%~70%程度爲理 想。藉由如此這般地形成凹陷形狀28，由於熔融了的銲錫 係會積存於此部分處，因此，係能夠使配置在倒裝晶片連 接端子26上之銲錫（未圖示）的量增加。亦即是，由於 凹陷形狀28係發揮作爲使銲錫積存之容器的功能，而銲 錫係積存於凹陷形狀2 8之中，因此，係能夠在倒裝晶片 連接端子26上，形成爲了形成銲錫塡料所需之充分的銲 錫。 作爲本發明之封裝基板的第5例，係可列舉出如圖3 中所示一般’將倒裝晶片連接端子2 6之前端形成於銲料 阻劑4之開口 31內者。另外，係省略預備銲錫之展示。 當如同先前技術之一般的封裝基板一般，經由對於接著在 絕緣層3之表面上的金屬箔進行蝕刻來形成電路圖案的情 -19" 201246414 況時，此電路圖案，係爲凸狀電路32(圖1)，所形成之 倒裝晶片連接端子26，係僅有其之底面會與絕緣層3作接 著。又，由於係經由蝕刻所形成，因此，由凸狀電路3 2 所成之電路圖案，從剖面來觀察時，係產生有相較於電路 圖案之表面側而以底面側之寬幅爲更細的所謂基蝕（ undercut )現象。因此，若是將倒裝晶片連接端子26之尺 寸細微化，則由於由凸狀電路32所成之電路圖案的底面 和絕緣層3之間的接著面積會減少，因此，與絕緣層3之 間的密著力會降低，就算是僅在進行倒裝晶片連接時而施 加有些許之外力，亦會有發生剝離的可能性。因此，爲了 確保絕緣層3和倒裝晶片連接端子26之間的密著力，係 採用有：藉由銲料阻劑4來作被覆，而從上側來固定電路 圖案，並使倒裝晶片連接端子26從銲料阻劑4之開口 3 1 而露出，藉由此，來將倒裝晶片連接端子26之長邊方向 的兩側經由銲料阻劑4而作固定的方法。但是，在此方法 中，會起因於銲料阻劑4之解析度的極限而對於銲料阻劑 4之開口 3 1的寬幅有所限定，故而，係有必要將倒裝晶片 連接端子26設爲較銲料阻劑4之解析度的極限更長。又 ，起因於此，電路圖案之拉繞的自由度亦會受限。若依據 本發明之封裝基板1的第5例，則由於係經由使倒裝晶片 連接端子26之上面從絕緣層3之表面而露出了的埋入電 路而形成之，因此，就算是細微，亦成爲能夠確保密著力 。因此，係並不需要經由銲料阻劑4來將在倒裝晶片連接 端子26之長邊方向的兩側處作了延長的電路圖案從上方 -20- 201246414 而作被覆，而能夠將倒裝晶片連接端子26之前端形成於 銲料阻劑4之開口 3 1內。故而，由於並不會受到銲料阻 劑4之解析度所限制，而能夠將倒裝晶片連接端子26細 微化，因此，係成爲能夠謀求更高密度化，並且能夠將電 路圖案之設計的自由度提升。 作爲本發明之封裝基板的第6例，係可列舉出如圖4 中所示一般，設置有在倒裝晶片連接端子26之長邊方向 的兩側或者是單側處而作了延長之埋入電路2者。若依據 本發明之封裝基板的第6例，則與第5例相同的，由於並 不會受到銲料阻劑4之解析度所限制，而能夠將倒裝晶片 連接端子26細微化，因此，係成爲能夠謀求更高密度化 ，並且能夠將電路圖案之設計的自由度提升。 作爲本發明之封裝基板的第7例，係可列舉出如圖8 中所示一般，使倒裝晶片連接端子26之一部份具備有在 短邊方向（寬幅方向）上作了擴張的部分33者。倒裝晶 片連接端子26之前端，係亦可形成在銲料阻劑4之開口 31內。另外，係省略預備銲錫之展示。藉由使此倒裝晶片 連接端子26部分性地具備有在短邊方向（寬幅方向）上 作了擴張的部分3 3，由於其與絕緣層3之間的密著面積係 擴大，因此，係能夠使倒裝晶片連接端子26和絕緣層3 之間的密著力更進一步提升，並且，係能夠確保更多之預 備銲錫19的量，又，於短邊方向（寬幅方向）上被作了 擴張之部分33的預備銲錫19，由於係經由表面張力而將 其以外之部分的銲錫拉扯過來，並形成銲錫積存，因此， -21 - 201246414 係能夠將銲錫積存在特定之位置處而安定地形成》 作爲本發明之半導體封裝的其中一例，係可列舉出如 圖9中所示一般，在上述之第1〜第7例的封裝基板1上 ，而將半導體元件15藉由倒裝晶片連接來作了搭載者。 在半導體元件15之突塊25形成面和半導體元件搭載用封 裝基板1之具備有倒裝晶片連接端子26的絕緣層3之間 ，係以塡充有下部塡材23爲理想。若依據此，則下部塡 材23係成爲能夠使半導體元件15之突塊25形成面和具 備有倒裝晶片連接端子26的絕緣層3之間之密著力更加 強固。故而，係可提供一種能夠與高密度化相對應並且在 信賴性上亦爲優良之半導體封裝24。 以下，使用圖10〜圖18，針對本發明之封裝基板的 製造方法之其中一例作說明。 首先’如圖10中所示一般，準備將第1載體金屬箔 1 〇和第2載體金屬箔1 1以及基底金屬箔1 2依此順序來作 了層積之多層金屬箔9。 第1載體金屬箔10，係爲用以保護第2載體金屬箔 11之表面（與第1載體金屬箔10之間）者，而被設爲可 在其與第2載體金屬箔1 1之間作物理性剝離。只要能夠 保護第2載體金屬箔11之表面，則並不特別對於材質或 厚度作限制，但是，在汎用性和處理性之觀點上，作爲材 質’係以銅箔或鋁箔爲理想，作爲厚度，係以1〜3 5 v m 爲理想。又，較理想，在第〗載體金屬箔1〇和第2載體 金屬箱1 1之間，係設置有用以使在此些之間之剝離強度 -22- 201246414 安定化的剝離層（未圖示），作爲剝離層，較理想，係爲 就算是進行複數次之在與絕緣樹脂作層積時的加熱、加壓 ，亦能夠使剝離強度安定化者。作爲此種剝離層，係可列 舉出：在日本特開2003 - 1 8 1 970號公報中所揭示之形成有 金屬氧化物層和有機劑層者、在日本特開2003-094553號 公報中所揭示之由Cu-Ni-Mo合金所成者、在日本再公表 專利W02006/ 01 3735號公報中所揭示之含有Ni以及W 之金屬氧化物或者是Ni以及Mo之金屬氧化物者。另外， 此剝離層，較理想，當將第1載體金屬箔10在其與第2 載體金屬箔1 1之間進行物理性剝離時，係以附著在第1 載體金屬箔1 〇側的狀態.下被剝離，而並不會殘留在第2 載體金屬箔11之表面上。 第2載體金屬箔11，係爲成爲爲了在將第1載體金屬 箔1 0作了剝離後的表面上進行第1圖案電鍍1 3而供給電 流之種晶層（供電層）者，而被設爲可在其與第1載體金 屬箔1 0之間以及其與基底金屬箔1 2之間作物理性剝離》 只要能夠與基底金屬箔12 —同地作爲供電層而起作用， 則並不特別對於材質或厚度作限制，但是，在汎用性和處 理性之觀點上，作爲材質，係以銅箔或鋁箔爲理想，作爲 厚度，係可使用1〜18/zm者。但是，如同後述一般，由 於在形成外層電路2時（圖16(12) 、（13) 、（14)) ，係藉由蝕刻而被除去，因此，爲了極力降低蝕刻量之偏 差並形成高精確度之細微電路，係以1〜之極薄金屬 箔爲理想。又，在其與第1載體金屬箔1〇之間以及其與 -23- 201246414 基底金屬箔1 2之間’爲了將此些之間的剝離強度安定化 ，較理想，係設置如同上述一般之剝離層（未圖示）。另 外，此剝離層，由於係與第2載體金屬箔11以及基底金 屬箔12成爲一體並作爲種晶層而起作用，因此，係希望 爲具備有導電性者。另外，此剝離層，較理想，當在其與 第2載體金屬箔1 1和基底金屬箔1 2之間進行物理性剝離 時，係以附著在基底金屬箔1 2側的狀態下被剝離，而並 不會殘留在第2載體金屬箔11之表面上。 基底金屬箔12，係爲當將多層金屬箔9和基材16作 層積並製作出核心基板17時，位置在被與基材16作層積 之側者，並被設爲能夠在其和第2載體金屬箔1 1之間進 行物理性剝離。只要是在與基板1 6作層積時具備有其與 基板1 6間的接著性，則並不特別對於材質或厚度作限制 ，但是，在汎用性和處理性之觀點上，作爲材質，係以銅 箱或銘箱爲理想，作爲厚度，係以9〜爲理想。又 ，在其與第2載體金屬箔1 1之間，爲了將此些之間的剝 離強度安定化，較理想，係設置如同上述一般之剝離層（ 未圖示）。另外，此剝離層，較理想，當在.其與第2載體 金屬箔1 1和基底金屬箔1 2之間進行物理性剝離時，係以 附著在基底金屬箔1 2側的狀態下被剝離，而並不會殘留 在第2載體金屬箔11之表面上者。 作爲多層金屬箔9，係使用：身爲具備有3層以上之 金屬箔（例如，如同上述一般，具有第1載體金屬箔10 和第2載體金屬箔n以及基底金屬箔12)之多層金屬箔 -24- 201246414 9，並且至少在2個場所之間（例如，如同上述一般，在 第1載體金屬箔1〇和第2載體金屬箔11之間、以及在第 2載體金屬箔1 1和基底金屬箔1 2之間）而能夠作物理性 剝離者。在進行將基材16層積於多層金屬箔9之基底金 屬箔1 2側而形成核心基板1 7之工程時，雖然會有樹脂粉 等之異物附著在第1載體金屬箔1〇之表面上的情況，但 是，就算是附著有此種異物，由於藉由將第1載體金屬箔 10在其與第2載體金屬箔11之間而進行物理性剝離，係 能夠形成並未被樹脂粉等之異物所影響的第2載體金屬箔 11之表面，因此，係能夠確保有高品質之金屬箔表面。故 而，由於就算是在將第2載體金屬箔11作爲種晶層來使 用並進行第1圖案鍍敷13的情況時，亦能夠對於缺陷之 發生作抑制，因此，係成爲能夠謀求良率之提升。 接著，如圖11(1)中所示一般，將多層金屬箔9之 基底金屬箔1 2側和基材1 6作層積，而形成核心基板1 7。 基材16，係爲與多層金屬箔9作層積一體化並形成核心基 板1 7者，作爲基材1 6，係能夠使用一般性地作爲半導體 元件搭載用封裝基板1之絕緣層3所使用者。作爲此種基 材1 6，係可列舉出玻璃環氧 '玻璃聚醯亞胺等。核心基板 17，係爲在使用多層金屬箔9而製造封裝基板1時，成爲 支持基板者，並爲以經由對於剛性作確保來提升作業性一 事以及對於處理時之損傷作防止並使良率提升一事作爲主 要功用者。因此’作爲基材1 6，係以具備有玻璃纖維等之 補強材者爲理想，例如，係可藉由將玻璃環氧、玻璃聚醯 -25- 201246414 亞胺等之預浸材與多層金屬箔9重疊並使用熱壓等來進行 加熱、加壓而作層積一體化，來形成之。藉由在基材16 之兩側（圖.11(1)之上下兩側）處層積多層金屬箔9, 並進行其後之工程，由於係能夠藉由1次的工程來進行製 造2個的封裝基板1之工程，因此，係能夠謀求工程數之 降低。又，由於係能夠在核心基板1 7之兩側處構成對稱 之構成的層積板，因此，係能夠對於彎曲的情況作抑制， 且亦能夠對由於作業性或者是由於勾卡在製造設備處等所 導致的損傷作抑制。 接著，如圖11(2)中所示一般，在多層金屬箔9之 第1載體金屬箔10和第2載體金屬箔11之.間，將第1載 體金屬箔10作物理性剝離。在第1載體金屬箔1〇之表面 上，會有附著有在層積時而從成爲基材16之材料的預浸 材等而來之樹脂粉等之異物的情況。因此，當使用此第1 載體金屬箔10來形成電路的情況時，會有由於附著在表 面上之樹脂粉等的異物，而在電路中產生斷線或短路等之 缺陷的情況，並有導致良率之降低的可能性。但是，如此 這般，藉由將第1載體金屬箔10作剝離除去，由於係能 夠使用並未附著有樹脂粉等之異物的第2載體金屬箔11 來形成電路，因此，係能夠抑制電路缺陷之發生’並成爲 能夠改善良率。又，由於係能夠將第1載體金屬箔10作 物理性剝離，因此，藉由對於第1載體金屬箔10和第2 載體金屬箔1 1之間的剝離強度作調整’係能夠容易地進 行剝離作業。此時，較理想’在多層金屬箔9之第1載體 -26 - 201246414 金屬箔10和第2載體金屬箔11之間的剝離層（未圖示） ，係被帶走至第1載體金屬箔10側。藉由此，在將第1 載體金屬箔10作了剝離後之第2載體金屬箔Π側，由於 係露出有第2載體金屬箔1 1之表面，因此，在後續工程 中所進行之對於第2載體金屬箔11上的鍍敷阻劑或者是 第1圖案鍍敷1 3的形成，係不會有被剝離層所阻礙的情 況。 於此，多層金屬箔9，較理想，係爲使第2載體金屬 箔Π和基底金屬箔12之間的剝離強度成爲較第1載體金 屬箔10和第2載體金屬箔11之間的剝離強度更大之多層 金屬箔9。藉由此，在將第1載體金屬箔10和第2載體金 屬箔1 1之間作物理性剝離時，能夠對於將第2載體金屬 箔1 1和基底金屬箔1 2之間同時作剝離一事作抑制。作爲 剝離強度，在進行加熱、加壓前之初期狀態下，若是設爲 :於第1載體金屬箔10和第2載體金屬箔11之間，係設 爲2N/m〜5 ON/m，於第2載體金屬箔11和基底金屬箔 12之間，係設爲101^/111〜7 01^/^1，於第1載體金屬箔 1 0和第2載體金屬箔1 1之間的剝離強度，係成爲較於第 2載體金屬箔1 1和基底金屬箔1 2之間的剝離強度更小了 5N/m〜20N/m，則不會有在製造工程之處理中而發生剝 離的情況，而能夠容易地在其中一方作剝離，並且，在將 第1載體金屬箔1 〇作剝離時，能夠對於第2載體金屬箔 1 1同時被剝離的情況作抑制，因此，作業性係爲佳。 剝離強度之調整，例如，係可如同在日本特開2003 - -27- 201246414 181970號公報或日本特開2003-094553號公報、日本再公 表專利W02006/ 0 1 3 73 5號公報中所示一般，對於成爲剝 離層之基底的第2載體金屬箔π之表面（與第1載體金 屬箔1〇之間）的粗度作調整，或者是對於成爲剝離層之 金屬氧化物或用以形成合金鍍敷層之電鍍液組成或條件作 調整，來進行之。 接著’如圖Π ( 3 )中所示一般，在殘留於核心基板 17上之第2載體金屬箔11上，進行第1圖案鍍敷13。如 同上述一般，由於在第2載體金屬箔11之表面（與第1 載體金屬箱10之間），係並未附著有從在層積時所使用 之預浸材等而來的樹脂粉等之異物，因此，係成爲能夠對 於起因於此所導致之電路缺陷作抑制。第1圖案鍍敷1 3， 係可在第2載體金屬箔11上，形成鍍敷阻劑（未圖示） ，之後，使用電鍍而進行之。作爲鍍敷阻劑，係可使用在 封裝基板1之製造製程中所使用的感光性阻劑。作爲電鍍 ，係可使用在封裝基板1之製造製程中所使用的硫酸銅電 鍍。 多層金屬箔9，較理想，係爲在預先設置有平均粗度 (Ra)爲0.3"m〜1.2"m的凹凸之第2載體金屬箔11的 表面上，隔著剝離層（未圖示）而層積有第1載體金屬箔 10之多層金屬箔9。藉由此，將第1載體金屬箔10與剝 離層一同地作了物理性剝離後之第2載體金屬箔11的表 面，係具備有預先所設置之平均粗度（Ra)爲0.3#m〜 1.2；czm的凹凸》因此，當在第2載體金屬箔11之表面（ -28 - 201246414 和第1載體金屬箔10之間）上而形成第1圖案鍍敷13用 之鏟敷阻劑時，係能夠使鍍敷阻劑之密著性或解析度提升 ，對於高密度電路之形成而言係爲有利。又’藉由預先在 第2載體金屬箔11之表面上設置凹凸，在將第1載體金 屬箔10作了剝離後，由於係並不需要對於第2載體金屬 箔11之表面進行粗面化處理，因此，係能夠謀求工程數 之降低。 設置在第2載體金屬箔11之表面上的凹凸之表面粗 度，在能夠改善鍍敷阻劑之密著性或解析度並且確保第1 圖案鍍敷1 3後之剝離性的觀點上，係以平均粗度（Ra ) 爲0.3em〜1.2//m爲理想。當平均粗度（Ra)爲未滿0.3 V m的情況時，會有發生鍍敷阻劑之密著性不足的情形之 傾向，而當平均粗度（Ra )爲超過1 .2 μ m的情況時，會 有使鍍敷阻劑成爲難以作追隨並發生密著性不足的情形之 傾向。進而，當鍍敷阻劑之線/空間爲較1 5 a m / 1 5 // m 更細微的情況時，平均粗度（Ra )係以0.5 μ m〜0.9 // m 爲理想。於此，所謂平均粗度（Ra )，係爲以JIS B 060 1 (2 0 0 1 )所規定之平均粗度（Ra )，並可使用觸針式表面 粗度計等來作測定。另外，平均粗度（Ra )之調整，若是 第2載體金屬箔1 1係爲銅箔，則係成爲能夠藉由對於在 形成作爲第2載體金屬箔11之銅箔時的銅電鍍之組成（ 包含添加劑等）或者是條件作調整，而進行之。 接著’如圖12(4)中所示一般，在包含有第1圖案 鍍敷13之第2載體金屬箔11上，層積絕緣層3，而形成 -29- 201246414 層積體22。作爲絕緣層3,係可使用一般之作爲封裝基板 1之絕緣層3所使用者。作爲此種絕緣層3，係可列舉出 環氧系樹脂、聚醯亞胺系樹脂等，例如，亦可將環氧系或 聚醯亞胺系之接著薄片，玻璃環氧或玻璃聚醯亞胺系等之 預浸材，使用熱壓等來進行加熱、加壓而作層積一體化， 來形成之。於此，所謂層積體22，係指如此這般而作了層 積一體化的狀態者之中，層積於包含有第1圖案鍍敷13 之第2載體金屬箔11上者。當在成爲絕緣層3之此些的 樹脂上更進而重疊成爲導體層20之金屬箔並同時進行加 熱、加壓而作了層積一體化的情況時，係亦包含有此導體 層20。又，如同後述一般，當藉由導體層20而形成內層 電路6、或者是形成與導體層20作連接之層間連接5的情 況時，係亦包含有此些之內層電路6或層間連接5。 接著，亦可如圖12(5) 、（6)中所示一般，形成層 間連接孔2 1，並形成層間連接5或內層電路6。層間連接 5，例如，係可使用所謂的正形（Conformal )工法來形成 層間連接孔2 1，之後，再對於此層間連接孔2 1內進行鍍 敷，而形成之。此鍍敷，係可作爲基底鍍敷而附加薄的無 電解銅鍍敷，之後，作爲厚鍍敷，使用無電解銅鍍敷或電 性銅鍍敷、塡孔鍍敷等。爲了將進行蝕刻之導體層20的 厚度變薄而成爲容易形成細微電路，較理想，係在薄的基 底鍍敷之後，形成鍍敷阻劑，並藉由電性銅鍍敷或塡孔鍍 敷來進行厚的鍍敷。內層電路6’例如’係可藉由在進行 了對於層間連接孔21之鍍敷後’經由蝕刻來將不必要部 -30- 201246414 分之導體層20除去，而形成之。 接著，亦可如同圖13(7) 、（8)以及圖14(9)、 (10)中所示一般，在內層電路6或層間連接5之上，進 而形成絕緣層3和導體層20，並與圖12(5) 、（6)時 相同的，以成爲所期望之層數的方式，來形成內層電路6 或外層電路2、7、層間連接5。另外，在本發明中，係有 著將內層電路6和外層電路2、7 —同統稱爲導體電路的 情況。 接著，如圖15(11)中所示一般，在多層金屬箔9之 第2載體金屬箔11和基底金屬箔12之間，將層積體22 與第2載體金屬箔1 1 一同地而從核心基板1 7作物理性剝 離，而分離之。此時，較理想，在多層金屬箔9之第2載 體金屬箔11和基底金屬箔12之間的剝離層（未圖示）， 係被帶走至基底金屬箔12側。藉由此，在將基底金屬箔 1 2作了剝離後之層積體2 2側，由於係露出有第2載體金 屬箔1 1之表面，因此，在後續工程中所進行之對於第2 載體金屬箔1 1的蝕刻，係不會有被剝離層所阻礙的情況 〇 接著，如圖16(12)〜（14)中所示一般，在作分離 而剝離了的層積體22之第2載體金屬箔11上，形成蝕刻 阻劑34，並對於層積體22之第2載體金屬箔1 1進行蝕刻 ’藉由此’來使前述第1圖案鍍敷13露出於絕緣層3之 表面，並形成埋入電路2’或者是在第1圖案鍍敷π上又 或是絕緣層3上，形成立體電路27。又，亦可如圖17( -31 - 201246414 12)〜（14)中所示一般，在作分離而剝離了的層積體22 之第2載體金屬箔11上，進行第2圖案鍍敷14，並在進 行了第2圖案鍍敷之部分以外的載體金屬箔上，形成蝕刻 阻劑，而進行蝕刻，藉由此，來將進行了第2圖案鑪敷14 之部分以及形成有蝕刻阻劑的部分以外之第2載體金屬箔 11，藉由蝕刻而除去，並使第1圖案鍍敷13露出於絕緣 層3之表面，而形成埋入電路2，或者是在第1圖案鍍敷 13上又或是絕緣層3上，形成立體電路27。另外，圖16 (1 2 )〜（1 4 )以及圖1 7 ( 1 2 )〜（14 )，係僅對於如同 圖15(11) —般所分離了的層積體22中之下側的部分作 展示。藉由圖16(12)〜（14)或者是圖17(12)〜（ 14 )之工程，使第1圖案鍍敷13從絕緣層3而露出所形 成的埋入電路2，係能夠形成倒裝晶片連接端子，被形成 在層積體表面之第1圖案鍍敷上的立體電路27,係能夠形 成突塊或柱（pillar )，形成在層積體表面之絕緣層上的 立體電路27,係能夠形成假端子。藉由此，在形成外層電 路2時，由於外層電路2之側面並不會被蝕刻所侵蝕，而 並不會產生基蝕，因此，係能夠形成細微之外層電路2。 又，藉由本發明所形成之外層電路2，由於係成爲被埋入 至絕緣層3中之狀態，因此，不僅是外層電路2之底面， 兩側之側面亦係與絕緣層3相密著’故而’就算是細微電 路，亦能夠確保充分之密著性。又’當作爲第2載體金屬 箱11而使用厚度1 〜5ym之極薄銅箱的情況時’由 於就算是些許之蝕刻量’亦能夠將第2載體金屬箔11除 -32- 201246414 去，因此，被埋入至絕緣層3中並從絕緣層3所露出之外 層電路2的表面，係成爲平坦，藉由將其設爲鋼線接合端 子或者是倒裝晶片連接端子，係能夠確保連接信賴性，而 適於作爲與半導體元件間之連接端子來使用。又，由於係 能夠將與半導體元件間之連接端子，設置在俯視時而與層 間連接5相重疊之位置處的外層電路2處，因此，係能夠 將與半導體元件間之連接端子，設置在層間連接5之正上 方或者是正下方處，而亦能夠與小型化、高密度化作對應 。進而，由於藉由在任意之場所處形成立體電路27，係能 夠形成突塊或柱、假端子等的各種之導體電路的構成，並 且，藉由對於第2載體金屬箔11或第2圖案鍍敷14之厚 度作改變，亦能夠形成爲任意之高度，因此，係能夠和與 各種之半導體元件（未圖示）或其他之封裝基板間的連接 形態作對應。例如，如圖1 8中所示一般，藉由在本發明 之封裝基板1的第1圖案鍍敷13上設置立體電路27並形 成柱，而進行與頂基板之間的連接，就算是並不設置孔洞 (cavity)，亦能夠構成PoP。又，當如圖18中所示一般 ，半導體元件35側之突塊25係成爲週邊配置（在半導體 元件35之周圍將突塊25作並排配置）的情況時，於進行 倒裝晶片連接時，若是將半導體元件35推壓至半導體元 件搭載用封裝基板1側，則半導體元件35之中央部係容 易撓折而變形，但是，經由預先設置假端子（在圖1 8中 ，係爲被形成在絕緣層上之立體電路27 )，由於係能夠將 半導體元件3 5之下面作支撐，因此，係能夠對於變形作 -33- 201246414 抑制。又，若是以將假端子與第1圖案鍍敷或者是層間連 接5作連接的方式來作形成，則亦能夠將從半導體元件35 而來之熱作放熱。因此，係能夠將信賴性提升。另外，所 謂假端子，係爲電性獨立而並不作爲電性電路來起作用者 ，在圖16、圖17中，雖係被形成在絕緣層上，但是，係 亦能夠與被設爲並不會電性地起作用的第1圖案鍍敷或者 是層間連接5作連接。 接著，亦可因應於需要，而形成銲料阻劑4或者是保 護鍍敷8。作爲保護鍍敷8，較理想，係爲一般性地作爲 封裝基板之連接端子的保護鍍敷所使用之鎳鍍敷和金鍍敷 〇 如同上述一般，若依據本發明之封裝基板之製造方法 ，則係能夠形成在與層間連接相重疊的位置處具備有平坦 且細微之埋入電路的封裝基板，而能夠形成適於進行鋼線 接合或者是倒裝晶片連接之封裝基板。又，藉由在任意之 場所處形成立體電路，係能夠形成具備有突塊或柱等之各 種金屬構成的封裝基板。 〔實施例〕 接著，針對本發明之封裝基板的其他製造方法之實施 例作說明，但是，本發明，係並不被限定於本實施例。 (實施例1 ) 首先’如圖10中所示一般，準備了將第1載體金屬 -34- 201246414 箔10和第2載體金屬箔11以及基底金屬箔12依此順序 來作了層積之多層金屬箔9。第1載體金屬箔10，係使用 9ym之銅箔，第2載體金屬箔11’係使用3/zm之極薄 銅箔，基底金屬箔12，係使用18vm之銅箔。在基底金 屬箔12之表面（和第2載體金屬箔1 1之間），係以能夠 作物理性剝離的方式而設置了剝離層（未圖示）。又，在 第2載體金屬箔11之表面（和第1載體金屬箔10之間） ，係預先設置有平均粗度（Ra) 〇.7ym的凹凸。又，在 此凹凸上，亦即是在其與第1載體金屬箔1 〇之間，係以 能夠作物理性剝離的方式而設置了剝離層（未圖示）。在 基底金屬箔12和第2載體金屬箔11之間，以及在第2載. 體金屬箔1 1和第1載體金屬箔1 0之間的剝離層，係均爲 藉由使用Ni 30g/L、Mo 3.0g/L、檸檬酸30g/L之組成 的鍍敷浴來形成金屬氧化物層，而形成之。另外，剝離強 度之調整，係藉由對於電流作調整以調整形成剝離層之金 屬氧化物量，而進行之。此時之剝離強度，在基底金屬箔 12和第2載體金屬箔1 1之間，係爲47N/ m，在第2載 體金屬箔11和第1載體金屬箔10之間，係爲29N/ m » 另外，在進行了加熱、加壓後（將成爲基材16之預浸材 作層積而形成了核心基板1 7後）之剝離強度的變化率， 係爲相對於初期狀態而作了約1 〇 %程度之上升的程度》 在圖10中所示之多層金屬箔9的製作，具體而言係 如同下述一般地而進行。 (1)作爲基底金屬箔12，使用厚度18// m之電解銅 -35- 201246414 箔’並在硫酸30g/L中作60秒的浸漬而進行酸洗淨’之 後再以流水而進行30秒之水洗。 (2) 將洗淨後之電解銅箔作爲陰極’並將施加了氧 化銥塗敷之Ti (鈦）極板作爲陽極，而作爲含有Ni (鎳 )、Mo(鉬）、檸檬酸之鍍敷浴，在硫酸鎳6水合物30g /L、鉬酸鈉2水合物3.0g/L、檸檬酸3鈉2水合物30g /L、pH6.0、液溫度30°C之浴中，於電解銅箔之光澤面 上，以電流密度20A/ dm2來進行5秒鐘之電解處理’而 形成了包含有由鎳和鉬所成之金屬氧化物的剝離層（未圖 示）。 (3) 在形成剝離層（未圖示）之後的表面上，藉由 硫酸銅5水合物200g/L、硫酸100g/L、液溫度40°C之 浴，而將施加有氧化銥塗敷之Ti (鈦）極板作爲陽極，並 藉由電流密度4A/ dm2來進行200秒之電解鍍敷，而形成 厚度3//m之成爲第2載體金屬箔11的金屬層。 (4) 在形成了成爲第2載體金屬箔11之金屬層後的 表面上，使用與上述（2)相同之浴，而藉由電流密度 10A/ dm2來進行10秒之電解處理，而形成含有由鎳和鉬 所成之金屬氧化物的剝離層（未圖示）。 (5 )在形成了剝離層1 3後的表面上，使用與上述（ 3 )相同之浴，而藉由電流密度4A/ dm2來進行600秒之 電解鍍敷，而形成厚度9/zm之成爲第1載體金屬箔1〇的 金屬層。 (6)在與基材16作接觸之面上，藉由硫酸銅鍍敷而 -36- 201246414 形成粒狀之粗化粒子，並施加了鉻酸處理以及矽烷耦合劑 處理。又，對於並不與基材16接觸之面，係施加了鉻酸 處理。 接著，如圖11(1)中所示一般，將多層金屬箔9之 基底金屬箔1 2側和基材1 6作層積，而形成核心基板1 7。 作爲基材16，係使用玻璃環氧之預浸材，並在此預浸材之 上下兩側處重疊多層金屬箔9，而使用熱壓來進行加熱、 加壓並作了層積一體化。 接著，如圖11(2)中所示一般，在多層金屬箔9之 第1載體金屬箔10和第2載體金屬箔11之間，將第1載 體金屬箔1 〇作了物理性剝離。 接著，如圖1 1 ( 3 )中所示一般，在殘留於核心基板 17上之第2載體金屬箔11上，進行了第1圖案鍍敷13» 第1圖案鍍敷13，係在第2載體金屬箔11上’形成感光 性之鍍敷阻劑，之後，使用硫酸銅電鍍而作了形成。 接著，如圖12(4)中所示一般’在包含有第1圖案 鍍敷13之第2載體金屬箔11上’作爲絕緣層3和導體層 20，而層積銅箔（12//m)並形成了層積體22°作爲絕緣 層3，係將環氧系之接著薄片，使用熱壓而進行加熱、加 壓並作層積一體化，而形成之。 接著，如圖12(5) 、（6)中所示一般’形成了層間 連接5或內層電路6。層間連接5’係在使用正形（ Conformal)工法而形成了層間連接孔21之後’對於此層 間連接孔2 1內進行鑛敷’而形成之。此鍍敷’係作爲基 -37- 201246414 底鍍敷而進行薄的無電解銅鍍敷’之後’形成感光性之鍍 敷阻劑，再作爲厚鍍敷而進行了硫酸銅電鍍。之後’藉由 以蝕刻來將不必要部分之導體層20除去，而形成了內層 電路6。 接著，如圖13(7) 、（8)以及圖14(9) 、（10) 中所示一般，在內層電路6或層間連接5之上’進而形成 絕緣層3和導體層20’並形成內層電路6或外層電路2、 7、層間連接5，而形成了具備有4層的導體層20之層積 體22 〇 接著，如圖15(11)中所示一般，在多層金屬箔9之 第2載體金屬箔11和基底金屬箔12之間，將層積體22 與第2載體金屬箔1 1 一同地而從核心基板1 7作物理性剝 離，而分離之。 接著，如圖16(12)〜（14)中所示一般，在作分離 而剝離了的層積體22之第2載體金屬箔11上，形成蝕刻 阻劑1 4，並對於層積體2 2之第2載體金屬箔1 1進行蝕刻 ，藉由此，來使前述第1圖案鍍敷13露出於前述絕緣層3 之表面，並形成了埋入電路2，並且，在第1圖案鍍敷13 上或是絕緣層3上，形成了立體電路27。另外，使第1圖 案鍍敷13從絕緣層3而露出所形成的埋入電路2，係作爲 倒裝晶片連接端子，被形成在層積體表面之第1圖案鍍敷 上的立體電路27’係作爲突塊，形成在層積體表面之絕緣 層上的立體電路27，係作爲假端子。 接著’形成感光性之銲料阻劑，之後，作爲保護鍍敷 -38- 201246414 ，而進行無電解鎳鍍敷和無電解金鍍敷，而形成了封裝基 板。 (實施例2) 對於在基底金屬箔12和第2載體金屬箔11之間以及 在第2載體金屬箔1 1和第1載體金屬箔1 0之間的剝離強 度，藉由均爲使用具備有Ni (鎳）30g/ L、Mo (鉬） 3.0g/L、檸檬酸30g/L之組成的鍍敷浴來形成金屬氧化 物層，並對此時之電流作改變’以對於形成剝離層之金屬 氧化物量作調整，而使剝離強度作改變。此時之剝離強度 ，在基底金屬箔12和第2載體金屬箔11之間，係爲23N /m，在第2載體金屬箔11和第1載體金屬箔10之間， 係爲18N/m。除此之外，係與實施例1相同的，而製作 了封裝基板。 (實施例3 ) 對於在基底金屬箔12和第2載體金屬箔11之間以及 在第2載體金屬箔11和第1載體金屬箔10之間的剝離強 度，藉由均爲使用具備有Ni (鎳）30g / L、Mo (鉬） 3.0g/ L、檸檬酸30g/ L之組成的鍍敷浴來形成金屬氧化 物層，並對此時之電流作改變，以對於形成剝離層之金屬 氧化物量作調整，而使剝離強度作改變。此時之剝離強度 ，在基底金屬箔12和第2載體金屬箔11之間，係爲15N /m，在第2載體金屬箔11和第1載體金屬箔10之間， -39- 201246414 係爲2N/m。除此之外，係與實施例1相同的，而製作了 封裝基板。 (實施例4) 對於在基底金屬箔12和第2載體金屬箔11之間以及 在第2載體金屬箔11和第1載體金屬箔10之間的剝離強 度，藉由均爲使用具備有Ni (鎳）30g/ L、Mo (鉬） 3.0g/L、檸檬酸30g/L之組成的鍍敷浴來形成金屬氧化 物層，並對此時之電流作改變，以對於形成剝離層之金屬 氧化物fi作調整，而使剝離強度作改變。此時之剝離強度 ，在基底金屬箔12和第2載體金屬箔11之間，係爲68N /m，在第2載體金屬箔11和第1載體金屬箔10之間， 係爲48N/ m。 使用上述所準備之多層金屬箔9，代替實施例1之圖 16(12)〜（14)中所示之工程，而如同圖17(12)〜（ 14)中所示一般，在作分離而剝離了的層積體22之第2 載體金屬箔Π上，進行第2圖案鍍敷14，並在進行了第 2圖案鍍敷之部分以外的載體金屬箔上，形成蝕刻阻劑34 ，而進行蝕刻，藉由此，來將進行了第2圖案鍍敷14之 部分以及形成有蝕刻阻劑的部分以外之第2載體金屬箔1 1 ，藉由蝕刻而除去，並使第1圖案鍍敷13露出於絕緣層3 之表面，而形成埋入電路2,並且在第1圖案鍍敷13上或 是絕緣層3上，形成立體電路27。另外，使第1圖案鍍敷 1 3從絕緣層3而露出所形成的埋入電路2，係作爲倒裝晶 -40- 201246414 片連接端子，被形成在層積體表面之第1圖案銨敷上的立 體電路27’係作爲柱，形成在層積體表面之絕緣層上的立 體電路27，係作爲假端子。除了此工程之外，係與實施例 1相同的，而製作了封裝基板》 (實施例5) 對於在基底金屬箔12和第2載體金屬箔11之間以及 在第2載體金屬箔Π和第1載體金屬箔1 0之間的剝離強 度，藉由均爲使用具備有Ni (鎳）30g/ L、Mo (鉬） 3.0g/L、檸檬酸30g/L之組成的鍍敷浴來形成金屬氧化 物層，並對此時之電流作改變，以對於形成剝離層之金屬 氧化物量作調整，而使剝離強度作改變。此時之剝離強度 ，在基底金屬箔12和第2載體金屬箔11之間，係爲43N /m，在第2載體金屬箔11和第1載體金屬箔10之間， 係爲28N/ m。除此之外，係與實施例4相同的，而製作 了封裝基板。 (實施例6) 對於在基底金屬箔12和第2載體金屬箔11之間以及 在第2載體金屬箔1 1和第1載體金屬箔1 〇之間的剝離強 度，藉由均爲使用具備有Ni (鎳）30g/ L、Mo (鉬） 3.0g/L、檸檬酸30g/L之組成的鍍敷浴來形成金屬氧化 物層，並對此時之電流作改變，以對於形成剝離層之金屬 氧化物量作調整，而使剝離強度作改變。此時之剝離強度 -41 - 201246414 ’在基底金屬箔12和第2載體金屬箔11之間’係爲22N /m’在第2載體金屬箔11和第1載體金屬箔1〇之間’ 係爲4N/ m。除此之外，係與實施例4相同的’而製作了 封裝基板。 於表1中，係針對實施例1〜6，而對於被埋入至絕緣 層3中所形成之外層電路2的最終狀態、第1載體金屬箔 1 0和第2載體金屬箔1 1之間的剝離強度、第2載體金屬 箔11和基底金屬箱12之間的剝離強度、在進行處理時之 載體金屬箔的剝落之有無，來作了展示。在實施例1〜6 之任一者中，均係能夠形成線/空間爲ΙΟ/zm/lOjczm之 程度的細微之外層電路2(表1中之〇，係代表並不存在 有基蝕）。又，在對於剖面作了觀察後，其結果，係均未 發生有基蝕。進而，根據剖面之觀察結果，可以得知，由 於第2載體金屬箱11係使用了 3/zm之極薄銅箱，因此， 僅藉由些許之餓刻量便能夠均一地作了除去，而外層電路 2之表面的凹凸係爲平坦。又，不論是實施例1〜6中之何 者，在製造工程的處理中’在第1載體金屬箔1〇和第2 載體金屬箔Π之間、以及第2載體金屬箔U和基底金屬 箔12之間，均並未有剝落的情況（表1之〇，係代表不 存在有剝落）。又’在將第1載體金屬箱1〇和第2載體 金屬箔1 1之間作剝離時’係並沒有使第2載體金屬箱i i 和基底金屬箔1 2之間作剝離的情況。 -42- 201246414 〔表1〕 項目 線/空間（ym/em) 剝離強度（N/m) 處理時之 金屬箔的 剝落 10/10 15/15 20/20 第1載體金屬箔/ 第2載體金屬箔 第2載體金屬箔 /基底金屬箔 實施例1 〇 〇 〇 29 47 〇 實施例2 〇 〇 〇 18 23 〇 實施例3 〇 〇 〇 2 15 〇 實施例4 〇 〇 〇 48 68 〇 實施例5 〇 〇 〇 28 43 〇 實施例6 〇 〇 〇 4 22 〇 如圖1 8中所示一般，對於藉由實施例4所製作了的 封裝基板（圖17(14))之埋入電路2，而將半導體元件 35之突塊25作推壓，並使用銲錫（未圖示）來作了倒裝 晶片連接。半導體元件35,其之突塊25雖係被作了週邊 配置，但是，由於係將半導體元件35之下面藉由成爲假 端子之立體電路27來作了支撐，因此，在半導體元件35 處係並未發生有撓折的情況。 在加熱、加壓前（將成爲基材16之預浸材作層積並 形成核心基板1 7之前）之初期的剝離強度（N/ m )之測 定，係製作出裁切爲10mm寬幅之多層金屬箔的樣本，並 使用添希隆（音譯）RTM-100CORIENTEC股份有限公司 製，商品名，「添希隆」係爲登記商標），而準據於JIS Z 023 7之90度拉扯剝離法，來在室溫（25 °C )下，首先 ，將第1載體金屬箔朝向90度方向而以每分鐘3 0 0mm之 速度而作拉扯剝離並進行測定，接著，將第2載體金屬箔 朝向90度方向而以每分鐘3 00mm之速度作拉扯剝離並進 -43- 201246414 行測定。又，針對進行了加熱、加壓後（將成爲基材16 之預浸材作層積而形成了核心基板1 7後）之剝離強度’ 亦與初期之剝離強度同樣的而進行測定，並求取出相對於 初期狀態之變化率。另外，在將多層金屬箔9和成爲基材 16之玻璃環氧預浸材作層積並形成核心基板17時的加熱 、加壓條件，係使用真空沖壓，並設爲壓力3MPa，溫度 175°C，保持時間1.5hr (小時）。 以下，藉由實施例來對本發明作具體說明，但是，本 發明係並不被限定於此些之實施例。 (實施例7 ) 藉由與實施例1相同之方法，而至作了具備有埋入電 路之倒裝晶片端子的封裝基板。於此，在被形成於封裝基 板上之銲料阻劑處，係被設置有開口，在此開口內，係被 配置有線/空間爲20 // m/ 20 μ m ( 40 // m節距）的成爲 倒裝晶片連接端子之埋入電路。經由銲料阻劑之開口所規 定出的倒裝晶片連接端子之長邊方向的尺寸（倒裝晶片連 接端子之長度），係爲約1〇〇 Am。 接著，在成爲倒裝晶片連接端子之埋入電路上，經由 印刷銲錫糊並作回焊，而形成預備銲錫。在預備銲錫用之 銲錫糊中，係使用Sn (錫）-Ag (銀）-Cu (銅）系之 ECO SOLDER M705 (千住金屬工業股份有限公司製，商品 名，ECOSOLDER係爲登記商標），在回焊中，係使用紅 外線回焊裝置，而以峰値溫度2 6 0 °C之條件來進行之》 -44- 201246414 接著，施加切斷加工，而設爲封裝尺寸。此 斷加工之封裝基板，係如圖2中所示一般，具備 3、和以使上面露出於此絕緣層3之表面處的方 之埋入電路2、和被設置在絕緣層3上以及埋入 之銲料阻劑4，位置在被設置於此銲料阻劑4處 內的埋入電路2,係形成倒裝晶片連接端子26» 倒裝晶片連接端子26作被覆之預備銲錫19的厚 3〜5;zm»於此，銲錫的厚度，係使用身爲非接 定機之HISOMET( UNION光學股份有限公司製 ，HISOMET乃爲登記商標），而在預備銲錫19 後，對於銲料阻劑和倒裝晶片連接端子26之間 測定，而測定出來。 如圖9中所示一般，在製作了封裝基板1後 體元件1 5藉由倒裝晶片連接而作了搭載。倒裝 ，係以使封裝基板1上之倒裝晶片連接端子26 元件15之突塊25 (係爲在銅柱上形成有Sn (錫 量％人§ (銀）-0.5質量％^ (銅）銲錫者，並爲節 、高度25 m )相對向的方式，而作了對位，之 超音波倒裝晶片接合機SH-50MP(ALTECS股份 ，製品名）來進行了倒裝晶片連接。倒裝晶片連 條件，係一面倂用有超音波，一面升溫至2 3 0 °C 單位突塊50g之加壓，而作了 4秒鐘之保持。之 導體元件15之突塊25形成面和封裝基板丨之具 晶片連接端子26的絕緣層3之間，塡充下部塡; 進行了切 有絕緣層 式所設置 電路2上 之開口 3 1 又，將此 度，係爲 觸階差測 ，商品名 之形成前 的階差作 ，將半導 晶片連接 和半導體 )·3·0 質 距 40 // m 後，使用 有限公司 接之壓著 並進行每 後，在半 備有倒裝 才劑2 3， -45- 201246414 而得到半導體封裝24。 (實施例8) 將倒裝晶片連接端子作被覆之預備銲錫的厚度，係爲 7〜10/zm。除此之外，係與實施例7相同的，而得到了第 10電路基板以及半導體封裝。 (實施例9) 將倒裝晶片連接端子作被覆之預備銲錫的厚度，係爲 17〜20ym。除此之外，係與實施例7相同的，而得到了 封裝基板以及半導體封裝。 〔比較例1〕 將倒裝晶片連接端子作被覆之預備銲錫的厚度，係爲 1〜2 y m。除此之外，係與實施例7相同的，而得到了封 裝基板以及半導體封裝。 〔參考例1〕 將倒裝晶片連接端子作被覆之預備銲錫的厚度’係爲 25〜28#m»除此之外，係與實施例7相同的，而得到了 封裝基板以及半導體封裝。 (實施例1 〇 ) 與實施例7相同的’在成爲倒裝晶片連接端子之埋入 -46- 201246414 電路上，形成了預備銲錫。於此，如圖5中所示一般，在 銲料阻劑4處，係被設置有開口 3 1，在此開口 3 1內，係 被配置有成爲倒裝晶片連接端子26之埋入電路2。又，在 包含倒裝晶片連接端子26之埋入電路2的底面處，係被 連接有通孔1 8。之後，係與實施例7相同的，而形成了封 裝基板以及半導體封裝。 (實施例1 1 ) 藉由與實施例4相同之方法，而如圖17(12)〜（14 )中所示一般，在第2載體金屬箔11上進行第2圖案鍍 敷14，並在埋入電路之成爲倒裝晶片連接端子的場所之一 部份處，形成了凸形狀（立體電路）。又，係形成銲料阻 劑，並形成作爲保護鍍敷之鎳/金鍍敷（鎳鍍敷和其上之 金鍍敷）。於此，如圖6中所示一般，在銲料阻劑4處， 係被設置有開口 3 1，在此開口 31內，係被配置有成爲倒 裝晶片連接端子26之埋入電路2。又，在倒裝晶片連接端 子26之長邊方向的一部份處’係被形成有凸形狀27，此 凸形狀27之高度，係爲5 μ m程度。凸形狀27之範圍， 係爲倒裝晶片連接端子26之短邊方向的尺寸之1 〇〇%、倒 裝晶片連接端子26之長邊方向的尺寸之30%程度。之後 ，係與實施例7相同的’而形成了封裝基板以及半導體封 裝。 (實施例1 2 ) -47- 201246414 與實施例1相同的，而製作了具備有埋入電路之倒裝 晶片端子的封裝基板。之後，形成蝕刻阻劑，並以使露出 於上面之埋入電路的上面之一部份成爲較絕緣層之表面而 更加凹陷，其他部分則係照原樣而殘留的方式，來進行蝕 刻，藉由此，而形成了凹陷形狀。之後，係形成了銲料阻 劑、並形成作爲保護鍍敷之鎳/金鍍敷（鎳鍍敷和其上之 金鍍敷）。於此，如圖7中所示一般，在銲料阻劑4處， 係被設置有開口 31，在此開口 31內，係被配置有成爲倒 裝晶片連接端子26之埋入電路2。又，在倒裝晶片連接端 子26之長邊方向的一部份處，係被形成有凹陷形狀28， 此凹陷形狀28之深度，係爲5 // m程度。凹陷形狀28之 範圍，係爲倒裝晶片連接端子26之短邊方向的尺寸之 100%、倒裝晶片連接端子26之長邊方向的尺寸之30%程 度。之後，係與實施例7相同的，而形成了封裝基板以及 半導體封裝。 (實施例1 3 ) 與實施例7相同的，而製作了具備有埋入電路之倒裝 晶片端子的封裝基板。於此，如圖3中所示一般，在銲料 阻劑4處，係被設置有開口 3 1，在此開口 31內，係被配 置有成爲倒裝晶片連接端子26之埋入電路2。又，倒裝晶 片連接端子26之前端，係被形成在銲料阻劑4之開口 3 1 內。之後，係與實施例7相同的，而形成了封裝基板以及 半導體封裝。 -48- 201246414 (實施例1 4 ) 與實施例7相同的，而製作了具備有埋入電路之倒裝 晶片端子的封裝基板。於此，如圖4中所示一般，在銲料 阻劑4處，係被設置有開口 3 1，在此開口 3 1內，係被配 置有成爲倒裝晶片連接端子26之埋入電路2。又，係設置 有在倒裝晶片連接端子26之長邊方向的兩側或者是單側 處而作了延長之埋入電路2。之後，係與實施例7相同的 ，而形成了封裝基板以及半導體封裝。 (實施例1 5 ) 與實施例7相同的，而製作了具備有埋入電路之倒裝 晶片端子的封裝基板。於此，如圖8中所示一般，在銲料 阻劑4處，係被設置有開口 3 1，在此開口 31內，係被配 置有成爲倒裝晶片連接端子26之埋入電路2。又，倒裝晶 片連接端子26之長邊方向的一部份，係形成有在短邊方 向（寬幅方向）上作了擴張之部分3 3。亦即是，倒裝晶片 連接端子26，係形成有部分性地在短邊方向（寬幅方向） 上作了擴張的部分3 3。之後，係與實施例7相同的，而形 成了封裝基板以及半導體封裝。 〔比較例2〕 與實施例7相同的，而製作了具備有埋入電路之倒裝 晶片端子的封裝基板。於此，如圖16(14)中所示一般， -49- 201246414 在埋入電路2之被配置有倒裝晶片連接端子之面的相反面 處，係被配置有與圖1中所示者相同之由凸狀電路所成的 電路圖案（外層電路7)。 接著，在此由凸狀電路所成之電路圖案（外層電路7 )上，形成銲料阻劑，並形成作爲保護鍍敷之鎳/金鍍敷 (鎳鑛敷和其上之金鍍敷）。於此，在銲料阻劑處，係被 設置有開口，在此開口內，係被配置有線/空間爲2 0 y m /20//m( 40 節距）的成爲倒裝晶片連接端子之由凸 狀電路所成的電路圖案。 接著，在成爲倒裝晶片連接端子之由凸狀電路所成的 電路圖案（.外層電路7 )上，經由印刷銲錫糊並作回焊， 而形成預備銲錫。在預備銲錫用之銲錫糊中，係使用Sn (錫）-Ag (銀）-Cu (銅）系之 ECOSOLDER M705 (千 住金屬工業股份有限公司製，商品名，ECOSOLDER係爲 登記商標），在回焊中，係使用紅外線回焊裝置，而以峰 値溫度260 °C之條件來進行之。 接著，施加切斷加工，而設爲封裝尺寸。此封裝基板 ，係如圖1中所示一般，具備有絕緣層3、和被設置在此 絕緣層3之表面處的由凸狀電路32所成之電路圖案、和 被設置在絕緣層3上以及由凸狀電路32所成之電路圖案 上的銲料阻劑4，位置在被設置於此銲料阻劑4處之開口 31內的由凸狀電路32所成之電路圖案，係形成倒裝晶片 連接端子26。又，將此倒裝晶片連接端子26作被覆之預 備銲錫1 9的厚度，係爲3〜5 /z m。之後，與實施例7相 -50- 201246414 同的，而得到了半導體封裝。 〔比較例3〕 將倒裝晶片連接端子作被覆之預備銲錫的厚度，係爲 1 7〜20 μ m °除此之外，係與比較例3相同的，而得到了 封裝基板以及半導體封裝。 於表2中，針對實施例7〜15、參考例1、比較例1〜 3之封裝基板，對於倒裝晶片連接端子之剖面形狀、銲錫 厚度、銲錫架橋之有無作了調查，並對於結果作展示。又 ’針對實施例7〜15、參考例1以及比較例1〜3之半導體 封裝’係對於銲錫塡料之狀態作了調查，並對於結果作展 不。 〔表2〕 項目 倒裝晶片 連接端子 銲錫厚度 (Aim) 電路圖案之 剖面形狀 婷錫架橋 之有無 銲錫塡料 之狀態 實施例7 埋入電路 3〜5 略矩形 -fnT- m 良好 實施例8 7〜10 Μ II 實施例9 17〜20 II " 比較例1 1〜2 Μ 不良 參考例1 25〜2 8 有 " 實施例10 3〜5 無 良好 實施例11 8〜1 0 II 實施例12 1 3〜5 " 實施例13 J 3〜5 " 實施例141 3〜5 ” 實施例15 3〜5 II 比較例2 凸狀電路 3〜5 存在有基蝕 不良 比較例3 II 1 7 〜20 ” 有 良好 -51 - 201246414 根據倒裝晶片連接端子之剖面形狀的觀察結果’可以 得知，在實施例7〜1 5中，倒裝晶片連接端子之側面以及 底面係被埋入至絕緣層中並作密著，剖面形狀係爲略矩形 ，且並未發現到基蝕。另一方面，在比較例2、3中，由 於係身爲凸狀電路，因此，係僅有倒裝晶片連接端子之底 面爲與絕緣層相密著。又，在倒裝晶片連接端子之剖面形 狀中，係觀察到有基蝕，在最爲狹窄的場所處，係相對於 頂部寬幅（表面側之寬幅）而成爲不滿一半之寬幅。 根據銲錫厚度之測定結果，在實施例7〜15中，銲錫 厚度係爲3〜20/zm，又，根據銲錫架橋之確認結果，可 以得知，在此銲錫厚度之範圍內，係並不存在有銲錫架橋 之發生。另一方面，在比較例1中，銲錫厚度係爲1〜2/zm 而爲薄，而並不存在有銲錫架橋之發生》在參考例1中， 銲錫厚度係爲25〜28/zm而爲厚，在相鄰接之倒裝晶片連 接端子間，係發生了銲錫架橋。在比較例3中，銲錫厚度 雖係爲17〜20"m，但是，由於其係爲凸狀電路，因此， 銲錫係繞入至倒裝晶片連接端子之側面處，而發生了銲錫 架橋。 根據半導體封裝之銲錫塡料的確認結果，可以得知， 在實施例7〜15、參考例1以及比較例3中，在與半導體 元件之突塊間所被形成的靜錫塡料，係在半導體元件之突 塊以及封裝基板之倒裝晶片連接端子的兩者之間而使銲錫 作了浸濕擴廣’其狀況係爲良好》另一方面，在比較例1 以及2中，在半導體元件之突塊或者是封裝基板之倒裝晶 -52- 201246414 片連接端子的一部份處，係存在有銲錫之浸濕擴廣並不充 分的場所，銲錫塡料之形成係並不充分。 倒裝晶片連接端子之剖面形狀，係藉由製作出微切片 ，並藉由金屬顯微鏡來對於剖面作觀察，而得之。倒裝晶 片連接端子上之銲錫的厚度，係使用身爲非接觸階差測定 機之HISOMET ( UNION光學股份有限公司製，商品名 HISOMET乃爲登記商標），而在預備銲錫之形成前後， 對於銲料阻劑和倒裝晶片連接端子之間的階差作測定，而 測定出來。銲錫架橋之有無以及銲錫塡料之狀態，係藉由 使用實體顯微鏡來以1 〇倍而進行觀察，而作了確認。 【圖式簡單說明】 〔圖1〕先前技術之封裝基板的倒裝晶片連接端子近 旁之（a)平面圖、（b)A-A’剖面圖、（c)B-B’剖面圖 〇 〔圖2〕本發明之封裝基板的倒裝晶片連接端子近旁 之（a)平面圖、（b)A-A’剖面圖、（c)B-B，剖面圖。 〔圖3〕本發明之封裝基板的倒裝晶片連接端子近旁 之（a)平面圖以及（b) A-A’剖面圖》 〔圖4〕本發明之封裝基板的倒裝晶片連接端子近旁 之（a)平面圖、（b)A-A’剖面圖、（C)B-B，剖面圖。 〔圖5〕本發明之封裝基板的倒裝晶片連接端子近旁 之（a)平面圖以及（b) A-A，剖面圖。 〔圖6〕本發明之封裝基板的倒裝晶片連接端子近旁 -53- 201246414 之（a)平面圖以及（b) A-A’剖面圖。 〔圖7〕本發明之封裝基板的倒裝晶片連接端子近旁 之（a)平面圖以及（b) A-A’剖面圖。 〔圖8〕本發明之封裝基板的倒裝晶片連接端子近旁 之（a)平面圖、（b)A-A’剖面圖、（c)B-B’剖面圖。 〔圖9〕本發明之封裝的倒裝晶片連接端子近旁之剖 面圖。 〔圖10〕在本發明中所使用之多層金屬箔的剖面圖。 〔圖11〕對於本發明之封裝基板的製造方法之一部份 作展示的流程圖。 〔圖12〕對於本發明之封裝基板的製造方法之一部份 作展示的流程圖。 〔圖13〕對於本發明之封裝基板的製造方法之一部份 作展示的流程圖。 〔圖14〕對於本發明之封裝基板的製造方法之一部份 作展示的流程圖。 〔圖15〕對於本發明之封裝基板的製造方法之一部份 作展示的流程圖。 〔圖16〕對於本發明之封裝基板的製造方法之一部份 作展示的流程圖。 〔圖17〕對於本發明之封裝基板的製造方法之一部份 作展示的流程圖。 〔圖18〕使用本發明之封裝基板之製造方法所製作出 的半導體封裝之剖面圖 -54- 201246414 【主要元件符號說明】 1:半導體元件搭載用封裝基板或封裝基板或者是第 1 〇電路基板 2:外層電路或埋入電路 3 :絕緣層 4 :銲料阻劑 5 :層間連接 6 :內層電路 7 :外層電路 8 :保護鑛.敷 9 :多層金屬箔 10 :第1載體金屬箔 1 1 :第2載體金屬箔 12 :基底金屬箔 13 :第1圖案鍍敷 14 :第2圖案鍍敷 1 5 :半導體元件 16 :基材 1 7 :核心基板 1 8 :通孔 1 9 :預備銲錫 20 :導體層 21 =層間連接孔 -55- 201246414 22 :層積體 23 :下塡充材 24 :半導體封裝 25 :(半導體元件側之）突塊 26 :倒裝晶片連接端子 27:凸形狀或立體電路 28 :凹陷形狀 2 9 :密封材 3 1 :(銲料阻劑之）開口 3 2 :凸狀電路 3 3 :在短邊方向上被作.了擴張的部分 3 4 :蝕刻阻劑 3 5 :半導體元件 -56-[Technical Field] The present invention relates to a method of manufacturing a package substrate for mounting a semiconductor element capable of high density, a package substrate for mounting a semiconductor element, and a semiconductor package. More specifically, A method of manufacturing a semiconductor element mounting package substrate including a flip chip connection terminal connected to a semiconductor element having a bump, a package substrate for mounting a semiconductor element, and a semiconductor package are provided. [Prior Art] A method of electrically connecting a connection terminal of a semiconductor device and a package substrate for mounting a semiconductor element (hereinafter, a case where a "package substrate for semiconductor element mounting" is referred to as a "package substrate") is used. There is a flip chip connection method. In this flip chip connection, in order to form a good solder paste between the bump and the bump of the semiconductor element, a plurality of solder pastes are used to form a preliminary solder on the flip chip connection terminal of the package substrate, and the solder is prepared therethrough. And the solder which is formed at the bump of the semiconductor element to ensure the amount of solder and to connect with the bump provided at the semiconductor element. On the other hand, with the miniaturization or high density of electronic components, there is a need to arrange the connection terminals with semiconductor elements at a high density, and the miniaturization of flip chip connection terminals is required. . When the flip chip connection terminal is made fine, the area of the contact terminal on which the preliminary solder is formed is reduced, so that the amount of the preliminary solder formed on the flip chip connection terminal is also reduced, and as a result, Half-5-201246414 The formation of solder paste formed between the bumps of the conductor elements is insufficient, and there is a problem that the connection reliability is lowered. Further, if it is desired to form a preliminary solder for a sufficient amount of connection to the semiconductor element on the fine flip chip connection terminal, as shown in FIG. 1, generally, in the general method, The flip chip connection terminal 26 is formed in a convex shape with respect to the surface of the package substrate, and therefore, the preliminary solder 19 is wound around the side of the flip chip connection terminal 26, and has a reverse connection with the adjacent one. There is a problem in that a bridge of the preliminary solder 19 is generated between the wafer connection terminals 26. That is, even if the preliminary solder 19 is supplied as the solder for forming the flip chip connection terminal 26, a considerable proportion of the solder covers the side of the flip chip connection terminal 26 and is consumed. The ratio of the ready solder used to form the solder paste required for the connection is reduced, and not only is there a bridge between the adjacent flip chip connection terminals 26 Happening. As a method for improving such a problem, a method of forming a wiring pattern at a region which becomes a flip chip connection terminal on a package substrate to be long so as to increase the amount of solder in this region is disclosed (Patent Document 1). Or the width of the wiring pattern of the region to be the flip chip connection terminal is partially set to a wider width than the other regions, thereby preparing the flip chip connection terminal A method of increasing the amount of solder (Patent Document 2). [PRIOR ART DOCUMENT] [Patent Document] -6 - 201246414 [Patent Document 1] JP-A-2002-329744 (Patent Document 2) JP-A-2005-101137 SUMMARY OF INVENTION [Problems to be Solved by the Invention] According to the methods of Patent Documents 1 and 2 described above, the amount of preliminary solder on the flip chip connection terminal for connection to the semiconductor element can be secured to some extent. However, as shown in FIG. 1, the circuit pattern for forming the flip chip connection terminal 26 is a circuit pattern which is formed in a convex shape from the surface of the package substrate i (hereinafter, also referred to as a "convex circuit"). In other words, the surface of the insulating layer 3 of the package substrate 1 is in close contact with the bottom surface of the convex circuit 32. Further, since the convex circuit 32 is generally formed by a method of uranium engraving such as a semi-aggregation method, a so-called base etch (UNDERCUT) is generated, and as a result, a circuit pattern is formed. The width is narrower than the top (surface side) and on the way in the thickness direction or at the bottom (bottom side). Therefore, if the flip chip connection terminal 26 is made fine, the adhesion area between the flip chip connection terminal 26 and the insulating layer 3 therebelow is reduced, or the width of the circuit pattern is reduced. By lowering the adhesion, even if a little external force is applied only when flip chip bonding is performed, there is a possibility that peeling of the flip chip connection terminal 26 occurs. The present invention has been made in view of the above-described problems, and an object of the present invention is to provide a 201246414 flip chip connection terminal capable of ensuring adhesion even fine, and having a bump capable of being bonded to a semiconductor element. In the flip chip connection, the flip chip connection terminal having the necessary amount of solder is required, and the semiconductor element mounting package substrate which is excellent in reliability and which is excellent in reliability can be manufactured. A method, a package substrate for mounting a semiconductor element, and a semiconductor package. [Means for Solving the Problem] The present invention relates to the following invention. 1. A method of manufacturing a package substrate for mounting a semiconductor element, comprising: laminating a plurality of metal foils in which a first carrier metal foil, a second carrier metal foil, and a base metal foil are laminated in this order, and The base metal foil side of the multilayer metal foil and the substrate are laminated to form a core substrate; and the first carrier metal foil crop is interposed between the first carrier metal foil and the second carrier metal foil of the multilayer metal foil a process of rational stripping; and performing a first pattern plating on the second carrier metal foil of the core substrate; and forming an insulating layer and a conductor on the second carrier metal foil including the first pattern plating The circuit and the interlayer connection are formed to form a laminate; and the laminate and the second carrier metal foil are physically separated from the core substrate between the second carrier metal foil and the base metal foil of the multilayer metal foil a process of separating and separating the substrate; and forming an etching resist on the second carrier metal foil of the laminate which has been peeled off, and etching the first pattern, thereby plating the first pattern from the layer The process of embedding the insulating layer on the surface of the body to form a buried circuit, or forming a three-dimensional circuit on the first pattern plating on the surface of the laminated body, or the insulating layer on the surface of the laminated layer -8 - 201246414 The process of forming a three-dimensional circuit is either a process of forming a concave shape on the first pattern plating on the surface of the laminate. 2.  A method of manufacturing a package substrate for mounting a semiconductor element, characterized in that a multilayer metal foil prepared by laminating a first carrier metal case, a second carrier metal foil, and a base metal foil in this order is provided and The base metal foil side of the multilayer metal foil and the substrate are laminated to form a core substrate; and the first carrier metal foil crop is 'between the first carrier metal foil and the second carrier metal foil of the multilayer metal foil a process of rational stripping: a process of performing a first pattern plating on a second carrier metal foil of the core substrate; and forming an insulating layer and a conductor on the second carrier metal foil including the first pattern plating a circuit for forming a laminate between the circuit and the interlayer connection; and physically forming the laminate and the second carrier metal foil together from the core substrate between the second carrier metal foil of the multilayer metal foil and the base metal foil a process of separating and separating; and performing a second pattern plating on the second carrier metal foil of the laminate which has been peeled off; and a portion where the second pattern plating is performed An etching resist is formed on the second carrier metal foil and etched, and the second carrier metal foil other than the portion where the second pattern is plated and the portion where the etching resist is formed is removed by etching. Thereby, the first pattern plating is exposed from the insulating layer on the surface of the laminate to form a buried circuit, or a three-dimensional circuit is formed on the first pattern of the surface of the laminate: C-process Or forming a three-dimensional circuit on the insulating layer on the surface of the laminate; or engineering or forming a concave shape on the first pattern plating on the surface of the laminate. -9- 201246414 3.  The method for producing a package substrate for mounting a semiconductor device according to the first aspect, wherein the second carrier metal foil including the first pattern plating is formed by forming an insulator, a conductor circuit, and an interlayer connection to form a layer. The process of the integrated body and the process of physically separating and separating the laminate and the second carrier metal foil from the core substrate between the second carrier metal foil of the multilayer metal foil and the base metal foil. Between the projects, there are: the construction of the insulating layer and the conductor circuit forming the desired number of layers.  The method for producing a package substrate for mounting a semiconductor element according to any one of the first aspect, wherein the first pattern plating is exposed from the insulating layer on the surface of the laminate to form a buried circuit. Forming a flip chip connection terminal, in the process of forming a three-dimensional circuit on the first pattern plating on the surface of the laminate, forming a pillar or a part of the long side direction of the flip chip connection terminal Forming a convex shape, in the process of forming a three-dimensional circuit on the insulating layer on the surface of the laminated body, forming a dummy terminal 〇 5.  A package substrate for semiconductor element mounting, which is a package substrate for mounting a semiconductor device, which is manufactured by the method for manufacturing a package substrate for mounting a semiconductor device according to any one of the first to fourth aspects, wherein Provided with: an insulating layer; and a buried circuit provided to expose the upper surface to the surface of the insulating layer; and a solder resist disposed on the insulating layer and buried in the circuit, disposed thereon The buried circuit in the opening of the solder resist forms a flip chip connection terminal, and the flip chip connection terminal 'is covered by a preliminary solder having a thickness of 3 μm or more. -10- 201246414 6.  The package substrate for mounting a semiconductor element according to the item 5, wherein a through hole is connected to a bottom surface of the buried circuit in which the flip chip connection terminal is formed. 7.  The semiconductor element mounting package substrate according to the fifth aspect or the sixth aspect, wherein a part of the longitudinal direction of the flip chip connection terminal is formed in a convex shape. 8.  The package substrate for mounting a semiconductor element according to any one of the items 5 to 7, wherein a portion of the flip chip connection terminal in the longitudinal direction is formed in a recessed shape. 9.  The package substrate for mounting a semiconductor element according to any one of the items 5 to 8, wherein the front end of the flip chip connection terminal is disposed in the opening of the solder resist. 10.  The package substrate for mounting a semiconductor element according to any one of the items of the present invention, wherein the package substrate for mounting the semiconductor element is provided on both sides or one side in the longitudinal direction of the flip chip connection terminal. Part of the buried circuit. 11.  The package substrate for mounting a semiconductor device according to any one of the items 5 to 10, wherein a part of the flip chip connection terminal is expanded in a short side direction. 12.  A semiconductor package in which a semiconductor device is mounted on a flip chip connection terminal of a package substrate for mounting a semiconductor element according to any one of the items 5 to 11 by flip chip bonding The bump. -11 - 201246414 [Effects of the Invention] According to the present invention, it is possible to provide a flip chip connection terminal capable of ensuring adhesion even if it is fine, and is capable of being inverted between the bumps of the semiconductor element. A method of manufacturing a package substrate for mounting a semiconductor element which is excellent in reliability and which is excellent in reliability, and a flip chip connection terminal for which a necessary amount of solder is necessary for mounting a wafer, and a semiconductor A package substrate for mounting components and a semiconductor package. [Embodiment] Hereinafter, an example of a package substrate for mounting a semiconductor element of the present invention will be described with reference to Figs. 2 to 9 . The first example of the package substrate for mounting a semiconductor device of the present invention (hereinafter referred to as a "package substrate") includes an insulating layer 3 as shown in FIG. 2, and is exposed to the upper surface. a buried circuit 2 provided in a manner of the surface of the insulating layer 3; and a solder resist 4 disposed on the insulating layer 3 and buried in the circuit 2, and disposed on the solder resist 4 The embedded circuit 2 in the opening 31 is formed as a flip chip connection terminal 26, and the flip chip connection terminal 26 is a semiconductor element mounting package which is covered by a preliminary solder 19 having a thickness of 3 // m or more. Substrate 1. According to this configuration, the flip chip connection terminal 26 is formed by the buried circuit 2 having the upper surface exposed on the surface of the insulating layer 3. Therefore, since the side surface and the bottom surface of the flip chip connection terminal 26 are buried in the insulating layer 3 and fixed, the buried circuit 2 of the flip chip connection terminal -12-201246414 26 is formed, even if it is a line The fine circuit pattern having a level of 20/zm/2 〇em or less is also a flip chip connection terminal 26 capable of securing the adhesion to the insulating layer 3. In the case where the embedded circuit 2 having the both sides in the longitudinal direction of the flip-chip connecting terminal 26 is provided, the embedded circuit 2 can also fix the flip-chip connecting terminal 26 from both sides. It is desirable from the viewpoint of ensuring the adhesion, but in the present invention, compared to the general convex circuit 32 shown in FIG. 1, it can be formed even if it is fine, and the insulating layer 3 can be formed. The adhesion between them ensures the flip chip connection terminal 26. Therefore, as shown in FIG. 3, an embedded circuit 2 which is extended only at one side in the longitudinal direction of the flip-chip connecting terminal 26 can be formed, in which case the flip chip can be connected. Since the size of the terminal 26 is reduced, it is preferable from the viewpoint of further increasing the density. Further, as shown in Fig. 4, both sides of the buried circuit 2 which are extended on one side and both sides in the longitudinal direction of the flip chip connection terminal 26 may be provided. In this manner, the buried circuit 2 is extended in the longitudinal direction of the flip-chip connecting terminal 26, either at both sides in the longitudinal direction of the flip-chip connecting terminal 26 or only in the single It can be on the side, so it is possible to increase the degree of freedom in design. Further, since the flip chip connection terminal 26 is covered by the preliminary solder 19 having a thickness of 3 am or more, it is possible to secure the flip chip connection with the bump 25 of the semiconductor element 15. The amount of solder needed. Therefore, it is possible to provide a package substrate 1 for mounting a semiconductor element which is compatible with high density and which is excellent in reliability. -13- 201246414 The term "insulating layer" as used in the present invention refers to an insulating substrate, a core substrate, a film, an interlayer insulating layer, a build-up layer, or the like formed using an organic insulating material. As such an insulating layer, those which are generally used in a package substrate can be used, and a prepreg impregnated with an epoxy resin or a polyimide resin in a glass cross can be used. The oxygen-based film or the polyimide-based film or the like is formed by heating or pressurizing. The term "embedded circuit" as used in the present invention means a circuit provided in such a manner that at least a portion of the bottom surface and the side surface are buried in the insulating layer and at least the upper surface is exposed on the surface of the insulating layer. Such a buried circuit can be, for example, via a so-called transfer. The method is formed by using a metal foil as a power supply layer, and pattern plating is applied thereon to form a specific circuit pattern, and then an insulating layer is formed on the circuit pattern, and the circuit pattern is buried therein. In the insulating layer, the metal foil as the power supply layer is removed by etching or the like, and the surface of the circuit pattern buried in the pattern insulating layer is exposed from the insulating layer to the so-called solder resist of the present invention. The surface of the package substrate is protected so that the preliminary solder does not adhere to a portion other than the buried circuit of the flip chip connection terminal. Further, the portion to be flip-chip connecting terminals in the buried circuit is defined by the opening provided in the solder resist, so that the buried circuit in the opening forms the flip-chip connecting terminal. As a solder resist, from the viewpoint of being able to form a fine opening of a vertical thickness of 100 μm or less which is used to form a flip chip connection terminal with good precision, * is a photosensitive solder resist-14 - 201246414 The agent is ideal. The flip chip connection terminal of the present invention is a connection terminal used for mounting a semiconductor element on a package substrate via flip chip bonding. Moreover, the flip chip connection refers to a method of connecting the active device surface of the semiconductor element toward the package substrate, and forming a bump as an electrode on the semiconductor element, and inverting the semiconductor element on the package substrate. The mounting position is the same, and then the bump of the semiconductor element and the flip chip connection terminal formed on the package substrate are connected. The flip chip connection terminal of the present invention is actually not only referring to the semiconductor element. The connecting portion of the bump is referred to as a portion of the buried circuit which is connected to the bump of the semiconductor element and which is exposed from the surface of the insulating layer in the opening of the solder resist. On the surface of the flip chip connection terminal, nickel/gold plating (nickel plating and a gold plating layer formed thereon) may be provided in order to prevent oxidation of the surface and ensure the wettability of the preliminary solder. It is a protective plating such as nickel/palladium/gold plating (nickel plating on which palladium plating is formed and a gold plating is formed thereon). The term "pre-solder solder" as used in the present invention refers to solder which is provided on a flip chip connection terminal for performing flip-chip bonding with a semiconductor element. The preliminary solder can be formed by printing a solder paste and reflowing it, or by other known methods. As an example of the solder paste, a Sn (tin)-Pb (lead) type, a Sn (tin)-Ag (silver)-Cu (copper) type, etc. used for mounting an electronic component can be mentioned. The solder particles are mixed with rosin or an organic solvent. In the printing of the solder paste, a metal mask or a screen plate or the like can be used. Reflow can be carried out by infrared reflow, vapor phase soldering, etc., which are generally used in the mounting of electronic parts -15-201246414. Although the reflow is different depending on the solder paste, 'for example, it is a Sn-Pb (tin and lead) system, and the peak temperature is 240 ° C. The process is Sn (tin)-Ag (silver). The -Cu (copper) system is the condition of the peak temperature t. In the package substrate of the present invention, the flip chip connection terminal is covered with a preliminary solder of 3//m or more. If the preliminary solder is less than 3 /z m, the solder paste cannot be sufficiently formed between the flip chip connection terminal and the semiconductor element, and it is difficult to ensure the connectivity. On the other hand, if the thickness of the preliminary solder exceeds 20/zm, there is a possibility of bridging between the preliminary solder on the adjacent flip chip connection terminals. Therefore, the thickness of the preliminary solder is preferably 3 β ' or less than 20 M m. Further, in general, since the top surface of the flip-chip terminal has a long and narrow rectangular shape in plan view, the preliminary solder formed by reflowing the solder paste or the like is formed into a slightly semi-cylindrical shape via the solder tension ( In the present invention, the thickness of the preliminary solder is formed to be the thickest in the longitudinal direction (the length and the short side direction (wide direction)) of the flip chip connection terminal. The system is set to be slightly centered in the longitudinal direction (longitudinal direction) and the short side direction (width) of the reverse connection terminal, and the step between the etching agent surface and the solder surface by the non-contact type step measuring machine The second example of the package substrate of the present invention is the VPS condition, and if it is 260, the thickness of the thickness of the bump is reliable, and there is a raw solder τι. The above wafer is connected to the surface soldering direction of the solder). Therefore, the solder resist in the wafer orientation direction is generally shown in Fig. 5-16-201246414, on the bottom surface of the buried circuit 2 including the flip chip connection terminal 26. The connection of the through holes 18 is omitted. In addition, the display of the preliminary solder is omitted. In Fig. 5, the bottom surface of the flip chip connection terminal 26 is extended from the bottom surface of the flip chip connection terminal 26 and from the flip chip connection terminal 26 The through hole 18 is formed in both sides of the bottom surface of the buried circuit 2. However, it is also possible to form the through hole 18 only in one of the ones. That is, in the second example, The bottom surface of the flip chip connection terminal 26 embedded in the insulating layer 3, or the bottom surface of the buried circuit 2 which is extended from the flip chip connection terminal 26 toward the long side direction, or the like The bottom surface of both of them is formed with a through hole 18. By thus connecting the through hole 18 at the bottom surface, the flip chip connection terminal 26 is oriented from the flip chip connection terminal 26 toward the long side. Since the extended buried circuit 2 is fixed to the insulating layer 3 via the through hole 18, the adhesion between the flip chip connection terminal 26 and the insulating layer 3 can be made in comparison with the first example. In the present invention, the so-called through hole is intended to be For the connection between the layers on which the plurality of wiring layers are provided on the substrate, for example, holes for interlayer connection of the wiring layers may be formed by laser or the like, and then plating may be performed in the holes. In order to obtain more of the bottom surface of the flip chip connection terminal or the connection area between the bottom surface of the buried circuit and the through hole extending from the flip chip connection terminal toward the long side direction, it is preferable. The through hole is formed by so-called filled via plating. As a third example of the package substrate of the present invention, it is exemplified as shown in FIG. 6 in the flip chip connection terminal 26. A portion of the long-side direction -17-201246414 is formed with a convex shape 27. In addition, the display of the preliminary solder 19 is omitted. The convex shape 27 can be formed, for example, by forming a plating resist and pattern plating a portion of the buried circuit to which the flip chip connection terminal 26 is buried. Further, although not shown, it is also possible to form a buried circuit from the surface of the insulating layer 3 so that one side of the side surface and the upper surface are protruded, and then an etching resist is formed to make it stand out. One portion of the buried circuit is formed by being etched while remaining prominently and leaving the other portion in the same plane as the surface of the insulating layer 3. The height of the convex shape 27 is preferably about 3/zm to 8/zm, and the range of the convex shape 27 is set to be 50% of the dimension in the short-side direction (wide direction) of the flip-chip connecting terminal 26. ~1 0 0 °/. It is preferable that the length of the flip chip connection terminal 26 is 10% to 70% of the dimension in the longitudinal direction (longitudinal direction). By forming the convex shape 27 at a portion in the longitudinal direction of the flip-chip connecting terminal 26 as described above, since the solder is accumulated in the step portion of the convex shape 27 (not shown), The amount of solder disposed on the flip chip connection terminal 26 can be increased as compared with the case where the surface is flat. Further, since the convex shape 27 is a cause for concentrating the solder of the other portion, and the solder is aggregated with the convex shape 27 as a center, the protruding solder storage portion can be formed on the flip chip connection. The terminal 26 is at a specific position in the longitudinal direction. Therefore, since the protruding portion of the flip chip connection terminal 26 can be provided corresponding to the position of the bump of the semiconductor element mounted on the flip chip connection terminal 26, the flip chip connection can be performed. The terminal 26 and the bump of the semiconductor element are surely connected. -18-201246414 As a fourth example of the package substrate of the present invention, a recessed shape is formed in a portion of the longitudinal direction of the flip-chip connecting terminal 26 as shown in FIG. . In addition, the display of the preliminary solder is omitted. Although not shown, the recessed shape 28 may be formed, for example, by embedding a surface from the surface of the insulating layer 3 to expose the surface, and then forming an etching resist, so that the upper surface is formed. A portion of the exposed buried circuit is formed by etching so that the surface of the insulating layer 3 is more recessed and the other portions remain as they are. The depth of the recessed shape 28 is preferably about 3 // m to 8 // m, and the range of the recessed shape 28 is set to be the rule of the short side direction (wide direction) of the flip chip connection terminal 26. It is desirable to be 50% to 100% of the inch and to be 10% to 70% of the dimension in the longitudinal direction (longitudinal direction) of the flip chip connection terminal 26. By forming the recessed shape 28 in this manner, since the molten solder is accumulated in this portion, the amount of solder (not shown) disposed on the flip chip connection terminal 26 can be increased. In other words, since the recessed shape 28 functions as a container for depositing solder, and the solder is stored in the recessed shape 28, it is possible to form a solder paste on the flip chip connection terminal 26. Sufficient solder required. As a fifth example of the package substrate of the present invention, the front end of the flip chip connection terminal 26 is formed in the opening 31 of the solder resist 4 as shown in Fig. 3 as a general example. In addition, the display of the preliminary solder is omitted. When the package substrate is generally formed as in the prior art, the circuit pattern is formed by the embossing of the metal foil on the surface of the insulating layer 3 to form a circuit pattern, which is a convex circuit 32 ( 1), the flip chip connection terminal 26 is formed such that only the bottom surface thereof is followed by the insulating layer 3. Further, since it is formed by etching, the circuit pattern formed by the convex circuit 3 2 is formed to have a wider surface than the surface side of the circuit pattern when viewed from the cross section. The so-called undercut phenomenon. Therefore, if the size of the flip chip connection terminal 26 is made fine, the area between the bottom surface of the circuit pattern formed by the convex circuit 32 and the insulating layer 3 is reduced, and therefore, between the insulating layer 3. The adhesion will be reduced, and even if a little external force is applied only when flip chip bonding is performed, there is a possibility of peeling. Therefore, in order to secure the adhesion between the insulating layer 3 and the flip-chip connecting terminal 26, the solder resist 4 is used for coating, and the circuit pattern is fixed from the upper side, and the flip-chip connecting terminal 26 is fixed. It is exposed from the opening 31 of the solder resist 4, whereby the both sides in the longitudinal direction of the flip chip connection terminal 26 are fixed by the solder resist 4. However, in this method, the width of the opening 31 of the solder resist 4 is limited due to the limit of the resolution of the solder resist 4, so it is necessary to set the flip chip connection terminal 26 to The limit of the resolution of the solder resist 4 is longer. Moreover, due to this, the degree of freedom in drawing the circuit pattern is also limited. According to the fifth example of the package substrate 1 of the present invention, since the upper surface of the flip chip connection terminal 26 is formed by embedding the circuit from the surface of the insulating layer 3, even if it is fine, Be able to ensure the adhesion. Therefore, it is not necessary to coat the circuit pattern which is extended at both sides in the longitudinal direction of the flip-chip connecting terminal 26 from the upper -20-201246414 via the solder resist 4, and it is possible to flip the wafer. The front end of the connection terminal 26 is formed in the opening 31 of the solder resist 4. Therefore, since the flip chip connection terminal 26 can be made fine without being limited by the resolution of the solder resist 4, the density can be increased, and the degree of freedom in designing the circuit pattern can be achieved. Upgrade. The sixth example of the package substrate of the present invention is exemplified as shown in FIG. 4, and is provided with an extension of the both sides in the longitudinal direction of the flip-chip connecting terminal 26 or a single side. Into the circuit 2. According to the sixth example of the package substrate of the present invention, the flip chip connection terminal 26 can be made fine without being limited by the resolution of the solder resist 4, as in the fifth example. The density can be increased, and the degree of freedom in designing a circuit pattern can be improved. As a seventh example of the package substrate of the present invention, as shown in FIG. 8, a portion of the flip chip connection terminal 26 is provided with an expansion in the short side direction (wide direction). Part 33. The front end of the flip chip connection terminal 26 may also be formed in the opening 31 of the solder resist 4. In addition, the display of the preliminary solder is omitted. By partially providing the flip-chip connecting terminal 26 with the portion 3 3 which is expanded in the short-side direction (wide direction), since the adhesion area between the flip-chip connecting terminal and the insulating layer 3 is enlarged, The adhesion between the flip chip connection terminal 26 and the insulating layer 3 can be further improved, and the amount of the preliminary solder 19 can be ensured, and the short side direction (wide direction) can be made. Since the preliminary solder 19 of the expanded portion 33 is pulled by the solder other than the surface tension, and the solder is accumulated, the -21 - 201246414 can stably store the solder at a specific position. Formed as an example of the semiconductor package of the present invention, as shown in FIG. 9, generally, the semiconductor element 15 is connected by flip chip bonding on the package substrate 1 of the first to seventh examples described above. Come to be a carrier. It is preferable that the lower coffin 23 is filled between the projection 25 forming surface of the semiconductor element 15 and the insulating layer 3 including the flip chip connecting terminal 26 of the semiconductor element mounting package substrate 1. According to this, the lower material 23 is formed so that the adhesion between the surface of the bump 25 of the semiconductor element 15 and the insulating layer 3 having the flip chip connection terminal 26 can be made stronger. Therefore, it is possible to provide a semiconductor package 24 which can correspond to high density and is excellent in reliability. Hereinafter, an example of a method of manufacturing a package substrate of the present invention will be described with reference to Figs. 10 to 18 . First, as shown in Fig. 10, a multilayer metal foil 9 in which the first carrier metal foil 1 〇 and the second carrier metal foil 1 1 and the base metal foil 1 2 are laminated in this order is prepared. The first carrier metal foil 10 is used to protect the surface of the second carrier metal foil 11 (between the first carrier metal foil 10) and is disposed between the second carrier metal foil 11 and the second carrier metal foil 11 Crop rational stripping. As long as the surface of the second carrier metal foil 11 can be protected, the material and the thickness are not particularly limited. However, from the viewpoint of versatility and handleability, it is preferable to use copper foil or aluminum foil as the material. It is ideal for 1~3 5 vm. Further, preferably, a peeling layer (not shown) is provided between the first carrier metal foil 1〇 and the second carrier metal case 1 1 to stabilize the peel strength -22-201246414 between the two. In the case of the peeling layer, it is preferable that the peeling strength can be stabilized even if heating and pressurization are performed in a plurality of times when laminated with an insulating resin. In the case of the above-mentioned release layer, a metal oxide layer and an organic agent layer are disclosed in Japanese Laid-Open Patent Publication No. 2003-108553. A metal oxide containing Ni and W or a metal oxide of Ni and Mo disclosed in Japanese Laid-Open Patent Publication No. WO2006/01 3735 is disclosed. Further, the release layer is preferably in a state in which the first carrier metal foil 10 is adhered to the side of the first carrier metal foil 1 when it is physically peeled off from the second carrier metal foil 1 1 . The lower layer is peeled off and does not remain on the surface of the second carrier metal foil 11. The second carrier metal foil 11 is provided as a seed layer (power supply layer) for supplying current to the first pattern plating layer 1 on the surface after the first carrier metal foil 10 is peeled off. In order to be able to act as a power supply layer between the first carrier metal foil 10 and the base metal foil 12, as long as it can function as a power supply layer in the same manner as the base metal foil 12, it is not particularly The material or the thickness is limited. However, from the viewpoint of versatility and handleability, copper foil or aluminum foil is preferred as the material, and 1 to 18/zm can be used as the thickness. However, as described later, since the outer layer circuit 2 is formed (Figs. 16(12), (13), and (14)), it is removed by etching. Therefore, in order to minimize the variation in the etching amount and to form high precision. The fine circuit of the degree is ideal for the extremely thin metal foil of 1~. Further, in order to stabilize the peel strength between the first carrier metal foil 1 and the -23-201246414 base metal foil 12, it is preferable to set it as described above. Release layer (not shown). Further, since the release layer is integrated with the second carrier metal foil 11 and the base metal foil 12 and functions as a seed layer, it is desirable to have conductivity. Moreover, it is preferable that the peeling layer is peeled off in a state of being adhered to the side of the base metal foil 12 when physically peeling off from the second carrier metal foil 11 and the base metal foil 1 2, It does not remain on the surface of the second carrier metal foil 11. The base metal foil 12 is a side where the multilayer metal foil 9 and the base material 16 are laminated to form the core substrate 17, and the position is placed on the side to be laminated with the substrate 16, and is set to be 2 Physical peeling is performed between the carrier metal foils 1 1 . As long as it has the adhesion to the substrate 16 when it is laminated with the substrate 16, it is not particularly limited to the material or the thickness. However, as a material, it is used as a material from the viewpoint of versatility and handleability. Ideal for copper boxes or name boxes, as the thickness, it is ideal for 9~. Further, in order to stabilize the peeling strength between the second carrier metal foil 11 and the second carrier metal foil 11, it is preferable to provide a general peeling layer (not shown) as described above. In addition, this peeling layer is ideal when it is. When physically peeling off from the second carrier metal foil 1 1 and the base metal foil 1 2, the film is peeled off while being adhered to the side of the base metal foil 12, and does not remain in the second carrier metal foil. On the surface of 11 people. As the multilayered metal foil 9, a multilayer metal foil having three or more metal foils (for example, the first carrier metal foil 10 and the second carrier metal foil n and the base metal foil 12 as described above) is used. -24- 201246414 9, and at least between two places (for example, as described above, between the first carrier metal foil 1〇 and the second carrier metal foil 11 and the second carrier metal foil 11 and the substrate) Between the metal foils 1 2), it is possible to peel off the crop rationally. When the base material 16 is laminated on the base metal foil 1 2 side of the multilayered metal foil 9 to form the core substrate 17 , foreign matter such as resin powder adheres to the surface of the first carrier metal foil 1 . In this case, even if the foreign material adheres to the first carrier metal foil 10 and physically separated from the second carrier metal foil 11, it is possible to form a resin powder or the like. The surface of the second carrier metal foil 11 affected by the foreign matter can secure a high-quality metal foil surface. Therefore, even when the second carrier metal foil 11 is used as a seed layer and the first pattern plating 13 is performed, the occurrence of defects can be suppressed. Therefore, it is possible to improve the yield. . Next, as shown in Fig. 11 (1), the base metal foil 12 side of the multilayered metal foil 9 and the substrate 16 are laminated to form a core substrate 17. The base material 16 is formed by laminating and integrating the multilayer metal foil 9 to form the core substrate 17. The base material 16 can be used as the insulating layer 3 which is generally used as the package substrate 1 for semiconductor element mounting. By. Examples of such a substrate 16 are glass epoxy 'glass polyimine and the like. When the package substrate 1 is manufactured by using the multilayer metal foil 9, the core substrate 17 is a support substrate, and the workability is improved by ensuring rigidity, and the damage during processing is prevented and the yield is improved. The matter is the main utilitarian. Therefore, it is preferable that the substrate 16 is made of a reinforcing material such as glass fiber. For example, a prepreg such as glass epoxy or glass polyfluorene-25-201246414 imine may be used with a multilayer metal. The foils 9 are stacked and formed by laminating and heating by heat pressing or the like. By being on both sides of the substrate 16 (Fig. 11(1) Upper and lower sides of the metal foil 9 are laminated, and subsequent engineering is performed. Since it is possible to manufacture two package substrates 1 by one engineering, it is possible to achieve The number of projects is reduced. Further, since it is possible to form a laminated board having a symmetrical structure on both sides of the core substrate 17, it is possible to suppress the bending, and it is also possible to work at the manufacturing facility or because it is stuck at the manufacturing facility. The damage caused by the suppression is suppressed. Next, as shown in Fig. 11 (2), in general, the first carrier metal foil 10 and the second carrier metal foil 11 of the multilayer metal foil 9. The first carrier metal foil 10 was peeled off rationally. On the surface of the first carrier metal foil 1 异, foreign matter such as resin powder may be adhered from a prepreg or the like which is a material of the substrate 16 at the time of lamination. Therefore, when the first carrier metal foil 10 is used to form a circuit, there is a possibility that a defect such as a disconnection or a short circuit occurs in the circuit due to foreign matter such as resin powder adhering to the surface. The possibility of a decrease in yield. However, in the above-described manner, the first carrier metal foil 10 is removed and removed, and the circuit can be formed by using the second carrier metal foil 11 to which foreign matter such as resin powder is not adhered. It happened 'and became able to improve yield. In addition, since the first carrier metal foil 10 can be peeled off in a crop condition, the peeling strength between the first carrier metal foil 10 and the second carrier metal foil 1 1 can be easily adjusted. . At this time, it is preferable that the peeling layer (not shown) between the first carrier -26 - 201246414 metal foil 10 and the second carrier metal foil 11 of the multilayered metal foil 9 is carried away to the first carrier metal foil 10 sides. As a result, the surface of the second carrier metal foil 11 is exposed on the side of the second carrier metal foil after the first carrier metal foil 10 is peeled off, so that it is performed in the subsequent work. The plating resist on the carrier metal foil 11 or the first pattern plating 13 is not hindered by the peeling layer. Here, the multilayer metal foil 9 is preferably such that the peeling strength between the second carrier metal foil and the base metal foil 12 is smaller than the peel strength between the first carrier metal foil 10 and the second carrier metal foil 11. Larger multilayer metal foil 9. By this, when the first carrier metal foil 10 and the second carrier metal foil 11 are peeled off from each other, the second carrier metal foil 1 1 and the base metal foil 1 2 can be simultaneously peeled off. inhibition. In the initial state before the heating and pressurization, the peeling strength is set to be 2 N/m to 5 ON/m between the first carrier metal foil 10 and the second carrier metal foil 11 The peel strength between the first carrier metal foil 11 and the second carrier metal foil 1 1 is set to be 101^/111 to 7 01^/^1 between the second carrier metal foil 11 and the base metal foil 12. When the peel strength between the second carrier metal foil 1 1 and the base metal foil 1 2 is 5 N/m to 20 N/m, the peeling does not occur during the processing of the manufacturing process. In addition, when the first carrier metal foil 1 is peeled off, the second carrier metal foil 1 can be peeled off at the same time. Therefore, workability is preferable. The adjustment of the peeling strength can be, for example, as shown in Japanese Laid-Open Patent Publication No. 2003--27-201246414 181970 or Japanese Patent Laid-Open Publication No. 2003-094553, and Japanese Patent Publication No. WO2006/0 1 3 73 5 Adjusting the thickness of the surface of the second carrier metal foil π (between the first carrier metal foil 1〇) which is the base of the release layer, or for forming a metal oxide as a release layer or for forming an alloy plating The plating composition or conditions of the coating are adjusted to carry out. Next, as shown in Fig. 3 (3), the first pattern plating 13 is performed on the second carrier metal foil 11 remaining on the core substrate 17. As described above, the surface of the second carrier metal foil 11 (between the first carrier metal case 10) does not adhere to the resin powder or the like which is used in the prepreg or the like used for lamination. Foreign matter, therefore, is capable of suppressing circuit defects caused by this. The first pattern plating 1 3 is formed by forming a plating resist (not shown) on the second carrier metal foil 11 and then performing electroplating. As the plating resist, a photosensitive resist used in the manufacturing process of the package substrate 1 can be used. As the plating, copper sulfate electroplating used in the manufacturing process of the package substrate 1 can be used. The multilayer metal foil 9, which is preferably provided with an average roughness (Ra) of 0. 3"m~1. On the surface of the second carrier metal foil 11 having the unevenness of 2" m, the multilayer metal foil 9 of the first carrier metal foil 10 is laminated via a peeling layer (not shown). By this, the surface of the second carrier metal foil 11 which is physically peeled off together with the peeling layer is provided with a predetermined average roughness (Ra) of 0. 3#m~ 1. 2; embossing of czm" Therefore, when the shovel resist for the first pattern plating 13 is formed on the surface of the second carrier metal foil 11 (between -28 - 201246414 and the first carrier metal foil 10), The adhesion or resolution of the plating resist can be improved, which is advantageous for the formation of a high-density circuit. Further, by providing irregularities on the surface of the second carrier metal foil 11 in advance, after peeling off the first carrier metal foil 10, it is not necessary to roughen the surface of the second carrier metal foil 11 Therefore, it is possible to reduce the number of projects. The surface roughness of the unevenness provided on the surface of the second carrier metal foil 11 is improved from the viewpoint of improving the adhesion or resolution of the plating resist and ensuring the peeling property after the first pattern plating 13 The average roughness (Ra) is 0. 3em~1. 2//m is ideal. When the average roughness (Ra) is less than 0. In the case of 3 V m , there is a tendency that the adhesion of the plating resist is insufficient, and when the average roughness (Ra ) is more than 1. In the case of 2 μm, there is a tendency that the plating resist is difficult to follow and the adhesion is insufficient. Further, when the line/space of the plating resist is finer than 1 5 a m / 1 5 // m, the average roughness (Ra ) is 0. 5 μ m~0. 9 // m is ideal. Here, the average roughness (Ra) is an average thickness (Ra) defined by JIS B 060 1 (2001), and can be measured using a stylus type surface roughness meter or the like. In addition, when the second carrier metal foil 11 is a copper foil, the adjustment of the average thickness (Ra) is a composition capable of copper plating when forming a copper foil as the second carrier metal foil 11 ( It is carried out by including additives or the like. Then, as shown in Fig. 12 (4), the insulating layer 3 is laminated on the second carrier metal foil 11 including the first pattern plating 13, thereby forming a laminate 22 of -29-201246414. As the insulating layer 3, a user who is generally used as the insulating layer 3 of the package substrate 1 can be used. Examples of the insulating layer 3 include an epoxy resin and a polyimide resin. For example, an epoxy or polyimide film may be used, and a glass epoxy or a glass polyimide may be used. The prepreg such as an amine is formed by laminating and heating by heat and pressure using a hot press or the like. Here, the laminated body 22 is one of the states in which the integration is performed in such a manner that it is laminated on the second carrier metal foil 11 including the first pattern plating 13 . When the metal foil serving as the conductor layer 20 is further laminated on the resin which is the insulating layer 3 and heated and pressurized at the same time to be laminated and integrated, the conductor layer 20 is also included. Further, as will be described later, when the inner layer circuit 6 is formed by the conductor layer 20 or the interlayer connection 5 is formed by the conductor layer 20, the inner layer circuit 6 or the interlayer connection is also included. 5. Next, as shown in Figs. 12 (5) and (6), the interlayer connection hole 2 1 may be formed and the interlayer connection 5 or the inner layer circuit 6 may be formed. The interlayer connection 5, for example, can be formed by forming a layer connection hole 2 1 using a so-called Conformal method, and then plating the inside of the interlayer connection hole 2 1 . This plating can be applied as a base plating with a thin electroless copper plating, and then, as thick plating, electroless copper plating, electric copper plating, or pupil plating can be used. In order to make the thickness of the conductor layer 20 to be etched thin, it is easy to form a fine circuit, and it is preferable to form a plating resist after plating on a thin substrate, and to perform plating by electroplating or boring. To carry out thick plating. The inner layer circuit 6' can be formed, for example, by removing the conductor layer 20 of the unnecessary portion -30 - 201246414 by etching after the plating for the interlayer connection hole 21 is performed. Then, as shown in FIGS. 13(7), (8), and FIGS. 14(9), (10), the inner layer circuit 6 or the interlayer connection 5 is further formed to further form the insulating layer 3 and the conductor layer 20. Similarly to the case of Figs. 12 (5) and (6), the inner layer circuit 6 or the outer layer circuits 2, 7 and the interlayer connection 5 are formed so as to have a desired number of layers. Further, in the present invention, the inner layer circuit 6 and the outer layer circuits 2, 7 are collectively referred to as a conductor circuit. Next, as shown in Fig. 15 (11), the laminated body 22 and the second carrier metal foil 1 1 are collectively formed between the second carrier metal foil 11 of the multilayered metal foil 9 and the base metal foil 12 The core substrate 17 is rationally stripped and separated. In this case, it is preferable that the peeling layer (not shown) between the second carrier metal foil 11 of the multilayered metal foil 9 and the base metal foil 12 is carried away to the side of the base metal foil 12. Thereby, on the side of the laminate 2 2 after the base metal foil 12 is peeled off, since the surface of the second carrier metal foil 11 is exposed, the second carrier is carried out in the subsequent process. The etching of the metal foil 11 is not hindered by the peeling layer. Next, as shown in Figs. 16 (12) to (14), the second layer of the laminated body 22 which has been separated and separated An etching resist 34 is formed on the carrier metal foil 11, and the second carrier metal foil 11 of the laminate 22 is etched to thereby expose the first pattern plating 13 to the surface of the insulating layer 3. The buried circuit 2' is formed either on the first pattern plating π or on the insulating layer 3 to form the three-dimensional circuit 27. Further, as shown in FIG. 17 (-31 - 201246414 12) to (14), the second pattern plating 14 may be performed on the second carrier metal foil 11 of the laminate 22 which has been separated and separated. And an etching resist is formed on the carrier metal foil other than the portion where the second pattern plating is performed, and etching is performed, whereby the portion where the second pattern furnace layer 14 is formed and the etching resist are formed The second carrier metal foil 11 other than the portion is removed by etching, and the first pattern plating 13 is exposed on the surface of the insulating layer 3 to form the buried circuit 2 or on the first pattern plating 13 Or on the insulating layer 3, a three-dimensional circuit 27 is formed. Further, Fig. 16 (1 2 ) to (1 4 ) and Figs. 17 (1 2 ) to (14 ) are only for the lower side of the laminate 22 which is separated as in Fig. 15 (11). Part of the show. The buried pattern 2 formed by exposing the first pattern plating 13 from the insulating layer 3 can be formed by the processes of Figs. 16 (12) to (14) or Figs. 17 (12) to (14). The wafer connection terminal is formed by a three-dimensional circuit 27 formed on the first pattern plating on the surface of the laminate, and is formed into a bump or a pillar, and a three-dimensional circuit 27 is formed on the insulating layer on the surface of the laminate. It is capable of forming a dummy terminal. Thereby, when the outer layer circuit 2 is formed, since the side surface of the outer layer circuit 2 is not eroded by the etching, the base etching is not generated, and therefore, the fine outer layer circuit 2 can be formed. Further, since the outer layer circuit 2 formed by the present invention is buried in the insulating layer 3, not only the bottom surface of the outer layer circuit 2 but also the side surfaces on both sides are in close contact with the insulating layer 3' Therefore, even if it is a fine circuit, it can ensure sufficient confidentiality. Further, when the ultra-thin copper case having a thickness of 1 to 5 μm is used as the second carrier metal case 11, the second carrier metal foil 11 can be removed by -32-201246414 even if it is a little etching amount. The surface of the outer layer circuit 2 which is buried in the insulating layer 3 and exposed from the insulating layer 3 is flat, and the connection is ensured by the steel wire bonding terminal or the flip chip connection terminal. It is suitable for use as a connection terminal with a semiconductor element. Further, since the connection terminal with the semiconductor element can be provided in the outer layer circuit 2 at a position overlapping the interlayer connection 5 in a plan view, the connection terminal with the semiconductor element can be disposed between the layers. Immediately above or directly below the connection 5, it is also possible to correspond to miniaturization and high density. Further, by forming the three-dimensional circuit 27 at an arbitrary place, it is possible to form a structure of various conductor circuits such as bumps, posts, dummy terminals, and the like, and to plate the second carrier metal foil 11 or the second pattern. The thickness of the coating 14 can be changed to any height, and therefore, it can correspond to a connection form between various semiconductor elements (not shown) or other package substrates. For example, as shown in FIG. 18, in general, by providing a three-dimensional circuit 27 on the first pattern plating 13 of the package substrate 1 of the present invention and forming a pillar, the connection with the top substrate is performed, even if it is not Setting a hole can also constitute a PoP. Further, as shown in FIG. 18, when the bumps 25 on the side of the semiconductor element 35 are arranged in a peripheral arrangement (the bumps 25 are arranged side by side around the semiconductor element 35), when flip chip bonding is performed, When the semiconductor element 35 is pressed to the side of the semiconductor element mounting package substrate 1, the central portion of the semiconductor element 35 is easily deformed and deformed. However, a dummy terminal is provided in advance (in FIG. 18, it is formed in The three-dimensional circuit 27 on the insulating layer is capable of supporting the lower surface of the semiconductor element 35, and therefore can be suppressed from -33 to 201246414 for the deformation. Further, if the dummy terminal is formed by plating the first pattern or the interlayer connection 5, the heat from the semiconductor element 35 can be released. Therefore, it is possible to improve the reliability. In addition, the dummy terminal is electrically independent and does not function as an electrical circuit. Although it is formed on the insulating layer in FIGS. 16 and 17, it can be combined with The first pattern plating that does not function electrically or the interlayer connection 5 is connected. Next, the solder resist 4 or the protective plating 8 may be formed as needed. As the protective plating 8, it is preferable to use a nickel plating and a gold plating which are generally used as a protective plating of a connection terminal of a package substrate. As described above, according to the manufacturing method of the package substrate according to the present invention, It is possible to form a package substrate having a flat and fine embedded circuit at a position overlapping the interlayer connection, and to form a package substrate suitable for wire bonding or flip chip bonding. Further, by forming a three-dimensional circuit at any place, it is possible to form a package substrate having various metals such as bumps or pillars. [Embodiment] Next, an embodiment of another manufacturing method of the package substrate of the present invention will be described. However, the present invention is not limited to the embodiment. (Embodiment 1) First, as shown in Fig. 10, a plurality of layers in which the first carrier metal-34-201246414 foil 10 and the second carrier metal foil 11 and the base metal foil 12 are laminated in this order are prepared. Metal foil 9. The first carrier metal foil 10 is made of a copper foil of 9 μm, the second carrier metal foil 11' is made of an ultra-thin copper foil of 3/zm, and the base metal foil 12 is made of a copper foil of 18 vm. A peeling layer (not shown) is provided on the surface of the base metal foil 12 (between the second carrier metal foil 11) so as to be peelably peelable. Further, the surface of the second carrier metal foil 11 (between the first carrier metal foil 10) is previously provided with an average roughness (Ra) 〇. 7ym bumps. Further, on the unevenness, that is, a peeling layer (not shown) is provided between the first and second carrier metal foils 1 so as to be capable of being peeled off by crops. Between the base metal foil 12 and the second carrier metal foil 11, and in the second load.  The peeling layer between the bulk metal foil 1 1 and the first carrier metal foil 10 is obtained by using Ni 30 g/L, Mo 3. A plating bath of 0 g/L and a citric acid composition of 30 g/L was formed to form a metal oxide layer. Further, the adjustment of the peel strength is carried out by adjusting the current to adjust the amount of the metal oxide forming the peeling layer. The peel strength at this time is 47 N/m between the base metal foil 12 and the second carrier metal foil 1 1 and is 29 N/m between the second carrier metal foil 11 and the first carrier metal foil 10. In addition, the rate of change in peel strength after heating and pressurization (after the core substrate 17 is formed by laminating the prepreg of the substrate 16 to form the core substrate 17) is approximated to the initial state. 1 degree of increase in the degree of 》%>> The production of the multilayered metal foil 9 shown in Fig. 10 is specifically carried out as follows. (1) As the base metal foil 12, an electrolytic copper-35-201246414 foil having a thickness of 18/m was used, and it was subjected to acid immersion in 30 g/L of sulfuric acid for 60 seconds, and then water-flow was performed for 30 seconds. Washed in water. (2) Electrolytic copper foil after washing is used as a cathode', and a Ti (titanium) plate coated with ruthenium oxide is used as an anode, and is plated as containing Ni (nickel), Mo (molybdenum), and citric acid. Bath, in nickel sulfate 6 hydrate 30g / L, sodium molybdate 2 hydrate 3. 0g / L, citrate 3 sodium 2 hydrate 30g / L, pH6. 0. In a bath at a liquid temperature of 30 ° C, on the shiny side of the electrolytic copper foil, electrolysis treatment is carried out for 5 seconds at a current density of 20 A/dm 2 to form a metal oxide containing nickel and molybdenum. Peel layer (not shown). (3) On the surface after the formation of the peeling layer (not shown), the cerium oxide coating is applied by a bath of copper sulfate 5 hydrate 200 g/L, sulfuric acid 100 g/L, and a liquid temperature of 40 ° C. The Ti (titanium) plate was used as an anode, and electrolytic plating was performed for 200 seconds by a current density of 4 A/dm 2 to form a metal layer of the second carrier metal foil 11 having a thickness of 3/m. (4) On the surface of the metal layer to be the second carrier metal foil 11, the same bath as in the above (2) is used, and the electrolytic treatment is performed for 10 seconds at a current density of 10 A/dm2 to form a A release layer (not shown) of a metal oxide formed of nickel and molybdenum. (5) On the surface on which the peeling layer 13 was formed, the same bath as in the above (3) was used, and electrolytic plating was performed for 600 seconds by a current density of 4 A/dm2 to form a thickness of 9/zm. The metal layer of the first carrier metal foil 1〇. (6) On the surface in contact with the substrate 16, the coarse particles of the granular form were formed by copper sulfate plating, -36-201246414, and chromic acid treatment and decane coupling agent treatment were applied. Further, a chromic acid treatment was applied to the surface which was not in contact with the substrate 16. Next, as shown in Fig. 11 (1), the base metal foil 12 side of the multilayered metal foil 9 and the substrate 16 are laminated to form a core substrate 17. As the substrate 16, a prepreg made of glass epoxy was used, and a plurality of metal foils 9 were placed on the upper and lower sides of the prepreg, and heated, pressurized, and laminated by heat pressing. Next, as shown in Fig. 11 (2), the first carrier metal foil 1 is physically peeled off between the first carrier metal foil 10 of the multilayered metal foil 9 and the second carrier metal foil 11. Next, as shown in FIG. 1 1 (3), the first pattern plating 13»the first pattern plating 13 is performed on the second carrier metal foil 11 remaining on the core substrate 17, and the second pattern plating is performed. A photosensitive plating resist is formed on the carrier metal foil 11 and then formed by electroplating with copper sulfate. Next, as shown in Fig. 12 (4), the 'on the second carrier metal foil 11 including the first pattern plating 13' is generally used as the insulating layer 3 and the conductor layer 20, and the copper foil is laminated (12//m). Further, a laminate 22° was formed as the insulating layer 3, and an epoxy-based succeeding sheet was formed by heating, pressurizing and laminating the laminate using hot pressing. Next, as shown in Figs. 12 (5) and (6), the interlayer connection 5 or the inner layer circuit 6 is generally formed. The interlayer connection 5' is formed by performing "minening" in the interlayer connection hole 2 1 after forming the interlayer connection hole 21 by a Conformal method. This plating was subjected to a thin electroless copper plating as a base-37-201246414 bottom plating, and then a photosensitive plating resist was formed, and copper sulfate plating was performed as thick plating. Thereafter, the inner layer circuit 6 is formed by removing unnecessary portions of the conductor layer 20 by etching. Next, as shown in FIGS. 13(7), (8), and FIGS. 14(9), (10), generally, the inner layer circuit 6 or the interlayer connection 5 is formed to further form the insulating layer 3 and the conductor layer 20'. The inner layer circuit 6 or the outer layer circuits 2, 7, and the interlayer connection 5 are formed, and the laminate 22 having the conductor layer 20 having four layers is formed. Next, as shown in Fig. 15 (11), in the multilayer metal foil Between the second carrier metal foil 11 of 9 and the base metal foil 12, the laminate 22 is peeled off from the core substrate 17 together with the second carrier metal foil 1 1 and separated. Next, as shown in FIGS. 16(12) to (14), an etching resist 14 is formed on the second carrier metal foil 11 of the laminated body 22 which has been separated and separated, and the laminated body 2 is formed. The second carrier metal foil 1 1 of 2 is etched, whereby the first pattern plating 13 is exposed on the surface of the insulating layer 3, the buried circuit 2 is formed, and the first pattern plating is performed. On the upper surface of the insulating layer 3, a three-dimensional circuit 27 is formed. In addition, the embedded circuit 2 formed by exposing the first pattern plating 13 from the insulating layer 3 serves as a flip chip connection terminal, and is formed in a three-dimensional circuit 27' on which the first pattern is plated on the surface of the laminate. As a bump, the three-dimensional circuit 27 formed on the insulating layer on the surface of the laminate is used as a dummy terminal. Next, a photosensitive solder resist was formed, and then, as a protective plating -38 - 201246414, electroless nickel plating and electroless gold plating were performed to form a package substrate. (Example 2) The peeling strength between the base metal foil 12 and the second carrier metal foil 11 and between the second carrier metal foil 11 and the first carrier metal foil 10 is provided by using Ni (nickel) 30g / L, Mo (molybdenum) 3. A plating bath of 0 g/L and a citric acid composition of 30 g/L was used to form a metal oxide layer, and the current at this time was changed to adjust the amount of metal oxide forming the peeling layer to change the peel strength. The peel strength at this time was 23 N/m between the base metal foil 12 and the second carrier metal foil 11, and was 18 N/m between the second carrier metal foil 11 and the first carrier metal foil 10. Except for this, a package substrate was produced in the same manner as in Example 1. (Example 3) The peeling strength between the base metal foil 12 and the second carrier metal foil 11 and between the second carrier metal foil 11 and the first carrier metal foil 10 was provided by using Ni ( Nickel) 30g / L, Mo (molybdenum) 3. A plating bath of 0 g/L and a citric acid composition of 30 g/L was used to form a metal oxide layer, and the current at this time was changed to adjust the amount of metal oxide forming the peeling layer to change the peel strength. The peel strength at this time is 15 N / m between the base metal foil 12 and the second carrier metal foil 11, between the second carrier metal foil 11 and the first carrier metal foil 10, and -39-201246414 is 2N/m. Except for this, a package substrate was produced in the same manner as in Example 1. (Example 4) The peeling strength between the base metal foil 12 and the second carrier metal foil 11 and between the second carrier metal foil 11 and the first carrier metal foil 10 was provided by using Ni ( Nickel) 30g / L, Mo (molybdenum) 3. A plating bath of 0 g/L and a citric acid composition of 30 g/L is used to form a metal oxide layer, and the current at this time is changed to adjust the metal oxide fi forming the peeling layer to change the peel strength. . The peel strength at this time was 68 N / m between the base metal foil 12 and the second carrier metal foil 11, and was 48 N / m between the second carrier metal foil 11 and the first carrier metal foil 10. The multilayer metal foil 9 prepared above is used instead of the one shown in Figs. 16(12) to (14) of the embodiment 1, and is separated as shown in Figs. 17(12) to (14). On the second carrier metal foil of the peeled laminate 22, the second pattern plating 14 is performed, and an etching resist 34 is formed on the carrier metal foil other than the portion where the second pattern is plated. By etching, the second carrier metal foil 1 1 other than the portion where the second pattern plating 14 is formed and the portion where the etching resist is formed is removed by etching, and the first pattern is plated 13 The buried circuit 2 is formed on the surface of the insulating layer 3, and a three-dimensional circuit 27 is formed on the first pattern plating 13 or the insulating layer 3. In addition, the buried circuit 2 formed by exposing the first pattern plating 13 from the insulating layer 3 is used as a flip-chip-40-201246414 chip connection terminal, and is formed on the surface of the laminate by the first pattern ammonium coating. The upper three-dimensional circuit 27' serves as a column, and a three-dimensional circuit 27 formed on the insulating layer on the surface of the laminate is used as a dummy terminal. In addition to this, a package substrate was produced in the same manner as in Example 1 (Example 5). Between the base metal foil 12 and the second carrier metal foil 11 and in the second carrier metal foil Π and 1 The peel strength between the carrier metal foils 10, by using Ni (nickel) 30 g / L, Mo (molybdenum) 3. A plating bath having a composition of 0 g/L and 30 g/L of citric acid was used to form a metal oxide layer, and the current at this time was changed to adjust the amount of metal oxide forming the peeling layer to change the peel strength. The peel strength at this time was 43 N / m between the base metal foil 12 and the second carrier metal foil 11, and was 28 N / m between the second carrier metal foil 11 and the first carrier metal foil 10. Except for this, a package substrate was produced in the same manner as in Example 4. (Example 6) The peeling strength between the base metal foil 12 and the second carrier metal foil 11 and between the second carrier metal foil 11 and the first carrier metal foil 1 , is provided by using Ni (nickel) 30g / L, Mo (molybdenum) 3. A plating bath having a composition of 0 g/L and 30 g/L of citric acid was used to form a metal oxide layer, and the current at this time was changed to adjust the amount of metal oxide forming the peeling layer to change the peel strength. At this time, the peel strength -41 - 201246414 'between the base metal foil 12 and the second carrier metal foil 11' is 22 N /m' between the second carrier metal foil 11 and the first carrier metal foil 1' It is 4N/m. Except for this, a package substrate was produced in the same manner as in Example 4. In Table 1, for the first embodiment, the final state of the outer layer circuit 2 formed in the insulating layer 3, between the first carrier metal foil 10 and the second carrier metal foil 11 is applied. The peel strength, the peel strength between the second carrier metal foil 11 and the base metal case 12, and the presence or absence of peeling of the carrier metal foil at the time of processing were demonstrated. In any of the first to sixth embodiments, the fine outer layer circuit 2 capable of forming a line/space of ΙΟ/zm/lOjczm (the one in Table 1 indicates that there is no base etching). Further, after observing the cross section, no base corrosion occurred in the results. Further, from the observation results of the cross-section, it can be seen that since the second carrier metal case 11 uses a very thin copper box of 3/zm, it can be uniformly removed by only a small amount of hungry. The unevenness of the surface of the outer layer circuit 2 is flat. Further, in any of the first to sixth embodiments, in the process of the manufacturing process, 'between the first carrier metal foil 1〇 and the second carrier metal foil 、, and the second carrier metal foil U and the base metal foil 12 There was no flaking between the two (the ones in Table 1 indicate that there is no flaking). Further, when the first carrier metal case 1〇 and the second carrier metal foil 1 1 are peeled off, the second carrier metal case i i and the base metal foil 12 are not peeled off. -42- 201246414 [Table 1] Item line/space (ym/em) Peel strength (N/m) Stripping of metal foil during processing 10/10 15/15 20/20 1st carrier metal foil / 2nd carrier metal Foil 2nd Carrier Metal Foil / Base Metal Foil Example 1 〇〇〇 29 47 〇 Example 2 〇〇〇 18 23 〇 Example 3 〇〇〇 2 15 〇 Example 4 〇〇〇 48 68 〇 Example 5 〇 〇〇28 43 〇Embodiment 6 〇〇〇4 22 〇 As shown in Fig. 18, the buried circuit 2 of the package substrate (Fig. 17 (14)) fabricated by the fourth embodiment will be The bumps 25 of the semiconductor element 35 are pressed and flip-chip bonded using solder (not shown). In the semiconductor element 35, the bumps 25 are circumferentially arranged. However, since the lower surface of the semiconductor element 35 is supported by the dummy circuit 27 which becomes a dummy terminal, the semiconductor element 35 is attached. There was no deflection. The measurement of the peel strength (N/m) at the initial stage before heating and pressurization (before the prepreg of the substrate 16 was laminated and before forming the core substrate 17) was cut to a width of 10 mm. A sample of a multi-layered metal foil, which is manufactured by Timothy RTM-100CORIENTEC Co., Ltd., trade name, "Tian Xilong" is a registered trademark), and is subject to the 90 degree pull-off method of JIS Z 023 7 First, at room temperature (25 ° C), first, the first carrier metal foil is pulled and peeled at a speed of 300 mm per minute toward the direction of 90 degrees, and then the second carrier metal foil is oriented. In the direction of 90 degrees, pull at a speed of 300 mm per minute and measure in the line -43-201246414. In addition, the peeling strength ' after the heating and pressurization (after the core substrate 17 is formed by laminating the prepreg of the substrate 16) is also measured in the same manner as the initial peel strength, and The rate of change from the initial state is taken out. In addition, when the multilayer metal foil 9 and the glass epoxy prepreg which is the base material 16 are laminated and the core substrate 17 is formed, vacuum pressing is used, and the pressure is 3 MPa, and the temperature is 175°. C, hold time 1. 5hr (hours). Hereinafter, the present invention will be specifically described by way of examples, but the invention is not limited to the examples. (Example 7) A package substrate including a flip chip terminal having a buried circuit was fabricated in the same manner as in Example 1. Here, at the solder resist formed on the package substrate, an opening is provided, in which the wired/space is configured to be 20 // m/ 20 μm (40 // m pitch) The embedded circuit that becomes the flip chip connection terminal. The length in the longitudinal direction of the flip chip connection terminal (the length of the flip chip connection terminal) defined by the opening of the solder resist is about 1 〇〇 Am. Next, on the buried circuit to be a flip chip connection terminal, solder paste is printed and reflowed to form a preliminary solder. In the solder paste for solder preparation, ECO SOLDER M705 (manufactured by Senju Metal Industry Co., Ltd., trade name, ECOSOLDER is a registered trademark) of Sn (tin)-Ag (silver)-Cu (copper) system is used. In the reflow soldering, an infrared reflow soldering device is used, and the peak temperature is 260 ° C. -44 - 201246414 Next, the cutting process is applied to set the package size. The package substrate of this broken process is generally provided as shown in FIG. 2, and is provided with a buried circuit 2 on which the upper surface is exposed at the surface of the insulating layer 3, and is disposed on the insulating layer 3 and buried. The solder resist 4 is placed in the buried circuit 2 disposed in the solder resist 4 to form a flip chip connection terminal 26» the flip chip connection terminal 26 is used to cover the thickness of the preliminary solder 19~ 5;zm»In this case, the thickness of the solder is HISOMET (manufactured by UNION Optics Co., Ltd., HISOMET is a registered trademark) which is a non-contact machine, and after soldering 19, for solder resist and flip-chip The wafer connection terminals 26 were measured and measured. As shown in Fig. 9, in general, after the package substrate 1 is fabricated, the body element 15 is mounted by flip chip bonding. The flip-chip is formed so that the bump 25 of the flip-chip connection terminal 26 on the package substrate 1 is formed with a bump 25 on the copper pillar (the amount of tin is § (silver)-0. 5 mass% ^ (copper) solder, and the way to the relative height of the section, the height of 25 m), and the alignment, the ultrasonic flip chip bonding machine SH-50MP (ALTECS shares, product name) was carried out Flip-chip connections. The flip-chip bonding condition was performed by using ultrasonic waves on one side and heating up to 50 g of a unit bump of 2300 °C for 4 seconds. The protrusion 25 of the conductor element 15 forms a surface between the surface and the insulating layer 3 of the package substrate 26 having the wafer connection terminal 26, and is filled with the lower portion; the opening 3 1 on the circuit 2 provided with the insulating layer is cut, This degree is measured by the step difference, the step before the formation of the trade name, and the semiconductor wafer is connected to the semiconductor. ····························· Each time, a semiconductor package 24 is obtained by having a flip-chip agent 2 3, -45-201246414. (Example 8) The thickness of the preliminary solder to be coated with the flip chip connection terminal was 7 to 10 / zm. Otherwise, the same as in the seventh embodiment, the tenth circuit substrate and the semiconductor package were obtained. (Example 9) The thickness of the preliminary solder to be coated with the flip chip connection terminal was 17 to 20 μm. Except for this, in the same manner as in the seventh embodiment, a package substrate and a semiconductor package were obtained. [Comparative Example 1] The thickness of the preliminary solder to be coated with the flip chip connection terminal was 1 to 2 μm. Except for this, in the same manner as in Example 7, a package substrate and a semiconductor package were obtained. [Reference Example 1] A package substrate and a semiconductor package were obtained in the same manner as in Example 7 except that the thickness of the preliminary solder to be coated on the flip chip connection terminal was 25 to 28 #m». (Example 1 〇) The same soldering as in the seventh embodiment was carried out on the circuit of the buried wafer connection terminal -46-201246414. Here, as shown in Fig. 5, generally, in the solder resist 4, an opening 3 1 is provided, and in this opening 31, a buried circuit 2 which becomes a flip chip connection terminal 26 is disposed. Further, a through hole 18 is connected to the bottom surface of the buried circuit 2 including the flip chip connection terminal 26. Thereafter, the same as in the seventh embodiment, a package substrate and a semiconductor package were formed. (Example 1 1) By the same method as in Example 4, as shown in Figs. 17 (12) to (14), the second pattern plating 14 was performed on the second carrier metal foil 11, and A portion of the buried circuit that becomes a place for flip chip connection terminals forms a convex shape (stereoscopic circuit). Further, a solder resist is formed and nickel/gold plating (nickel plating and gold plating thereon) as a protective plating is formed. Here, as shown in Fig. 6, generally, at the solder resist 4, an opening 3 1 is provided, and in this opening 31, a buried circuit 2 which is a flip chip connection terminal 26 is disposed. Further, a portion 27 is formed at a portion in the longitudinal direction of the flip-chip connecting terminal 26, and the height of the convex shape 27 is about 5 μm. The range of the convex shape 27 is about 1% of the dimension in the short-side direction of the flip-chip connecting terminal 26, and about 30% of the dimension in the longitudinal direction of the flip-chip connecting terminal 26. Thereafter, the package substrate and the semiconductor package were formed in the same manner as in the seventh embodiment. (Example 1 2) -47-201246414 In the same manner as in Example 1, a package substrate including a flip chip terminal having a buried circuit was fabricated. Thereafter, an etch resist is formed, and a portion of the upper surface of the buried circuit exposed on the upper surface is further recessed as the surface of the insulating layer, and the other portions are etched as they are. Thus, a concave shape is formed. Thereafter, a solder resist is formed and nickel/gold plating (nickel plating and gold plating thereon) as a protective plating is formed. Here, as shown in Fig. 7, generally, at the solder resist 4, an opening 31 is provided, and in this opening 31, a buried circuit 2 which is a flip chip connection terminal 26 is disposed. Further, at a portion in the longitudinal direction of the flip-chip connecting terminal 26, a concave shape 28 is formed, and the depth of the concave shape 28 is about 5 // m. The range of the recessed shape 28 is 100% of the dimension in the short-side direction of the flip-chip connecting terminal 26 and 30% of the dimension in the longitudinal direction of the flip-chip connecting terminal 26. Thereafter, the package substrate and the semiconductor package were formed in the same manner as in the seventh embodiment. (Example 1 3) A package substrate including a flip chip terminal having a buried circuit was produced in the same manner as in Example 7. Here, as shown in Fig. 3, generally, at the solder resist 4, an opening 31 is provided, and in this opening 31, a buried circuit 2 which becomes a flip chip connection terminal 26 is disposed. Further, the front end of the flip chip connection terminal 26 is formed in the opening 3 1 of the solder resist 4. Thereafter, the package substrate and the semiconductor package were formed in the same manner as in the seventh embodiment. -48-201246414 (Example 1 4) A package substrate including a flip chip terminal having a buried circuit was produced in the same manner as in Example 7. Here, as shown in Fig. 4, generally, in the solder resist 4, an opening 3 1 is provided, and in this opening 31, a buried circuit 2 which becomes a flip chip connection terminal 26 is disposed. Further, a buried circuit 2 which is extended on both sides in the longitudinal direction of the flip chip connection terminal 26 or on one side is provided. Thereafter, the same as in the seventh embodiment, a package substrate and a semiconductor package were formed. (Example 1 5) A package substrate including a flip chip terminal having a buried circuit was produced in the same manner as in Example 7. Here, as shown in Fig. 8, generally, at the solder resist 4, an opening 3 is provided, and in this opening 31, a buried circuit 2 which becomes a flip chip connection terminal 26 is disposed. Further, a portion of the longitudinal direction of the flip chip connection terminal 26 is formed with a portion 3 3 which is expanded in the short side direction (wide direction). That is, the flip chip connection terminal 26 is formed with a portion 33 which is partially expanded in the short side direction (wide direction). Thereafter, the same as in the seventh embodiment, a package substrate and a semiconductor package were formed. [Comparative Example 2] A package substrate including a flip chip terminal having a buried circuit was produced in the same manner as in Example 7. Here, as shown in FIG. 16 (14), generally, -49-201246414 is disposed at the opposite side of the surface of the buried circuit 2 on which the flip chip connection terminal is disposed, as shown in FIG. The same circuit pattern (outer layer circuit 7) formed by the convex circuit. Next, a solder resist is formed on the circuit pattern (outer layer circuit 7) formed by the bump circuit, and nickel/gold plating (nickel ore and gold plating thereon) as a protective plating is formed. Here, in the solder resist, an opening is provided, and in this opening, a wire/space of 20 μm / 20 / / m (40 pitch) is formed as a flip chip connection terminal. The circuit pattern formed by the circuit. Next, a circuit pattern formed by a convex circuit is formed as a flip chip connection terminal. On the outer layer circuit 7), a solder paste is printed and reflowed to form a preliminary solder. In the solder paste for solder preparation, the ECOSOLDER M705 (manufactured by Senju Metal Industry Co., Ltd., trade name, ECOSOLDER is a registered trademark) of Sn (tin)-Ag (silver)-Cu (copper) system is used. In the welding, an infrared reflow soldering device is used, and the peak temperature is 260 ° C. Next, a cutting process is applied to set the package size. The package substrate, as shown in FIG. 1, is provided with an insulating layer 3, a circuit pattern formed by the convex circuit 32 disposed at the surface of the insulating layer 3, and disposed on the insulating layer 3. And a solder resist 4 on the circuit pattern formed by the bump circuit 32, and a circuit pattern formed by the bump circuit 32 in the opening 31 provided at the solder resist 4, forming a flip chip Connect the terminal 26. Further, the thickness of the solder 1 9 to be coated by the flip chip connection terminal 26 is 3 to 5 /z m. Thereafter, in the same manner as in Example 7 -50-201246414, a semiconductor package was obtained. [Comparative Example 3] A package substrate and a semiconductor package were obtained in the same manner as in Comparative Example 3 except that the thickness of the preliminary solder to be coated on the flip chip connection terminal was 17 to 20 μm. In Table 2, for the package substrates of Examples 7 to 15, Reference Example 1, and Comparative Examples 1 to 3, the cross-sectional shape of the flip-chip connecting terminal, the thickness of the solder, and the presence or absence of the solder bridging were investigated, and the results were Show. Further, the semiconductor packages of Examples 7 to 15, Reference Example 1, and Comparative Examples 1 to 3 were investigated for the state of the solder paste, and the results were not shown. [Table 2] Item flip chip connection terminal solder thickness (Aim) Circuit pattern cross-sectional shape Ting tin bridge with or without solder paste state Example 7 Buried circuit 3 to 5 Slightly rectangular - fnT- m Good example 8 7 ~10 Μ II Example 9 17~20 II " Comparative Example 1 1~2 不良 Bad reference example 1 25~2 8 Yes " Example 10 3~5 No good embodiment 11 8~1 0 II Example 12 1 3 to 5 " Example 13 J 3 to 5 " Example 141 3 to 5 ” Example 15 3 to 5 II Comparative Example 2 Convex circuit 3 to 5 There is a poor base etching Comparative Example 3 II 1 7 ~ 20 ′′ good-51 - 201246414 According to the observation result of the cross-sectional shape of the flip-chip connecting terminal, it can be seen that in the embodiments 7 to 15, the side surface and the bottom surface of the flip-chip connecting terminal are buried in the insulating layer. The middle part is densely packed, the cross-sectional shape is slightly rectangular, and no base etching is found. On the other hand, in Comparative Examples 2 and 3, since the body was a convex circuit, only the bottom surface of the flip chip connection terminal was in close contact with the insulating layer. Further, in the cross-sectional shape of the flip-chip connecting terminal, the base etching was observed, and in the narrowest portion, it was less than half the width with respect to the top wide (the width of the surface side). According to the measurement results of the thickness of the solder, in the examples 7 to 15, the thickness of the solder was 3 to 20/zm, and according to the result of the solder bridge, it was found that the thickness of the solder did not exist. There is a solder bridge. On the other hand, in Comparative Example 1, the thickness of the solder was 1 to 2/zm and was thin, and there was no occurrence of solder bridging. In Reference Example 1, the thickness of the solder was 25 to 28/zm. Thick, solder bridges occur between adjacent flip-chip connection terminals. In Comparative Example 3, although the thickness of the solder was 17 to 20 " m, since it was a convex circuit, the solder was wound around the side surface of the flip chip connection terminal, and solder bridging occurred. According to the results of the confirmation of the solder paste of the semiconductor package, it was found that in Examples 7 to 15, Reference Example 1, and Comparative Example 3, the static tin material formed between the bumps of the semiconductor element was The solder is wetted and spread between the bumps of the semiconductor element and the flip-chip connection terminals of the package substrate, and the condition is good. On the other hand, in Comparative Examples 1 and 2, the semiconductor device is in the semiconductor device. The bumps or the flip-chip of the package substrate-52-201246414 are part of the connection terminals, and there is a place where the solder wettability is insufficient, and the formation of the solder paste is not sufficient. The cross-sectional shape of the flip chip connection terminal is obtained by making a micro-slice and observing the cross section by a metal microscope. The thickness of the solder on the flip chip connection terminal is HISOMET (manufactured by UNION Optics Co., Ltd., trade name HISOMET is a registered trademark) which is a non-contact step measuring machine, and before and after the formation of the preliminary solder, the solder is used. The step difference between the resist and the flip chip connection terminal was measured and determined. The presence or absence of the solder bridge and the state of the solder paste were confirmed by observing with a solid microscope at 1 〇. BRIEF DESCRIPTION OF THE DRAWINGS [Fig. 1] (a) plan view, (b) A-A' sectional view, (c) B-B' sectional view of the flip chip connection terminal of the prior art package substrate 2] (a) plan view, (b) A-A' sectional view, (c) BB, cross-sectional view of the flip chip connection terminal of the package substrate of the present invention. [Fig. 3] (a) plan view and (b) A-A' cross-sectional view of the flip chip connection terminal of the package substrate of the present invention. [Fig. 4] The flip chip connection terminal of the package substrate of the present invention is adjacent ( a) plan view, (b) A-A' section view, (C) BB, section view. Fig. 5 is a (a) plan view and (b) A-A, cross-sectional view of the flip chip connection terminal of the package substrate of the present invention. Fig. 6 is a (a) plan view and (b) A-A' sectional view of the flip chip connection terminal of the package substrate of the present invention in the vicinity of -53-201246414. Fig. 7 is a (a) plan view and (b) A-A' sectional view of the flip chip connection terminal of the package substrate of the present invention. Fig. 8 is a (a) plan view, (b) A-A' sectional view, and (c) B-B' sectional view of the flip chip connection terminal of the package substrate of the present invention. Fig. 9 is a cross-sectional view showing the vicinity of a packaged flip chip connection terminal of the present invention. Fig. 10 is a cross-sectional view showing a multilayered metal foil used in the present invention. Fig. 11 is a flow chart showing a part of the manufacturing method of the package substrate of the present invention. Fig. 12 is a flow chart showing a part of a method of manufacturing a package substrate of the present invention. Fig. 13 is a flow chart showing a part of a method of manufacturing a package substrate of the present invention. Fig. 14 is a flow chart showing a part of the manufacturing method of the package substrate of the present invention. Fig. 15 is a flow chart showing a part of the manufacturing method of the package substrate of the present invention. Fig. 16 is a flow chart showing a part of a method of manufacturing a package substrate of the present invention. Fig. 17 is a flow chart showing a part of a method of manufacturing a package substrate of the present invention. [Fig. 18] A cross-sectional view of a semiconductor package produced by the method of manufacturing a package substrate of the present invention - 54 - 201246414 [Description of main components] 1: A package substrate or package substrate for mounting a semiconductor element or a first circuit substrate 2: outer circuit or buried circuit 3: insulating layer 4: solder resist 5: interlayer connection 6: inner layer circuit 7: outer layer circuit 8: protective ore. 9: multilayer metal foil 10: first carrier metal foil 1 1 : second carrier metal foil 12 : base metal foil 13 : first pattern plating 14 : second pattern plating 1 5 : semiconductor element 16 : substrate 1 7 : Core substrate 18 : Through hole 1 9 : Prepared solder 20 : Conductor layer 21 = Interlayer connection hole - 55 - 201246414 22 : Laminate 23 : Lower 塡 filling material 24 : Semiconductor package 25 : (on the side of the semiconductor element) Bump 26: Flip-chip connection terminal 27: convex shape or three-dimensional circuit 28: recessed shape 2 9 : sealing material 3 1 : (solder resist) opening 3 2 : convex circuit 3 3 : in the short side direction Work. Expanded part 3 4 : Etch resist 3 5 : Semiconductor component -56-

Claims (1)

201246414 七、申請專利範圍： 1. 一種半導體元件搭載用封裝基板之製造方法，其特 徵爲，具備有： 準備將第1載體金屬箔和第2載體金屬箔以及基底金 屬箔依此順序作了層積之多層金屬箔，並將此多層金屬箔 之基底金屬箔側和基材作層積而形成核心基板之工程；和 在前述多層金屬箔之第1載體金屬箔和第2載體金屬 箔之間，將第1載體金屬箔作物理性剝離之工程；和 在前述核心基板之第2載體金屬箔上，進行第1圖案 鍍敷之工程；和 在包含有前述第1圖案鍍敷之第2載體金屬箔上，形 成絕緣層和導體電路以及層間連接，而形成層積體之工程 :和 在前述多層金屬箔之第2載體金屬箔和基底金屬箔之 間，將前述層積體與前述第2載體金屬箔一同從核心基板 物理性地剝離而分離之工程；和 在前述作了剝離的層積體之第2載體金屬箔上，形成 蝕刻阻劑並進行蝕刻，藉由此來使第1圖案鍍敷從前述層 積體表面之絕緣層露出而形成埋入電路之工程、或者是在 前述層積體表面之第1圖案鍍敷上形成立體電路之工程、 或者是在前述層積體表面之絕緣層上形成立體電路之工程 、或者是在前述層積體表面之第1圖案鍍敷上形成凹陷形 狀之工程。 2. —種半導體元件搭載用封裝基板之製造方法，其特 -57- 201246414 徵爲，具備有： 準備將第1載體金屬箔和第2載體金屬箔以及基底金 屬箔依此順序作了層積之多層金屬箔’並將此多層金屬箔 之基底金屬箔側和基材作層積而形成核心基板之工程；和 在前述多層金屬箔之第1載體金屬箔和第2載體金屬 箔之間，將第1載體金屬箔作物理性剝離之工程：和 在前述核心基板之第2載體金屬箔上’進行第1圖案 鍍敷之工程：和 在包含有前述第1圖案鍍敷之第2載體金屬箔上’形 成絕緣層和導體電路以及層間連接，而形成層積體之工程 :和 在前述多層金屬箔之第2載體金屬箔和基底金屬箔之 間，將前述層積體與載體金屬箔一同從核心基板物理性地 剝離而分離之工程；和 在前述作了剝離的層積體之第2載體金屬箔上，進行 第2圖案鍍敷之工程；和 在進行了前述第2圖案鍍敷之部分以外的第2載體金 屬箔上，形成蝕刻阻劑並進行蝕刻，而將進行了前述第2 圖案鍍敷之部分以及形成了蝕刻阻劑的部分以外之第2載 體金屬箔藉由蝕刻而除去之，藉由此來使第1圖案鍍敷從 前述層積體表面之絕緣層露出而形成埋入電路之工程、或 者是在前述層積體表面之第1圖案鍍敷上形成立體電路之 1程'或者是在前述層積體表面之絕緣層上形成立體電路 之X程 '或者是在前述層積體表面之第丨圖案鍍敷上形成 -58- 201246414 凹陷形狀之工程。 3 .如申請專利範圍第1項或第2項所記載之半導體元 件搭載用封裝基板之製造方法，其中，在包含第1圖案鍍 敷之第2載體金屬箔上，形成絕緣體和導體電路以及層間 連接，而形成層積體之工程、和在多層金屬箔之第2載體 金屬箔和基底金屬箔之間，將前述層積體與第2載體金屬 箔一同從核心基板物理性地剝離並分離之工程，此兩者之 工程之間，係具備有：形成所期望之層數的絕緣層和導體 電路之工程。 4. 如申請專利範圍第1〜3項中之任一項所記載之半 導體元件搭載用封裝基板之製造方法，其中，在使第1圖 案鍍敷從層積體表面之絕緣層露出並形成埋入電路之工程 中，係形成倒裝晶片連接端子，在於層積體表面之第1圖 案鍍敷上形成立體電路之工程中，係形成柱（pillar )或 者是在倒裝晶片連接端子之長邊方向的一部份處形成凸形 狀，在於層積體表面之絕緣層上形成立體電路之工程中， 係形成假端子。 5. —種半導體元件搭載用封裝基板，係爲藉由如申請 專利範圍第1〜4項中之任一項所記載之半導體元件搭載 用封裝基板之製造方法製造出的半導體元件搭載用封裝基 板，其特徵爲，係具備有： 絕緣層；和 以使上表面露出於此絕緣層之表面處的方式而設置之 埋入電路；和 -59- 201246414 被設置在前述絕緣層上以及埋入電路上之銲料阻劑， 被配置在此銲料阻劑之開口內的埋入電路，係形成倒 裝晶片連接端子，此倒裝晶片連接端子，係經由厚度3 y m 以上之預備銲錫而被覆。 6 ·如申請專利範圍第5項所記載之半導體元件搭載用 封裝基板，其中，在形成倒裝晶片連接端子之埋入電路的 底面處，係連接有通孔。 7 ·如申請專利範圍第5項或第6項所記載之半導體元 件搭載用封裝基板，其中，在倒裝晶片連接端子之長邊方 向的一部份處，係被形成有凸形狀。 8 .如申請專利範圍第5〜7項中之任一項所記載之半 導體元件搭載用封裝基板，其中，在倒裝晶片連接端子之 長邊方向的一部份處，係被形成有凹陷形狀。 9.如申請專利範圍第5〜8項中之任一項所記載之半 導體元件搭載用封裝基板，其中，倒裝晶片連接端子之前 端，係被配置於銲料阻劑之開口內。 1 〇.如申請專利範圍第5〜9項中之任一項所記載之半 導體元件搭載用封裝基板，其中，係設置有具備在倒裝晶 片連接端子之長邊方向的兩側或者是單側處而作了延長的 部分之埋入電路。 1 1.如申請專利範圍第5〜1 0項中之任一項所記載之 半導體元件搭載用封裝基板，其中，倒裝晶片連接端子之 一部份，係在短邊方向上被作了擴張。 12.—種半導體封裝，其特徵爲：係在如申請專利範 -60- 201246414 圍第5〜1 1項中之任一項所記載之半導體元件搭載用封裝 基板的倒裝晶片連接端子上，藉由倒裝晶片連接而搭載有 半導體元件之突塊。 -61 -201246414 VII. Patent application scope: 1. A method of manufacturing a package substrate for mounting a semiconductor element, comprising: preparing a layer of the first carrier metal foil, the second carrier metal foil, and the base metal foil in this order a multilayer metal foil, and a process of forming a core substrate by laminating a base metal foil side of the multilayer metal foil and a substrate; and between the first carrier metal foil and the second carrier metal foil of the multilayer metal foil a process of rationally stripping the first carrier metal foil; and performing a first pattern plating on the second carrier metal foil of the core substrate; and a second carrier metal including the first pattern plating Forming an insulating layer, a conductor circuit, and an interlayer connection on the foil to form a laminate: and the laminate and the second carrier between the second carrier metal foil and the base metal foil of the multilayer metal foil a process in which the metal foil is physically separated from the core substrate and separated; and an etching resist is formed on the second carrier metal foil of the laminate which has been peeled off By engraving, the first pattern plating is exposed from the insulating layer on the surface of the laminate to form a buried circuit, or the third pattern is formed on the first pattern plating on the surface of the laminate. Or a process of forming a three-dimensional circuit on the insulating layer on the surface of the laminate or a process of forming a concave shape on the first pattern plating on the surface of the laminate. 2. A method of manufacturing a package substrate for mounting a semiconductor element, which is characterized in that: the first carrier metal foil, the second carrier metal foil, and the base metal foil are prepared in this order. a multilayer metal foil ′ and a process of forming a core substrate by laminating a base metal foil side of the multilayer metal foil and a substrate; and between the first carrier metal foil and the second carrier metal foil of the multilayer metal foil; The first carrier metal foil is rationally peeled off from the crop: and the first pattern plating is performed on the second carrier metal foil of the core substrate: and the second carrier metal foil including the first pattern plating The process of forming an insulating layer and a conductor circuit and interlayer connection to form a laminate: and the second laminate metal foil and the base metal foil of the multilayer metal foil, the laminate and the carrier metal foil are a process in which the core substrate is physically peeled off and separated; and a second pattern metal plating on the second carrier metal foil of the laminated body which has been peeled off; and (2) a second carrier metal foil other than the portion where the second pattern is plated and the portion where the etching resist is formed, by forming an etching resist on the second carrier metal foil other than the pattern plating portion and etching the etching film. By removing by etching, the first pattern plating is exposed from the insulating layer on the surface of the laminate to form a buried circuit, or the first pattern plating on the surface of the laminate is performed. The process of forming a three-dimensional circuit 'either the X-path of forming a three-dimensional circuit on the insulating layer on the surface of the laminated body or the forming of the concave shape of the -58-201246414 on the second pattern plating on the surface of the laminated body . The method of manufacturing a package substrate for mounting a semiconductor device according to the first aspect of the invention, wherein the insulator, the conductor circuit, and the interlayer are formed on the second carrier metal foil including the first pattern plating. The process of forming a laminate and connecting the second carrier metal foil and the base metal foil of the multilayer metal foil, physically separating and separating the laminate and the second carrier metal foil from the core substrate Engineering, between the two projects, has the engineering of forming an insulating layer and a conductor circuit of a desired number of layers. 4. The method of manufacturing a package substrate for mounting a semiconductor element according to any one of the first aspect of the present invention, wherein the first pattern plating is exposed from the insulating layer on the surface of the laminate to form a buried pattern. In the engineering of the circuit, a flip chip connection terminal is formed, and in the process of forming a three-dimensional circuit on the first pattern plating on the surface of the laminate, a pillar is formed or a long side of the flip chip connection terminal is formed. A portion of the direction is formed into a convex shape, and a dummy terminal is formed in the process of forming a three-dimensional circuit on the insulating layer on the surface of the laminate. The semiconductor device mounting package substrate manufactured by the method for manufacturing a semiconductor device mounting package substrate according to any one of the first to fourth aspects of the invention And characterized in that: an insulating layer; and a buried circuit provided in such a manner that an upper surface is exposed at a surface of the insulating layer; and -59-201246414 is disposed on the insulating layer and buried in the circuit The solder resist is disposed in the buried circuit in the opening of the solder resist to form a flip chip connection terminal, and the flip chip connection terminal is covered by a preliminary solder having a thickness of 3 μm or more. The package substrate for mounting a semiconductor element according to the fifth aspect of the invention, wherein a through hole is connected to a bottom surface of the buried circuit in which the flip chip connection terminal is formed. The package substrate for mounting a semiconductor element according to the fifth aspect or the sixth aspect of the invention, wherein a part of the longitudinal direction of the flip chip connection terminal is formed in a convex shape. The package substrate for mounting a semiconductor element according to any one of the fifth aspect of the invention, wherein a part of the longitudinal direction of the flip chip connection terminal is formed in a concave shape. . The package substrate for mounting a semiconductor element according to any one of claims 5 to 8, wherein the front end of the flip chip connection terminal is disposed in the opening of the solder resist. The package substrate for mounting a semiconductor element according to any one of the items of the present invention, wherein the package substrate is provided on both sides or one side in the longitudinal direction of the flip chip connection terminal. The buried part of the extended part was made. 1. The package substrate for mounting a semiconductor element according to any one of the fifth aspect of the invention, wherein the flip chip connection terminal is expanded in the short side direction. . A flip-chip connection terminal for a package substrate for mounting a semiconductor element according to any one of the items 5 to 11 of the above-mentioned application, A bump of a semiconductor element is mounted by flip chip bonding. -61 -
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI551438B (en) * 2014-03-26 2016-10-01 Jx Nippon Mining & Metals Corp Laminate composed of a resin and a metal layer made of a plate-shaped carrier
TWI584701B (en) * 2013-11-22 2017-05-21 Mitsui Mining & Smelting Co A supporting substrate having a circuit forming layer, a supporting substrate having a double-sided circuit forming layer, a multilayer laminated sheet, a method for manufacturing the multilayer printed wiring board, and a multilayer printed wiring board
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Families Citing this family (4)

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Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10242328A (en) * 1997-02-28 1998-09-11 Toshiba Corp Circuit board, circuit module having the circuit board and electronic equipment having the circuit module
JP3420076B2 (en) * 1998-08-31 2003-06-23 新光電気工業株式会社 Method for manufacturing flip-chip mounting board, flip-chip mounting board, and flip-chip mounting structure
JP2002052614A (en) * 2000-08-11 2002-02-19 Kanegafuchi Chem Ind Co Ltd Method for manufacturing laminated sheet
TWI223577B (en) * 1999-11-01 2004-11-01 Kaneka Corp Manufacturing method and manufacturing apparatus of laminated plate
JP2004253648A (en) * 2003-02-20 2004-09-09 Sumitomo Bakelite Co Ltd Printed circuit board and method for manufacturing the same, and multi-layer printed wiring board and method for manufacturing the same
JP4863076B2 (en) * 2006-12-28 2012-01-25 凸版印刷株式会社 Wiring board and manufacturing method thereof
JP4343236B2 (en) * 2007-03-30 2009-10-14 シャープ株式会社 Circuit board and method for forming circuit board
KR100966336B1 (en) * 2008-04-07 2010-06-28 삼성전기주식회사 High density substrate and manufacturing method thereof
JP2009289868A (en) * 2008-05-28 2009-12-10 Kyocer Slc Technologies Corp Wiring substrate and its manufacturing method
US8153905B2 (en) * 2009-02-27 2012-04-10 Ibiden Co., Ltd. Method for manufacturing printed wiring board and printed wiring board

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI584701B (en) * 2013-11-22 2017-05-21 Mitsui Mining & Smelting Co A supporting substrate having a circuit forming layer, a supporting substrate having a double-sided circuit forming layer, a multilayer laminated sheet, a method for manufacturing the multilayer printed wiring board, and a multilayer printed wiring board
TWI551438B (en) * 2014-03-26 2016-10-01 Jx Nippon Mining & Metals Corp Laminate composed of a resin and a metal layer made of a plate-shaped carrier
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WO2012121373A1 (en) 2012-09-13

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