TWI715485B - Circuit structure for improving pin glass strength in cof-ic packaging process - Google Patents
Circuit structure for improving pin glass strength in cof-ic packaging process Download PDFInfo
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Abstract
Description
本發明係關於覆晶薄膜技術領域,尤其涉及提高COF-IC封裝過程中引腳剝離強度的線路結構技術領域。 The present invention relates to the technical field of flip-chip films, and in particular to the technical field of circuit structures for improving the peel strength of pins in the COF-IC packaging process.
COF-IC封裝指使用內引腳壓焊設備對載帶上超細線路線路與顯示驅動晶片接腳在特定條件下進行壓焊,實現COF-IC封裝。 COF-IC packaging refers to the use of internal pin pressure welding equipment to pressure welding the ultra-fine circuit lines on the carrier tape and the pins of the display driver chip under specific conditions to achieve COF-IC packaging.
加工時,一方面由於超細線路的線寬小於10微米,導致線路與柔性基材的接觸面積受限,同時線路寬度受空間影響無法進行調整,另一方面晶片接腳間距細小且密集,線路與晶片接腳接合強度受限;還會受到線路加工過程中側蝕現象的影響,銅線焊接區域線路端頭往往不規整或側蝕嚴重,破壞壓焊後銅線對柔性基材的附著力,導致良率下降、產品壽命減小和電氣性能指標降低;易受到載帶線路加工過程、壓焊加工過程中機械因素、化學因素和物理因素的破壞,這種破壞容易在銅線與基材連接的邊緣部位產生,特別是在引腳部產生破壞,引腳部及邊緣區域應力集中往往導致尖端表面能過大,使該區域銅線的引腳容易與基材之間產生開裂並向內部的銅線遷移,最終造成銅線斷裂或銅線剝離基材,進而造成電路斷路或短路的情況發生。 During processing, on the one hand, the line width of the ultra-fine line is less than 10 microns, which results in the limited contact area between the line and the flexible substrate. At the same time, the line width cannot be adjusted due to the influence of space. On the other hand, the chip pin spacing is small and dense. The bonding strength with the chip pins is limited; it will also be affected by the side corrosion phenomenon during the circuit processing. The wire ends in the copper wire welding area are often irregular or severely side corroded, which damages the adhesion of the copper wire to the flexible substrate after pressure welding , Resulting in a decrease in yield, a decrease in product life and a decrease in electrical performance indicators; it is easily damaged by mechanical factors, chemical factors and physical factors during the processing of the carrier tape line and the pressure welding process. This damage is likely to occur on the copper wire and the substrate. The edge part of the connection occurs, especially the lead part. The stress concentration in the lead part and the edge area often leads to excessive surface energy of the tip, which makes the lead of the copper wire in this area easy to crack between the base material and the inner part. The migration of the copper wire will eventually cause the copper wire to break or the copper wire to peel off the substrate, which in turn causes the circuit to be broken or short-circuited.
為克服現有技術中存在的銅線對柔性基材附著強度微小,容易受到後續加工影響造成銅線斷裂或銅線剝離基材,而造成電路斷路或短路的問題,本發明揭露了一種提高COF-IC封裝過程中引腳剝離強度的線路結構。 In order to overcome the problem that the copper wire in the prior art has low adhesion strength to the flexible substrate, and is easily affected by subsequent processing, the copper wire is broken or the copper wire peels off the substrate, which causes the circuit to be broken or short-circuited, the present invention discloses a method for improving COF- Circuit structure of pin peel strength during IC packaging.
本發明透過以下技術方案實現上述目的:一種提高COF-IC封裝過程中引腳剝離強度的線路結構,其中,包括銅線、柔性基材和IC晶片,銅線附著在柔性基材上,IC晶片的接腳透過壓焊方式與銅線的引腳固定連接,銅線的引腳位於銅線的端部,銅線的引腳包括長引腳和短引腳,長引腳和短引腳間隔佈置,長引腳的形狀結構與銅線的形狀結構不同。其中長引腳和短引腳的形狀結構相同。 The present invention achieves the above objectives through the following technical solutions: a circuit structure for improving the peeling strength of pins in the COF-IC packaging process, which includes copper wires, flexible substrates and IC chips. The copper wires are attached to the flexible substrate and the IC chips The pins of the copper wire are fixedly connected to the pins of the copper wire by pressure welding. The pins of the copper wire are located at the end of the copper wire. The pins of the copper wire include long and short pins, and the distance between long and short pins Layout, the shape and structure of the long pin is different from that of the copper wire. The shape and structure of the long pin and the short pin are the same.
所述之提高COF-IC封裝過程中引腳剝離強度的線路結構,其中,長引腳或/和短引腳上端固定設置有線盤,線盤為圓形、橢圓形、長條形、塊狀結構中的一種或多種。 The circuit structure for improving the peeling strength of the pins in the COF-IC packaging process, wherein a wire reel is fixed at the upper end of the long pin or/and the short pin, and the wire reel is round, oval, long, and block-shaped One or more of the structures.
所述之提高COF-IC封裝過程中引腳剝離強度的線路結構,其中,IC長引腳壓接區上部分的銅線上設置有線盤,線盤為圓形、橢圓形、長條形、塊狀結構中的一種或多種。 The circuit structure for improving the peeling strength of the pins in the COF-IC packaging process, wherein a wire reel is arranged on the upper part of the copper wire in the crimping area of the long IC pin, and the wire reel is round, oval, long, and block One or more of the shape structure.
所述之提高COF-IC封裝過程中引腳剝離強度的線路結構,其中,長引腳為波浪形結構。 In the circuit structure for improving the peeling strength of the pins in the COF-IC packaging process, the long pins have a wave-shaped structure.
所述之提高COF-IC封裝過程中引腳剝離強度的線路結構,其中,長引腳為分段式塊狀結構。 In the circuit structure for improving the peeling strength of the pins in the COF-IC packaging process, the long pins have a segmented block structure.
所述之提高COF-IC封裝過程中引腳剝離強度的線路結構,其中,長引腳為點陣式結構。 In the circuit structure for improving the peeling strength of the pins in the COF-IC packaging process, the long pins have a dot matrix structure.
所述之提高COF-IC封裝過程中引腳剝離強度的線路結構,其中,長引腳為多條平行的波浪形結構。 In the circuit structure for improving the peel strength of pins in the COF-IC packaging process, the long pins are multiple parallel wave-shaped structures.
所述之提高COF-IC封裝過程中引腳剝離強度的線路結構,其中,長引腳為兩側向外延伸的“丰”字型結構。 In the circuit structure for improving the peeling strength of the pins during the COF-IC packaging process, the long pins have a "feng" structure extending outward on both sides.
與現有技術相比,本發明的有益效果是:本發明透過將IC晶片的接腳和銅線的引腳相壓接,透過改變銅線的引腳與柔性基材連接處的邊緣形狀,改善了銅線的引腳與柔性基材單一結合區域因外部載荷、溫度應力、殘餘應力帶來塑性變形、裂痕源產生的應力過分集中和組織不均勻的問題;透過設置線盤,進一步加強了銅線引腳的頭部與柔性基材的結合強度;增強了線路與柔性基材的附著力強度;改善了封裝環節產品良率;提升了產品壽命;同時將銅線的引腳和線盤設計成不同形狀並進行不同組合,提供了不同設計方案以滿足不同的線路結合強度要求。 Compared with the prior art, the present invention has the beneficial effects that: the present invention improves the shape of the edge of the joint between the copper wire pin and the flexible substrate by crimping the IC chip pin and the copper wire pin. The single bonding area of the lead of the copper wire and the flexible substrate is caused by external load, temperature stress, residual stress, plastic deformation, excessive stress generated by the crack source, and uneven structure; the copper wire is further strengthened by setting the wire reel The bonding strength between the head of the pin and the flexible substrate; enhances the adhesion strength between the circuit and the flexible substrate; improves the product yield of the packaging process; enhances the product life; at the same time, the copper wire pins and wire reels are designed into Different shapes and different combinations provide different design schemes to meet different line bonding strength requirements.
1:銅線 1: Copper wire
2:柔性基材 2: Flexible substrate
3:長引腳 3: Long pin
4:線盤 4: Bobbin
31:短引腳 31: short pin
圖1是本發明實施例1的結構示意圖;圖2是本發明實施例2的結構示意圖;圖3是本發明實施例3的結構示意圖;圖4是本發明實施例4的結構示意圖;圖5是本發明實施例5的結構示意圖;圖6是本發明實施例6的結構示意圖;圖7是本發明實施例7的結構示意圖;圖8是本發明實施例8的結構示意圖;圖9是本發明實施例9的結構示意圖;圖10是本發明實施例10的結構示意圖;
圖11是本發明實施例11的結構示意圖;圖12是本發明實施例12的結構示意圖;圖13是本發明實施例13的結構示意圖;圖14是本發明實施例14的結構示意圖。
Figure 1 is a schematic structural diagram of
以下結合圖式和實施例,對本發明進行進一步詳細說明。應可理解,此處所描述的具體實施例僅用以解釋本發明,並不用於限定本發明。 The following describes the present invention in further detail in conjunction with the drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, but not used to limit the present invention.
實施例1,如圖1所示,銅線1附著在柔性基材2上,IC晶片的接腳透過壓焊方式與銅線1的引腳固定連接,銅線1的引腳位於銅線1的端部,銅線1的引腳包括長引腳3和短引腳31,長引腳3和短引腳31間隔佈置,長引腳3與銅線1結構相同,為長條狀;短引腳31與銅線1結構相同,為長條狀;長引腳3上端固定設置有線盤4,所述線盤4為橢圓形。
Example 1, as shown in Figure 1, the
實施例2,如圖2所示,銅線1附著在柔性基材2上,IC晶片的接腳透過壓焊方式與銅線1的引腳固定連接,銅線1的引腳位於銅線1的端部,銅線1的引腳包括長引腳3和短引腳31,長引腳3和短引腳31間隔佈置;短引腳31與銅線1結構相同,為長條狀;長引腳3為兩側向外延伸的“丰”字型結構,延伸部位為橢圓形。
In
實施例3,如圖3所示,實施例3主要結構與實施例2相同,區別在於:長引腳3為波浪形結構。
實施例4,如圖4所示,實施例4主要結構與實施例2相同,區別在於:長引腳3為分段式塊狀結構。
實施例5,如圖5所示,實施例5主要結構與實施例2相同,區別在於:長引腳3為點陣式結構。
Embodiment 5, as shown in FIG. 5, the main structure of Embodiment 5 is the same as
實施例6,如圖6所示,實施例6主要結構與實施例2相同,區別在於:長引腳3為多條平行的波浪形結構。
Embodiment 6, as shown in FIG. 6, the main structure of Embodiment 6 is the same as
實施例7,如圖7所示,實施例7主要結構與實施例2相同,區別在於:長引腳3與短引腳31均為兩側向外延伸的“丰”字型結構,延伸部位為橢圓形。
Embodiment 7, as shown in FIG. 7, the main structure of embodiment 7 is the same as that of
實施例8,如圖8所示,實施例8主要結構與實施例7相同,區別在於:長引腳3與短引腳31均為波浪形結構。
Embodiment 8, as shown in FIG. 8, the main structure of Embodiment 8 is the same as that of Embodiment 7, except that the
實施例9,如圖9所示,實施例9主要結構與實施例7相同,區別在於:長引腳3與短引腳31均為分段式塊狀結構。
Embodiment 9, as shown in FIG. 9, the main structure of embodiment 9 is the same as that of embodiment 7, except that the
實施例10,如圖10所示,實施例10主要結構與實施例7相同,區別在於:長引腳3與短引腳31均為點陣式結構。
In Embodiment 10, as shown in FIG. 10, the main structure of Embodiment 10 is the same as that in Embodiment 7, except that the
實施例11,如圖11所示,實施例11主要結構與實施例7相同,區別在於:長引腳3與短引腳31均為多條平行的波浪形結構。
In Embodiment 11, as shown in FIG. 11, the main structure of Embodiment 11 is the same as that in Embodiment 7, except that the
實施例12,如圖12所示,實施例12主要結構與實施例8相同,區別在於:長引腳3上端固定設置有線盤4,線盤4為橢圓形結構。
Embodiment 12, as shown in FIG. 12, the main structure of Embodiment 12 is the same as that of Embodiment 8, except that a
實施例13,如圖13所示,實施例13主要結構與實施例7相同,區別在於:短引腳31為兩側向外延伸的“丰”字型結構,延伸部位為橢圓形;長引腳3為兩側向外延伸的“丰”字型結構,延伸部位為長條形,且長引腳3上端固定設置有線盤4,線盤4為橢圓形結構。
Embodiment 13, as shown in FIG. 13, the main structure of embodiment 13 is the same as that of embodiment 7, the difference is: the
實施例14,如圖14所示,實施例14主要結構與實施例11相同,區別在於:長引腳3上端固定設置有線盤4,線盤4為為橢圓形結構;短引腳31上端固定設置有線盤4,線盤4為塊狀結構。
Embodiment 14, as shown in FIG. 14, the main structure of embodiment 14 is the same as that of embodiment 11, except that: the upper end of the
綜上所述,由於IC晶片凸出於柔性基材2,IC晶片在封裝過程中常常容易受到外界各種因素(加工、運輸等操作)的影響,受到外力影響之後,與IC晶片的接腳相壓接的銅線1的引腳常常會被剝離柔性基材2。從表1看出本發明透過改變長引腳3和短引腳31的線路結構,使得長引腳3和短引腳31的邊緣不再是直線,當長引腳3或短引腳31與柔性基材2相連處出現裂紋時,一方面,不規則的邊緣使的裂紋分叉,緩和了裂紋尖端的應力集中,另一方面,不規則的邊緣對封裝過程中受到的外力進行了分散,從而提高了銅線1與柔性基材2的剝離強度。
In summary, because the IC chip protrudes from the
上述說明示出並描述了本發明的較佳實施例,如前所述,應當理解本發明並非局限於本文所揭露的形式,不應看作是對其他實施例的排除,而可用於各種其他組合、修改和環境,並能夠在本文所述發明構想範圍內,透過上述說明或相關領域的技術或知識進行改動。而本領域通常知識者所進行的改動和變化不脫離本發明的精神和範圍,則都應在本發明所附專利申請範圍的保護範圍內。 The above description shows and describes the preferred embodiments of the present invention. As mentioned above, it should be understood that the present invention is not limited to the form disclosed herein, and should not be regarded as the exclusion of other embodiments, but can be applied to various other embodiments. Combinations, modifications and environments can be modified through the above description or technology or knowledge in related fields within the scope of the inventive concept described herein. The modifications and changes made by those skilled in the art do not depart from the spirit and scope of the present invention, and should fall within the protection scope of the attached patent application of the present invention.
1:銅線 1: Copper wire
2:柔性基材 2: Flexible substrate
3:長引腳 3: Long pin
4:線盤 4: Bobbin
31:短引腳 31: short pin
Claims (7)
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Citations (3)
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TW493362B (en) * | 1999-03-16 | 2002-07-01 | Casio Computer Co Ltd | Electronic component connection terminal construction |
TW201246414A (en) * | 2011-03-09 | 2012-11-16 | Hitachi Chemical Co Ltd | Method for producing package substrate for mounting semiconductor element, package substrate for mounting semiconductor element, and semiconductor package |
TW201806458A (en) * | 2016-03-17 | 2018-02-16 | 東麗工程股份有限公司 | Flexible circuit board and method for manufacturing the same |
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TW493362B (en) * | 1999-03-16 | 2002-07-01 | Casio Computer Co Ltd | Electronic component connection terminal construction |
TW201246414A (en) * | 2011-03-09 | 2012-11-16 | Hitachi Chemical Co Ltd | Method for producing package substrate for mounting semiconductor element, package substrate for mounting semiconductor element, and semiconductor package |
TW201806458A (en) * | 2016-03-17 | 2018-02-16 | 東麗工程股份有限公司 | Flexible circuit board and method for manufacturing the same |
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