JP5034885B2 - Electronic device and method of manufacturing the same - Google Patents

Electronic device and method of manufacturing the same Download PDF

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JP5034885B2
JP5034885B2 JP2007295939A JP2007295939A JP5034885B2 JP 5034885 B2 JP5034885 B2 JP 5034885B2 JP 2007295939 A JP2007295939 A JP 2007295939A JP 2007295939 A JP2007295939 A JP 2007295939A JP 5034885 B2 JP5034885 B2 JP 5034885B2
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conductive film
electrode
stress
film
electronic device
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JP2009123898A (en
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泰治 酒井
俊也 赤松
大輔 水谷
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Fujitsu Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector

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  • Wire Bonding (AREA)

Description

本発明は、電子装置とその電子装置の製造方法に関する。   The present invention relates to an electronic device and a method for manufacturing the electronic device.

近年、携帯電話のような携帯機器市場における機器の小型化の要求に伴い、半導体素子を高密度で実装する要求が高まっている。この要求を叶えるべく、半導体素子をフェイスダウンで接続電極を介して回路基板に接続し、狭ピッチと多ピン化を可能とするフリップチップ接合が多用されている。   In recent years, with the demand for miniaturization of devices in the mobile device market such as mobile phones, there is an increasing demand for mounting semiconductor elements at high density. In order to meet this demand, flip-chip bonding is often used in which a semiconductor element is connected face-down to a circuit board via a connection electrode, and a narrow pitch and a large number of pins can be realized.

このフリップチップ接合が進展する一方で、有機樹脂を主体とする回路基板と、シリコンを主体とする半導体素子との熱膨張率差に起因する応力により、接続電極或いは半導体素子内部にクラックが発生し、接続信頼性が低下するという問題がある。   While this flip chip bonding progresses, cracks are generated in the connection electrode or the semiconductor element due to the stress caused by the difference in thermal expansion coefficient between the circuit board mainly composed of organic resin and the semiconductor element mainly composed of silicon. There is a problem that connection reliability is lowered.

このような回路基板と半導体素子との熱膨張率差を緩和するために、様々な応力緩和構造が提案されている。   In order to relieve the difference in thermal expansion coefficient between the circuit board and the semiconductor element, various stress relaxation structures have been proposed.

例えば、特許文献1では、表面に凹凸が形成された加工基板上にレジストパターンを形成し、そのレジストパターンの窓から露出する加工基板上に、上記の凹凸を反映した屈曲部を備えた微小な導電性接続部を形成して、その導電性接続部で半導体素子と回路基板とを接続する応力緩和構造が提案されている。この構造によれば、熱膨張率差に起因した応力が導電性接続部の屈曲部により緩和されることになる。   For example, in Patent Document 1, a resist pattern is formed on a processed substrate having a concavo-convex surface, and a minute portion having a bent portion reflecting the concavo-convex shape is formed on the processed substrate exposed from the resist pattern window. There has been proposed a stress relaxation structure in which a conductive connection portion is formed and a semiconductor element and a circuit board are connected by the conductive connection portion. According to this structure, the stress caused by the difference in thermal expansion coefficient is relieved by the bent portion of the conductive connection portion.

しかしながら、この導電性接続部を形成するのに必要な加工基板は、製作コストが高いため、導電性接続部の製造コストを抑えるために繰り返し使用する必要がある。そのため、導電性接続部が加工基板から剥離し易くするための離形材の処理等を管理、維持するコストが高くなるという問題がある。   However, the processed substrate necessary for forming the conductive connection portion has a high manufacturing cost, and therefore needs to be repeatedly used in order to reduce the manufacturing cost of the conductive connection portion. Therefore, there exists a problem that the cost which manages and maintains the process etc. of the mold release material for making it easy to peel an electroconductive connection part from a process board | substrate increases.

また、加工基板の表面に凹凸が形成されているため、加工基板上に塗布されたフォトレジストに十分な平坦性が得られず、露光工程においてフォーカスずれが発生し易くなり、微細なレジストパターンを形成するのが困難となる。   In addition, since unevenness is formed on the surface of the processed substrate, sufficient flatness cannot be obtained in the photoresist applied on the processed substrate, and it becomes easy for focus shift to occur in the exposure process, and a fine resist pattern is formed. It becomes difficult to form.

これに対し、特許文献2では、S字状のリードで回路基板と半導体素子とを接続し、そのリードで応力を緩和する応力緩和構造が提案されている。   On the other hand, Patent Document 2 proposes a stress relaxation structure in which a circuit board and a semiconductor element are connected by an S-shaped lead and stress is relaxed by the lead.

しかし、この方法では、S字状のリードとその先端のスポットとを形成するのに露光工程が2回必要となり、工程数が多いという問題がある。更に、そのリードの両端に端子を形成するためにアンダーエッチングを用いているので、エッチング時間等の厳密な制御が必要になると供に、任意形状の端子を形成することができないという不都合もある。   However, this method has a problem that the number of steps is large because two exposure steps are required to form the S-shaped lead and the spot at the tip thereof. Further, since under-etching is used to form terminals at both ends of the lead, there is a disadvantage that a terminal having an arbitrary shape cannot be formed as well as the need to strictly control the etching time and the like.

その他に、バネ性が付与されたワイヤバンプにより回路基板と半導体素子とを接続する構造もあるが、この構造ではワイヤバンプを一個ずつ形成していかなければならないため時間がかかる上に、微小なワイヤを狭ピッチで配列させるのが技術的に困難であるという問題がある。   In addition, there is a structure in which the circuit board and the semiconductor element are connected by wire bumps with spring properties. In this structure, it is necessary to form the wire bumps one by one. There is a problem that it is technically difficult to arrange them at a narrow pitch.

なお、この他にも、本発明に関連する技術が下記の特許文献3〜4にも開示される。
特開2003−188209号公報 特開平10−256314号公報 特許第2986095号明細書 特開平6−268017号公報 特開2005−166739号公報
In addition to this, techniques related to the present invention are also disclosed in the following Patent Documents 3 to 4.
JP 2003-188209 A JP-A-10-256314 Japanese Patent No. 2986095 JP-A-6-268017 Japanese Patent Laid-Open No. 2005-166739

本発明の目的は、電子部品と基板との応力差を簡単に緩和できる電子装置とその製造方法を提供することにある。   An object of the present invention is to provide an electronic device that can easily relieve a stress difference between an electronic component and a substrate, and a manufacturing method thereof.

本発明の一観点によれば、第1面に第1電極が形成された回路基板と、第1面に第2電極が形成された電子部品と、互いに応力の異なる第1導電膜と第2導電膜とを積層してなり、前記第1電極と前記第2電極とを電気的に接続する積層体とを有し、前記第1導電膜と前記第2導電膜とは共に同じ材料で構成され、且つ前記第1導電膜と前記第2導電膜とは互いに異なるめっき条件で形成されて、前記第1導電膜の応力は引張応力であり、前記第2導電膜の応力は圧縮応力であり、前記回路基板の前記第1面と前記電子部品の前記第1面とが互いに向き合うように前記回路基板と前記電子部品とを配置させ、前記第2導電膜を外側にして前記積層体を弧状に湾曲させて、該第2導電膜の一方の端部を前記第1電極に接合し、該第2導電膜の他方の端部を前記第2電極に接合した電子装置が提供される。 According to one aspect of the present invention, a circuit board having a first electrode formed on a first surface, an electronic component having a second electrode formed on a first surface, a first conductive film and a second stress having different stresses from each other. A conductive film is laminated, and has a laminated body that electrically connects the first electrode and the second electrode, and both the first conductive film and the second conductive film are made of the same material. In addition, the first conductive film and the second conductive film are formed under different plating conditions, the stress of the first conductive film is tensile stress, and the stress of the second conductive film is compressive stress. The circuit board and the electronic component are arranged so that the first surface of the circuit board and the first surface of the electronic component face each other, and the stacked body is formed in an arc shape with the second conductive film outside. And bending one end of the second conductive film to the first electrode, and the other of the second conductive film Electronic device the end joined to the second electrode is provided.

また、本発明の別の観点によれば、ベース基板の上に、互いに応力の異なる第1導電膜と第2導電膜をこの順に積層してなる積層体を形成する工程と、基板の第1電極に、前記第2導電膜の一方の端部を接合する工程と、前記接合の後、前記ベース基板から前記積層体を剥離し、前記応力の違いにより前記積層体を湾曲させる工程と、電子部品の第2電極に、前記第2導電膜の他方の端部を接合する工程とを有する電子装置の製造方法が提供される。   According to another aspect of the present invention, a step of forming a laminated body formed by laminating a first conductive film and a second conductive film having different stresses in this order on a base substrate, and a first substrate Bonding one end of the second conductive film to the electrode, peeling the laminated body from the base substrate after the bonding, bending the laminated body due to the difference in stress, and electrons There is provided a method of manufacturing an electronic device including a step of bonding the other end of the second conductive film to a second electrode of a component.

本発明によれば、第1、第2導電膜の内部応力の違いにより自然に湾曲した積層体により、電子部品と回路基板との熱膨張率差に起因した応力が緩和され、電子部品等にクラックが入る危険性を低減でき、電子部品と回路基板との接続信頼性が向上する。   According to the present invention, the stress caused by the difference in thermal expansion coefficient between the electronic component and the circuit board is relieved by the laminate that is naturally curved due to the difference in internal stress between the first and second conductive films, and the electronic component or the like The risk of cracking can be reduced, and the connection reliability between the electronic component and the circuit board is improved.

しかも、その積層体は、第1、第2導電膜の内部応力の違いによって自然に湾曲するので、積層体を湾曲させるための特別な装置が不要で、接続構造を低コストで簡単に得ることができる。   Moreover, since the laminate naturally curves due to the difference in internal stress between the first and second conductive films, a special device for curving the laminate is unnecessary, and a connection structure can be easily obtained at low cost. Can do.

更に、半導体装置の製造工程等において微細加工が可能なレジストパターンの窓内に第1、第2導電膜を成膜することで、これらの導電膜から構成される積層体を微細に形成できると供に、積層体を狭ピッチで配列することが可能となる。   Furthermore, when the first and second conductive films are formed in a resist pattern window that can be finely processed in a manufacturing process of a semiconductor device or the like, a laminate composed of these conductive films can be formed finely. In addition, the laminates can be arranged at a narrow pitch.

以下に、本発明の実施の形態に係る電子装置について、その製造工程を追いながら説明する。   Hereinafter, an electronic device according to an embodiment of the present invention will be described following the manufacturing process.

図1〜図5は、本実施形態に係る電子装置の製造途中の断面図である。   1 to 5 are cross-sectional views of the electronic device according to the present embodiment during manufacture.

最初に、図1(a)に示す断面構造を得るまでの工程について説明する。   First, steps required until a sectional structure shown in FIG.

まず、金属等よりなるベース基板10の上に、加熱によって室温時(20℃)よりも接着性が低下する材料よりなるフィルム、例えば熱発泡テープを離形層11として貼付する。本実施形態では、この熱発泡テープとして日東電工製のリバアルファを用いる。なお、UV硬化により接着性が低下する材料で離形層11を構成してもよい。   First, on the base substrate 10 made of metal or the like, a film made of a material whose adhesiveness is lower than that at room temperature (20 ° C.) due to heating, for example, a heat-foamed tape is attached as the release layer 11. In this embodiment, Riba Alpha manufactured by Nitto Denko is used as the thermal foam tape. In addition, you may comprise the release layer 11 with the material from which adhesiveness falls by UV hardening.

また、ベース基板10の材料としては、銅、銅合金、又はステンレスのような金属の他に、シリコン、及びPET(Polyethylene terephthalate)等の有機材料もある。   In addition to the metal such as copper, copper alloy, or stainless steel, the base substrate 10 includes silicon and organic materials such as PET (Polyethylene terephthalate).

次いで、スパッタ法により離形層11の上にシード層12としてチタン層を厚さ約0.1μmに形成する。なお、チタン層に代えて銅層をシード層12として形成してもよい。また、シード層12の成膜方法はスパッタ法に限定されず、蒸着法又は無電解めっきによりシード層12を形成してもよいし、シード層12として圧延箔を貼付してもよい。   Next, a titanium layer having a thickness of about 0.1 μm is formed on the release layer 11 as a seed layer 12 by sputtering. Note that a copper layer may be formed as the seed layer 12 instead of the titanium layer. In addition, the method for forming the seed layer 12 is not limited to the sputtering method, and the seed layer 12 may be formed by vapor deposition or electroless plating, or a rolled foil may be attached as the seed layer 12.

次に、図1(b)に示すように、シード層12上にフォトレジストを塗布し、それを露光現像することにより、平面形状が長方形の窓14aを備えたレジストパターン14を形成する。   Next, as shown in FIG. 1B, a photoresist is coated on the seed layer 12, and is exposed and developed to form a resist pattern 14 having a window 14a having a rectangular planar shape.

続いて、図1(c)に示すように、シード層12に給電を行いがなら、窓14aから露出するシード層12上に電解めっきにより第1金属膜(第1導電膜)16aとしてニッケル膜を10〜15μmの厚さに形成する。   Subsequently, as shown in FIG. 1C, if power is supplied to the seed layer 12, a nickel film is formed as a first metal film (first conductive film) 16a on the seed layer 12 exposed from the window 14a by electrolytic plating. Is formed to a thickness of 10 to 15 μm.

そのめっき条件は特に限定されない。本実施形態では、次のめっき液組成とめっき条件で第1金属膜16aを形成する。   The plating conditions are not particularly limited. In the present embodiment, the first metal film 16a is formed with the following plating solution composition and plating conditions.

(めっき液組成)
・硫酸ニッケル:240〜300g/リットル
・塩化ニッケル:45〜50g/リットル
・ホウ酸:30〜40g/リットル
(めっき条件)
・液温:45〜60℃
・電流密度:2〜8A/dm2
第1金属膜16aの構成材料は引張応力となり易い材料であるのが好ましいが、そのような材料としてはNiの他にFe、Pd、Cu、及びCr、或いはこれらの合金等もある。
(Plating solution composition)
Nickel sulfate: 240-300 g / liter Nickel chloride: 45-50 g / liter Boric acid: 30-40 g / liter (plating conditions)
Liquid temperature: 45-60 ° C
・ Current density: 2-8A / dm 2
The constituent material of the first metal film 16a is preferably a material that easily undergoes tensile stress, but such materials include Fe, Pd, Cu, Cr, and alloys thereof in addition to Ni.

また、第1金属膜16aの応力の値は、膜厚、めっき液組成、及びめっき条件を変えることにより調節することができる。   The stress value of the first metal film 16a can be adjusted by changing the film thickness, the plating solution composition, and the plating conditions.

次いで、図2(a)に示すように、シード層12から給電を行いながら、第1金属膜16aの上に電解めっきにより第2金属膜(第2導電膜)16bとして金膜を厚さ0.01〜2μmに形成する。   Next, as shown in FIG. 2A, a gold film is formed as a second metal film (second conductive film) 16b on the first metal film 16a by electrolytic plating while supplying power from the seed layer 12 to a thickness of 0. .01 to 2 μm.

このめっき条件は特に限定されないが、本実施形態では次の条件を採用する。   Although the plating conditions are not particularly limited, the following conditions are adopted in this embodiment.

(めっき液組成)
・亜硫酸金ナトリウム:10g/リットル
・亜硫酸ナトリウム:20g/リットル
・リン酸水素ナトリウム:20g/リットル
・タリウム:0.01g/リットル
(めっき条件)
・液温:40〜70℃
・電流密度:0.1〜3A/dm2
第2金属膜16bの構成材料は圧縮応力となり易い材料であるのが好ましい。そのような材料としては、Auの他に、Zn、Sn、Bi、Co、Ag、及びTiがあり、これらの材料で第2金属膜16bを構成するようにしてもよい。
(Plating solution composition)
・ Gold sodium sulfite: 10 g / liter ・ Sodium sulfite: 20 g / liter ・ Sodium hydrogen phosphate: 20 g / liter ・ Thallium: 0.01 g / liter (plating conditions)
Liquid temperature: 40-70 ° C
・ Current density: 0.1-3A / dm 2
It is preferable that the constituent material of the second metal film 16b is a material that easily becomes a compressive stress. As such a material, there are Zn, Sn, Bi, Co, Ag, and Ti in addition to Au, and the second metal film 16b may be formed of these materials.

更に、第1金属膜16aと同様に、膜厚、めっき液組成、及びめっき条件を変えることにより、第2金属膜16bの応力の値を調節するようにしてもよい。   Further, similarly to the first metal film 16a, the stress value of the second metal film 16b may be adjusted by changing the film thickness, the plating solution composition, and the plating conditions.

この後に、図2(b)に示すように、レジストパターン14を除去して、第1金属膜16aと第2金属膜16bとをベース基板10の上に積層体16として残す。   Thereafter, as shown in FIG. 2B, the resist pattern 14 is removed, and the first metal film 16 a and the second metal film 16 b are left as the stacked body 16 on the base substrate 10.

次いで、図2(c)に示すように、積層体16が形成されていない部分のシード層12をウエットエッチングにより除去する。シード層12としてチタン層を形成する場合は、そのエッチング液として例えばフッ化水素と硝酸の混合液が使用される。   Next, as shown in FIG. 2C, the portion of the seed layer 12 where the stacked body 16 is not formed is removed by wet etching. When a titanium layer is formed as the seed layer 12, for example, a mixed solution of hydrogen fluoride and nitric acid is used as the etching solution.

続いて、図3(a)に示すように、有機樹脂を主体とする回路基板50を用意し、その回路基板を積層体16に対向させる。   Subsequently, as illustrated in FIG. 3A, a circuit board 50 mainly composed of an organic resin is prepared, and the circuit board is opposed to the stacked body 16.

回路基板50の主面にはソルダレジスト53が形成されており、ソルダレジスト53の開口部の内部には第1電極51が形成されている。また、その第1電極51の表面には融点が139℃のSn-57Bi合金よりなる導電層52が形成されている。なお、導電層52は、Sn-57Bi合金層に限定されず、Au、Cu、Sn、及びSn基合金のいずれかよりなるめっき層や、導電性ペーストであってもよい。   A solder resist 53 is formed on the main surface of the circuit board 50, and a first electrode 51 is formed inside the opening of the solder resist 53. Further, a conductive layer 52 made of an Sn-57Bi alloy having a melting point of 139 ° C. is formed on the surface of the first electrode 51. The conductive layer 52 is not limited to the Sn-57Bi alloy layer, and may be a plated layer made of any of Au, Cu, Sn, and Sn-based alloy, or a conductive paste.

そして、図示のように、積層体16を構成する第2金属膜16bの一方の端部Aと、回路基板50の第1電極51とを位置合わせする。   Then, as shown in the figure, one end A of the second metal film 16b constituting the stacked body 16 and the first electrode 51 of the circuit board 50 are aligned.

次に、図3(b)に示すように、導電層52が溶融する150〜180℃の温度に導電層52を加熱しながら、ベース基板10を回路基板50に向けて押圧し、導電層52により積層体16を第1電極51に接合する。なお、このときベース基板10に加える圧力は特に限定されないが、本実施形態では各第1電極51に0.5〜10gの圧力が加わるようにする。   Next, as shown in FIG. 3B, while heating the conductive layer 52 to a temperature of 150 to 180 ° C. at which the conductive layer 52 melts, the base substrate 10 is pressed toward the circuit board 50, and the conductive layer 52 Thus, the stacked body 16 is joined to the first electrode 51. At this time, the pressure applied to the base substrate 10 is not particularly limited, but in the present embodiment, a pressure of 0.5 to 10 g is applied to each first electrode 51.

続いて、図4(a)に示すように、熱発泡テープよりなる離形層11が発泡する温度(約200℃)に該離形層11を加熱しながら、ベース基板10を回路基板50の上方に引き上げ、ベース基板10から積層体16を剥離する。なお、UV硬化により接着性が低下する材料で離形層11を構成する場合は、離形層11にUV照射を行うことでベース基板10から積層体16を剥離すればよい。   Subsequently, as shown in FIG. 4A, the base substrate 10 is attached to the circuit board 50 while heating the release layer 11 to a temperature (about 200 ° C.) at which the release layer 11 made of the heat-foaming tape foams. Pulled upward, the laminate 16 is peeled off from the base substrate 10. When the release layer 11 is made of a material whose adhesiveness is reduced by UV curing, the laminate 16 may be peeled from the base substrate 10 by irradiating the release layer 11 with UV.

このように剥離すると、各金属膜16a、16bの応力の違いに起因して、積層体16が第2金属膜16bを外側にして弧状に湾曲するようになる。   When peeled in this way, due to the difference in stress between the metal films 16a and 16b, the stacked body 16 is curved in an arc shape with the second metal film 16b on the outside.

なお、第1金属膜16aとシード層12との密着力が弱い場合には、図2(c)のシード層12のエッチング工程を省き、本工程でシード層12から積層体16を剥離するようにしてもよい。また、シード層12とベース基板10の密着力が弱く、同様に本工程で積層体16が剥離できる場合には、離形層11を省いてもよい。   When the adhesion between the first metal film 16a and the seed layer 12 is weak, the etching process of the seed layer 12 in FIG. 2C is omitted, and the stacked body 16 is peeled from the seed layer 12 in this process. It may be. Further, when the adhesion between the seed layer 12 and the base substrate 10 is weak and the laminate 16 can be peeled off in this process as well, the release layer 11 may be omitted.

次いで、図4(b)に示すように、回路形成面に第2電極61が形成されたシリコンを主体とする半導体素子(電子部品)60を用意する。その第2電極61の上には、Sn-3.5Ag合金よりなる接続端子62が予め接合されている。接続端子62の材料は特に限定されず、Au、Cu、Sn、及びSn基合金のいずれかよりなるめっき膜や、導電性ペーストで接続端子62を構成してもよい。   Next, as shown in FIG. 4B, a semiconductor element (electronic component) 60 mainly composed of silicon having the second electrode 61 formed on the circuit formation surface is prepared. On the second electrode 61, a connection terminal 62 made of Sn-3.5Ag alloy is bonded in advance. The material of the connection terminal 62 is not particularly limited, and the connection terminal 62 may be composed of a plating film made of any of Au, Cu, Sn, and Sn-based alloy, or a conductive paste.

次いで、接続端子62の融点である221℃以上の温度に該接続端子62を加熱しながら、フェイスダウンの状態で半導体素子60を回路基板50に向けて押圧する。本実施形態では、例えば、一つ当たりの第2電極61に0.5〜5gの圧力が加わるように半導体素子60を押圧する。   Next, the semiconductor element 60 is pressed toward the circuit board 50 in a face-down state while heating the connection terminal 62 to a temperature of 221 ° C. or higher, which is the melting point of the connection terminal 62. In the present embodiment, for example, the semiconductor element 60 is pressed so that a pressure of 0.5 to 5 g is applied to the second electrode 61 per one.

これにより、積層体16を構成する第2金属膜16bの他方の端部Bが第2電極61に接合され、積層体16によって第1、第2電極51、61同士が電気的且つ機械的に接続されたことになる。   As a result, the other end B of the second metal film 16b constituting the stacked body 16 is joined to the second electrode 61, and the first and second electrodes 51, 61 are electrically and mechanically connected to each other by the stacked body 16. It is connected.

なお、上記のように半導体素子60を押圧するのではなく、半導体素子60の自重によって積層体16を第2電極61に接合するようにしてもよい。その場合は、接続端子62に予めフラックスを転写しておき、そのフラックスにより接続端子62を積層体16に仮付けし、リフロー装置内で接続端子62をリフローすればよい。   Instead of pressing the semiconductor element 60 as described above, the stacked body 16 may be bonded to the second electrode 61 by its own weight. In that case, the flux may be transferred to the connection terminal 62 in advance, the connection terminal 62 may be temporarily attached to the laminate 16 with the flux, and the connection terminal 62 may be reflowed in the reflow apparatus.

この後は、積層体16による接続強度を補強するために、図5に示すように、回路基板50と半導体素子60との間に封止樹脂70を流し込む。封止樹脂70としては、例えば、エポキシ樹脂、或いはシアネートエステル樹脂等を使用できる。なお、封止樹脂70を予め基板側またはチップ側に供給しておき、接続端子の接合と樹脂封止を同時に行うこともできる。   Thereafter, in order to reinforce the connection strength of the laminate 16, a sealing resin 70 is poured between the circuit board 50 and the semiconductor element 60 as shown in FIG. As the sealing resin 70, for example, an epoxy resin or a cyanate ester resin can be used. Note that the sealing resin 70 may be supplied in advance to the substrate side or the chip side, and the connection of the connection terminals and the resin sealing may be performed simultaneously.

以上により、本実施形態に係る電子装置の基本構造が完成した。   Thus, the basic structure of the electronic device according to this embodiment is completed.

上記した本実施形態によれば、図5に示したように、半導体素子60と回路基板50との熱膨張率差に起因した応力が、湾曲した積層体16によって緩和されるので、半導体素子60等にクラックが入る危険性が低減し、半導体素子60と回路基板50との接続信頼性が向上する。   According to the present embodiment described above, as shown in FIG. 5, the stress caused by the difference in thermal expansion coefficient between the semiconductor element 60 and the circuit board 50 is relieved by the curved laminate 16, so that the semiconductor element 60 Thus, the risk of cracks is reduced, and the connection reliability between the semiconductor element 60 and the circuit board 50 is improved.

しかも、図4(a)に示したように、第1、第2金属膜16a、16bの内部応力の違いによって積層体16が自然に湾曲するので、積層体16を湾曲させるために特別な装置を必要とせず、接続構造を低コストで簡単に得ることができる。   In addition, as shown in FIG. 4A, the laminate 16 naturally curves due to the difference in internal stress between the first and second metal films 16a and 16b. The connection structure can be easily obtained at low cost.

更に、図1(b)〜図2(b)に示したように、半導体装置の製造工程等において微細加工が可能なレジストパターン14の窓14a内に各金属膜16a、16bを成膜するので、これらの金属膜から構成される積層体16を微細に形成できると供に、積層体16を狭ピッチで配列することが可能となる。   Further, as shown in FIGS. 1B to 2B, the metal films 16a and 16b are formed in the windows 14a of the resist pattern 14 that can be finely processed in the manufacturing process of the semiconductor device. In addition to the fact that the laminate 16 composed of these metal films can be finely formed, the laminates 16 can be arranged at a narrow pitch.

ところで、上記実施形態では、第1金属膜16aを引張応力にし、第2金属膜16bを圧縮応力にしたが、各膜16a、16bの応力の組み合わせはこれに限定されない。   By the way, in the said embodiment, although the 1st metal film 16a was made into the tensile stress and the 2nd metal film 16b was made into the compressive stress, the combination of the stress of each film | membrane 16a, 16b is not limited to this.

例えば、第1金属膜16aの応力を上記と同じ引張応力にし、第2金属膜16bの応力を、第1金属膜16aの引張応力よりも弱い引張応力にしてもよい。   For example, the stress of the first metal film 16a may be the same tensile stress as described above, and the stress of the second metal film 16b may be a tensile stress weaker than the tensile stress of the first metal film 16a.

或いは、第1金属膜16aの応力は圧縮応力にし、第2金属膜16bの応力を、第1金属膜16aの圧縮応力よりも強い圧縮応力としてもよい。   Alternatively, the stress of the first metal film 16a may be a compressive stress, and the stress of the second metal film 16b may be a compressive stress stronger than the compressive stress of the first metal film 16a.

これらによっても、図4(a)のように第2金属膜16bを外側にして弧状に湾曲した積層体16を得ることができる。   Also by these, as shown in FIG. 4A, the laminated body 16 curved in an arc shape with the second metal film 16b on the outside can be obtained.

膜の応力の向きはその材料によって略決まる。金属膜16a、16bとして引張応力の膜を形成する場合には、Ni、Cr、Cu、Fe及びPdのいずれか或いはこれらの合金でその膜を形成すればよい。   The direction of the stress of the film is substantially determined by the material. When forming a film having a tensile stress as the metal films 16a and 16b, the film may be formed of any one of Ni, Cr, Cu, Fe, and Pd, or an alloy thereof.

一方、金属膜16a、16bとして圧縮応力の膜を形成する場合には、Au、Zn、Sn及びBiのいずれか或いはこれらの合金でその膜を形成すればよい。   On the other hand, when a compressive stress film is formed as the metal films 16a and 16b, the film may be formed of any one of Au, Zn, Sn, and Bi or an alloy thereof.

また、応力の値については、既述のようにめっき液の組成、めっき条件、及び膜厚によって調節することができ、これにより所望の曲率で湾曲した積層体16を得ることができる。   Further, the stress value can be adjusted according to the composition of the plating solution, the plating conditions, and the film thickness as described above, whereby the laminate 16 curved with a desired curvature can be obtained.

なお、上記では第1、第2金属膜16a、16bの二層で積層体16を構成したが、積層数を3層以上としてもよい。   In the above description, the stacked body 16 is configured by two layers of the first and second metal films 16a and 16b. However, the number of stacked layers may be three or more.

図6は、3層構造の積層体16の一例を示す拡大断面図である。   FIG. 6 is an enlarged cross-sectional view showing an example of a laminate 16 having a three-layer structure.

この例では、第2金属膜16bの上に更に第3金属膜(第3導電膜)16cを形成している。その第3金属膜16cは、例えば図2(a)の状態で、窓14a内の第2金属膜16bの上にめっきにより形成され得る。   In this example, a third metal film (third conductive film) 16c is further formed on the second metal film 16b. The third metal film 16c can be formed by plating on the second metal film 16b in the window 14a, for example, in the state of FIG.

第3金属膜16cの応力の向きと値は特に限定されない。   The direction and value of the stress of the third metal film 16c are not particularly limited.

但し、第1〜第3金属膜16a〜16cのそれぞれの応力の値が、第1金属膜16aから第3金属膜16cに向かって単調に減少若しくは増大するように、第3金属膜16cの材料やめっき条件等を設定するのが好ましい。このように応力を単調に変化させることで、第1、第2金属膜16a、16bのみで積層体16を構成する場合と比較して、各膜16a〜16cの応力の違いによってそれらの界面に加わる応力が緩和され、積層体16の内部にクラックが入る危険性を低減できる。   However, the material of the third metal film 16c is such that the stress values of the first to third metal films 16a to 16c monotonously decrease or increase from the first metal film 16a toward the third metal film 16c. It is preferable to set the plating conditions and the like. In this way, by changing the stress monotonously, compared to the case where the stacked body 16 is configured by only the first and second metal films 16a and 16b, the difference between the stresses of the films 16a to 16c causes the interface between them. The applied stress is relaxed, and the risk of cracks inside the laminate 16 can be reduced.

また、上記では、異種の材料よりなる第1、第2金属膜16a、16bの二層で積層体16を構成するようにしたが、これら第1、第2金属膜16a、16bを供に同じ材料で構成し、且つそれらを異なるめっき条件で形成することにより、各金属膜16a、16bの応力に違いをもたせ、図4(a)のように積層体16を湾曲させてもよい。   Further, in the above description, the laminate 16 is configured by two layers of the first and second metal films 16a and 16b made of different materials. However, the first and second metal films 16a and 16b are the same. By forming them with materials and forming them under different plating conditions, the stresses of the metal films 16a and 16b may be made different, and the laminate 16 may be curved as shown in FIG.

また、第1、第2金属膜16a、16bの一方に代えて、ポリイミドやエポキシ樹脂からなる樹脂膜を形成してもよい。そのような樹脂膜としては、例えば、東レ・デュポン株式会社製のカプトンフィルム等、現在市販されている膜を使用することが可能である。   Further, instead of one of the first and second metal films 16a and 16b, a resin film made of polyimide or epoxy resin may be formed. As such a resin film, for example, a commercially available film such as a Kapton film manufactured by Toray DuPont Co., Ltd. can be used.

このような樹脂膜を使用する場合、図1(a)の工程において、離形層11の上にその樹脂層を形成した後、当該樹脂膜の上にレジストパターンを形成する。そして、レジストパターンの窓から露出する樹脂膜の上に無電解めっき法により例えば銅膜又はニッケル膜等の金属膜を形成する。その後、レジストパターンを、その上に形成された金属膜と供に除去することで、樹脂膜と金属膜よりなる積層体が離形層11の上に形成される。その積層体は、金属膜と樹脂膜との応力の違いにより、金属膜を外側にした状態で図4(a)で説明したように湾曲する。   In the case of using such a resin film, in the step of FIG. 1A, after forming the resin layer on the release layer 11, a resist pattern is formed on the resin film. Then, a metal film such as a copper film or a nickel film is formed on the resin film exposed from the resist pattern window by electroless plating. Thereafter, the resist pattern is removed together with the metal film formed thereon, so that a laminate composed of the resin film and the metal film is formed on the release layer 11. The laminate is curved as described with reference to FIG. 4A with the metal film facing outward due to the difference in stress between the metal film and the resin film.

以下に、本発明の特徴を付記する。   The features of the present invention are added below.

(付記1) 第1電極が形成された回路基板と、
第2電極が形成された電子部品と、
互いに応力の異なる第1導電膜と第2導電膜とを積層してなり、前記第1電極と前記第2電極とを電気的に接続する積層体とを有し、
前記積層体を湾曲させて、該第2導電膜の一方の端部を前記第1電極に接合し、該第2導電膜の他方の端部を前記第2電極に接合したことを特徴とする電子装置。
(Appendix 1) a circuit board on which a first electrode is formed;
An electronic component on which a second electrode is formed;
A laminated body that is formed by laminating a first conductive film and a second conductive film having different stresses, and electrically connects the first electrode and the second electrode;
The laminated body is curved, one end of the second conductive film is bonded to the first electrode, and the other end of the second conductive film is bonded to the second electrode. Electronic equipment.

(付記2) 前記第1導電膜は金属からなる第1金属膜、前記第2導電膜は金属からなる第2金属膜であることを特徴とする付記1に記載の電子装置。   (Supplementary note 2) The electronic device according to supplementary note 1, wherein the first conductive film is a first metal film made of metal, and the second conductive film is a second metal film made of metal.

(付記3) 前記第1導電膜と前記第2導電膜の少なくとも一方は、Ni、Fe、Pd、Cu、Cr、Au、Sn、Bi、Zn、Co、Ag、及びTiのいずれか、若しくはこれらの合金により構成されることを特徴とする付記2に記載の電子装置。   (Supplementary Note 3) At least one of the first conductive film and the second conductive film is one of Ni, Fe, Pd, Cu, Cr, Au, Sn, Bi, Zn, Co, Ag, and Ti, or these The electronic device according to attachment 2, wherein the electronic device is made of an alloy of

(付記4) 前記積層体は、前記第2導電膜を外側にして弧状に湾曲していることを特徴とする付記1に記載の電子装置。   (Supplementary note 4) The electronic device according to supplementary note 1, wherein the stacked body is curved in an arc shape with the second conductive film facing outside.

(付記5) 前記第1導電膜の応力は引張応力であり、前記第2導電膜の応力は圧縮応力であることを特徴とする付記1に記載の電子装置。   (Supplementary note 5) The electronic device according to supplementary note 1, wherein the stress of the first conductive film is a tensile stress, and the stress of the second conductive film is a compressive stress.

(付記6) 前記第1導電膜の応力は引張応力であり、前記第2導電膜の応力は、前記第1導電膜の前記引張応力よりも弱い引張応力であることを特徴とする付記1に記載の電子装置。   (Additional remark 6) The stress of the said 1st electrically conductive film is a tensile stress, The stress of the said 2nd electrically conductive film is a tensile stress weaker than the said tensile stress of the said 1st electrically conductive film. The electronic device described.

(付記7) 前記第1導電膜の応力は圧縮応力であり、前記第2導電膜の応力は、前記第1導電膜の前記圧縮応力よりも強い圧縮応力であることを特徴とする付記1に記載の電子装置。   (Supplementary note 7) The supplementary note 1 is characterized in that the stress of the first conductive film is a compressive stress, and the stress of the second conductive film is a compressive stress stronger than the compressive stress of the first conductive film. The electronic device described.

(付記8) 前記第2導電膜の上に更に第3導電膜が形成され、前記第1〜第3導電膜におけるそれぞれの応力の値が、前記第1導電膜から前記第3導電膜に向かって単調に減少若しくは増大することを特徴とする付記1に記載の電子装置。   (Supplementary Note 8) A third conductive film is further formed on the second conductive film, and each stress value in the first to third conductive films is directed from the first conductive film to the third conductive film. The electronic device according to appendix 1, wherein the electronic device monotonously decreases or increases.

(付記9) ベース基板の上に、互いに応力の異なる第1導電膜と第2導電膜をこの順に積層してなる積層体を形成する工程と、
基板の第1電極に、前記第2導電膜の一方の端部を接合する工程と、
前記接合の後、前記ベース基板から前記積層体を剥離し、前記応力の違いにより前記積層体を湾曲させる工程と、
電子部品の第2電極に、前記第2導電膜の他方の端部を接合する工程と、
を有することを特徴とする電子装置の製造方法。
(Additional remark 9) The process of forming on the base substrate the laminated body formed by laminating | stacking the 1st conductive film and the 2nd conductive film from which a stress mutually differs in this order,
Bonding one end of the second conductive film to the first electrode of the substrate;
After the bonding, peeling the laminate from the base substrate, bending the laminate due to the difference in stress,
Bonding the other end of the second conductive film to the second electrode of the electronic component;
A method for manufacturing an electronic device, comprising:

(付記10) 前記ベース基板の上に離形層を形成する工程を更に有し、
前記積層体を形成する工程において、前記離形層の上に前記積層体を形成することを特徴とする付記9に記載の電子装置の製造方法。
(Additional remark 10) It further has the process of forming a release layer on the said base substrate,
The method for manufacturing an electronic device according to appendix 9, wherein in the step of forming the laminate, the laminate is formed on the release layer.

(付記11) 前記離形層の材料として、加熱により室温時よりも接着性が低下する材料を用い、
前記ベース基板から前記積層体を剥離する工程において、前記離形層を加熱することを特徴とする付記10に記載の電子装置の製造方法。
(Supplementary Note 11) As a material for the release layer, a material whose adhesiveness is lower than that at room temperature by heating is used.
The method of manufacturing an electronic device according to appendix 10, wherein the release layer is heated in the step of peeling the laminate from the base substrate.

(付記12) 前記積層体を形成する工程は、
前記ベース基板の上に、窓を備えたレジストパターンを形成する工程と、
前記レジストパターンの窓内の前記ベース基板上に、前記第1導電膜と前記第2導電膜とをこの順に形成する工程と、
前記レジストパターンを除去して、前記第1導電膜と前記第2導電膜とを前記ベース基板の上に前記積層体として残す工程とを有することを特徴とする付記9に記載の電子装置の製造方法。
(Additional remark 12) The process of forming the said laminated body,
Forming a resist pattern with a window on the base substrate;
Forming the first conductive film and the second conductive film in this order on the base substrate in the window of the resist pattern;
The method of manufacturing an electronic device according to appendix 9, further comprising a step of removing the resist pattern and leaving the first conductive film and the second conductive film on the base substrate as the stacked body. Method.

(付記13) 前記第1導電膜と前記第2導電膜とを形成する工程において、該第1導電膜と該第2導電膜とを電解めっきにより形成すると供に、めっき条件、めっき液組成、又は膜厚により前記第1導電膜と前記第2導電膜の応力を調節することを特徴とする付記12に記載の電子装置の製造方法。   (Supplementary Note 13) In the step of forming the first conductive film and the second conductive film, the first conductive film and the second conductive film are formed by electrolytic plating, and the plating conditions, the plating solution composition, The method of manufacturing an electronic device according to appendix 12, wherein the stress of the first conductive film and the second conductive film is adjusted by a film thickness.

図1(a)〜(c)は、本発明の実施の形態に係る電子装置の製造途中の断面図(その1)である。1A to 1C are cross-sectional views (part 1) in the course of manufacturing the electronic device according to the embodiment of the present invention. 図2(a)〜(c)は、本発明の実施の形態に係る電子装置の製造途中の断面図(その2)である。2A to 2C are cross-sectional views (part 2) in the middle of manufacturing the electronic device according to the embodiment of the present invention. 図3(a)、(b)は、本発明の実施の形態に係る電子装置の製造途中の断面図(その3)である。3A and 3B are cross-sectional views (part 3) in the course of manufacturing the electronic device according to the embodiment of the present invention. 図4(a)、(b)は、本発明の実施の形態に係る電子装置の製造途中の断面図(その4)である。4A and 4B are cross-sectional views (part 4) in the middle of manufacturing the electronic device according to the embodiment of the present invention. 図5は、本発明の実施の形態に係る電子装置の製造途中の断面図(その5)である。FIG. 5 is a cross-sectional view (part 5) of the electronic device according to the embodiment of the present invention during manufacture. 図6は、本発明の実施の形態において、三層構造の積層体の一例を示す拡大断面図である。FIG. 6 is an enlarged cross-sectional view showing an example of a three-layer laminate in the embodiment of the present invention.

符号の説明Explanation of symbols

10…ベース基板、11…離形層、12…シード層、14…レジストパターン、14a…窓、16a〜16c…第1〜第3金属膜、16…積層体、50…回路基板、51…第1電極、52…導電層、53…ソルダレジスト、60…半導体素子、61…第2電極、62…接続端子、70…封止樹脂。 DESCRIPTION OF SYMBOLS 10 ... Base substrate, 11 ... Release layer, 12 ... Seed layer, 14 ... Resist pattern, 14a ... Window, 16a-16c ... 1st-3rd metal film, 16 ... Laminated body, 50 ... Circuit board, 51 ... 1st DESCRIPTION OF SYMBOLS 1 electrode, 52 ... Conductive layer, 53 ... Solder resist, 60 ... Semiconductor element, 61 ... 2nd electrode, 62 ... Connection terminal, 70 ... Sealing resin.

Claims (3)

第1面に第1電極が形成された回路基板と、
第1面に第2電極が形成された電子部品と、
互いに応力の異なる第1導電膜と第2導電膜とを積層してなり、前記第1電極と前記第2電極とを電気的に接続する積層体とを有し、
前記第1導電膜と前記第2導電膜とは共に同じ材料で構成され、且つ前記第1導電膜と前記第2導電膜とは互いに異なるめっき条件で形成されて、前記第1導電膜の応力は引張応力であり、前記第2導電膜の応力は圧縮応力であり、
前記回路基板の前記第1面と前記電子部品の前記第1面とが互いに向き合うように前記回路基板と前記電子部品とを配置させ、
前記第2導電膜を外側にして前記積層体を弧状に湾曲させて、該第2導電膜の一方の端部を前記第1電極に接合し、該第2導電膜の他方の端部を前記第2電極に接合したことを特徴とする電子装置。
A circuit board having a first electrode formed on a first surface;
An electronic component having a second electrode formed on the first surface;
A laminated body that is formed by laminating a first conductive film and a second conductive film having different stresses, and electrically connects the first electrode and the second electrode;
The first conductive film and the second conductive film are both made of the same material, and the first conductive film and the second conductive film are formed under different plating conditions, and the stress of the first conductive film Is tensile stress, stress of the second conductive film is compressive stress,
Arranging the circuit board and the electronic component such that the first surface of the circuit board and the first surface of the electronic component face each other;
The laminate is curved in an arc shape with the second conductive film outside, the one end of the second conductive film is joined to the first electrode, and the other end of the second conductive film is connected to the first electrode. An electronic device characterized by being joined to a second electrode.
ベース基板の上に、互いに応力の異なる第1導電膜と第2導電膜をこの順に積層してなる積層体を形成する工程と、
基板の第1電極に、前記第2導電膜の一方の端部を接合する工程と、
前記接合の後、前記ベース基板から前記積層体を剥離し、前記応力の違いにより前記積層体を湾曲させる工程と、
電子部品の第2電極に、前記第2導電膜の他方の端部を接合する工程と、
を有することを特徴とする電子装置の製造方法。
Forming a laminated body formed by laminating a first conductive film and a second conductive film having different stresses in this order on a base substrate;
Bonding one end of the second conductive film to the first electrode of the substrate;
After the bonding, peeling the laminate from the base substrate, bending the laminate due to the difference in stress,
Bonding the other end of the second conductive film to the second electrode of the electronic component;
A method for manufacturing an electronic device, comprising:
前記積層体を形成する工程は、
前記ベース基板の上に、窓を備えたレジストパターンを形成する工程と、
前記レジストパターンの窓内の前記ベース基板上に、前記第1導電膜と前記第2導電膜とをこの順に形成する工程と、
前記レジストパターンを除去して、前記第1導電膜と前記第2導電膜とを前記ベース基板の上に前記積層体として残す工程とを有することを特徴とする請求項2に記載の電子装置の製造方法。
The step of forming the laminate includes
Forming a resist pattern with a window on the base substrate;
Forming the first conductive film and the second conductive film in this order on the base substrate in the window of the resist pattern;
3. The electronic device according to claim 2 , further comprising a step of removing the resist pattern and leaving the first conductive film and the second conductive film as the stacked body on the base substrate. Production method.
JP2007295939A 2007-11-14 2007-11-14 Electronic device and method of manufacturing the same Expired - Fee Related JP5034885B2 (en)

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