JP5716948B2 - Manufacturing method of package substrate for mounting semiconductor device - Google Patents

Manufacturing method of package substrate for mounting semiconductor device Download PDF

Info

Publication number
JP5716948B2
JP5716948B2 JP2010218900A JP2010218900A JP5716948B2 JP 5716948 B2 JP5716948 B2 JP 5716948B2 JP 2010218900 A JP2010218900 A JP 2010218900A JP 2010218900 A JP2010218900 A JP 2010218900A JP 5716948 B2 JP5716948 B2 JP 5716948B2
Authority
JP
Japan
Prior art keywords
metal foil
plating
carrier
carrier metal
surface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2010218900A
Other languages
Japanese (ja)
Other versions
JP2012074576A (en
Inventor
田村 匡史
匡史 田村
学 杉林
学 杉林
邦司 鈴木
邦司 鈴木
清男 服部
清男 服部
Original Assignee
日立化成株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日立化成株式会社 filed Critical 日立化成株式会社
Priority to JP2010218900A priority Critical patent/JP5716948B2/en
Publication of JP2012074576A publication Critical patent/JP2012074576A/en
Application granted granted Critical
Publication of JP5716948B2 publication Critical patent/JP5716948B2/en
Application status is Active legal-status Critical
Anticipated expiration legal-status Critical

Links

Images

Description

  The present invention relates to a method of manufacturing a package substrate for mounting a semiconductor element capable of increasing the density.

  As electronic components become smaller and higher in density, a systemized package board for mounting semiconductor elements (hereinafter sometimes referred to as a “package board”) is required, represented by SiP (System in Package). In recent years, a package in which a plurality of semiconductor elements are stacked on a single package substrate has become the mainstream in PoP (Package on Package). It is necessary to arrange them at a high density, and miniaturization of the outer layer circuit is required.

  Further, flip chip connection or wire bonding connection is used for electrical connection between the semiconductor element and the connection terminal of the package substrate. However, as the connection terminal becomes finer, it tends to be difficult to ensure connection reliability. Specifically, in flip chip connection using solder, if the surface and side surfaces of the connection terminals are exposed, solder may wrap around the side surfaces of the connection terminals, which may cause a short circuit between the connection terminals. It is required that the terminal is embedded in the insulating layer, and the connection terminal and the insulating layer are flat. On the other hand, in the wire bonding connection, the nickel plating as the base plating is required to have a certain thickness. However, if the thickness of the nickel plating as the base plating is satisfied, the connecting terminal becomes thick and the flatness with respect to the surface of the insulating layer is lost. For this reason, it is difficult to satisfy the connection reliability of both the flip chip connection and the wire bond connection, and the flatness between the connection terminal and the insulating layer is reduced along with the miniaturization of the connection terminal. In addition, it is required to ensure the thickness of the base plating.

  As a method of forming a fine outer layer circuit, an interlayer connection hole is provided in an insulating substrate provided with a thin copper foil having a thickness of about 2 μm, and a thin film having a thickness of about 0.1 μm is formed on the thin copper foil and in the interlayer connection hole. After electroless copper plating is performed, a plating resist is formed thereon, and the portion that becomes the outer layer circuit is thickened by pattern electroplating. Then, the plating resist is removed and the entire surface is etched to perform pattern electroplating. There is a method of forming an outer layer circuit by removing only a non-existing portion (that is, only a thin portion of a conductor) (Patent Document 1).

  In addition, as a method of obtaining flatness between the outer layer circuit and the insulating layer, an insulating resin is provided on the surface of a physically peelable carrier copper foil with a carrier copper foil to form a support substrate. After forming a conductor pattern to be an outer layer circuit by pattern copper plating on the ultra-thin copper foil of this support substrate, forming an insulating resin and interlayer connection thereon, and then physically peeling the support substrate including the carrier copper foil Furthermore, there is a method of forming a fine outer layer circuit by removing the ultrathin copper foil by etching (Patent Document 2).

  Furthermore, as a method of obtaining the flatness between the outer layer circuit and the insulating layer, a wiring film having a predetermined pattern is formed on the surface of the intermediate film of the carrier film, and conductive pillars are formed on the surface of the wiring film by pattern plating, thereby providing interlayer insulation. Prepare two wiring members on which the film is formed, stack and integrate them so that the end faces of the conductive pillars are in contact, remove the carrier film by etching using the intermediate film as an etching stop layer, and further remove the intermediate film by etching There is a method of forming wiring (Patent Document 3).

JP 2004-140176 A JP 2005-101137 A JP 2006-135277 A

  However, in the method of Patent Document 1, since the thin copper foil provided on the insulating substrate and the thin electroless copper plating are used as the power feeding layer of the pattern electrolytic copper plating, the entire surface is etched after the pattern electroplating. For this, etching for the thickness of the power feeding layer (a layer obtained by combining a thin copper foil and a thin electroless copper plating) is required. When the power feeding layer is removed by this etching, an undercut tends to occur. For this reason, the substantial adhesion width between the formed outer layer circuit and the insulating base material is reduced, and it is difficult to form a fine outer layer circuit having a line / space level of 15 μm / 15 μm or less, for example. Further, the outer layer circuit protrudes from the insulating base material by the thickness, and there is a problem that the flatness between the outer layer circuit and the insulating base material cannot be satisfied.

  Further, in the method of Patent Document 2, when an insulating resin is laminated on the surface of an ultrathin copper foil (thickness 1 to 5 μm) with a carrier copper foil, the ultrathin exposed on the surface side of the support substrate is formed. Resin powder of insulating resin may adhere to the surface of the copper foil, and the resin powder attached to the ultrathin copper foil may reduce the yield when processing the ultrathin copper foil to form a fine outer layer circuit. It can be a factor. In addition, although the outer layer circuit is embedded in the insulating layer, if the base nickel plating and gold plating for wire bonding are performed on the outer layer circuit, the outer layer circuit protrudes from the insulating layer by these thicknesses. There was a problem that the flatness with the substrate was not sufficient.

  In the method of Patent Document 3, the carrier film is removed by etching using the intermediate film as an etching stop layer, and further the intermediate film is removed by etching. However, the yield is lowered because defects such as pinholes are likely to occur in the etching stop layer. In addition, since etching is performed in two stages, the unevenness on the surface of the formed outer layer circuit may increase, and the connection reliability with the semiconductor element may decrease. Further, as with the cited document 2, the outer layer circuit protrudes from the insulating layer by the thickness of the underlying nickel plating and gold plating for wire bonding, so that the flatness between the outer layer circuit and the insulating substrate is still not sufficient. It was.

  The present invention has been made in view of the above-described problems, and it is possible to form a fine and tight outer layer circuit by hardly causing undercut, and suppress adhesion of resin powder when laminated with an insulating layer. The manufacturing method of a package substrate for mounting a semiconductor device, which can improve the yield, and can ensure the connection reliability with the semiconductor device by having the outer layer circuit flat with respect to the insulating layer and having a noble metal plating on the surface. I will provide a.

The present invention relates to the following.
(1) A first carrier metal foil, a second carrier metal foil, and a base metal foil are laminated in this order, and between the first carrier metal foil and the second carrier metal foil and between the second carrier metal foil and the base metal. Preparing a multilayer metal foil provided with a release layer between each of the foils, laminating the base metal foil side of the multilayer metal foil and a base material to form a core substrate; A step of physically peeling the first carrier metal foil at an interface between the first carrier metal foil and the second carrier metal foil, a step of performing pattern plating on the second carrier metal foil remaining on the core substrate, In the step of forming a laminate by laminating an insulating layer on a second carrier metal foil including pattern plating, and the interface between the second carrier metal foil and the base metal foil of the multilayer metal foil, Core substrate with carrier metal foil And physically separating and separating, and etching from the second carrier metal foil side of the separated laminate to remove at least a part of the second carrier metal foil, and the surface of the pattern plating is A step of forming a dent on the surface of the insulating layer, and a base plating and a noble metal plating are performed on the surface of the pattern plating on which the dent is formed, and the surface of the noble metal plating is a surface of the insulating layer A method of manufacturing a package substrate for mounting a semiconductor element, the method comprising:
(2) A method for manufacturing a package substrate for mounting a semiconductor element according to the above (1), wherein the base plating is nickel plating or nickel plating and palladium plating, and the noble metal plating is gold plating or silver plating.
(3) In the above (1) or (2), the multilayer metal foil has a peel strength at the interface between the second carrier metal foil and the base metal foil, which is the interface between the first carrier metal foil and the second carrier metal foil. A method for manufacturing a package substrate for mounting a semiconductor element, which is a multilayer metal foil formed larger than the peel strength.
(4) In any one of the above (1) to (3), the multilayer metal foil is formed on the surface of the second carrier copper foil provided with irregularities having an average roughness (Ra) of 0.3 μm to 1.2 μm in advance. A manufacturing method of a package substrate for mounting a semiconductor element, which is a multilayer metal foil in which one carrier copper foil is laminated.

  According to the present invention, it is possible to form a fine and adhesive outer layer circuit because it is difficult for undercut to occur, and it is possible to improve yield by suppressing adhesion of resin powder when laminated with an insulating layer, Since the outer layer circuit is flat with respect to the insulating layer and has noble metal plating on the surface, it is possible to provide a method for manufacturing a package substrate for mounting a semiconductor element that can ensure connection reliability with the semiconductor element.

It is sectional drawing of the multilayer metal foil used for this invention. It is a flowchart showing a part of manufacturing method of the package substrate of this invention. It is a flowchart showing a part of manufacturing method of the package substrate of this invention. It is a flowchart showing a part of manufacturing method of the package substrate of this invention. It is a flowchart showing a part of manufacturing method of the package substrate of this invention. It is a flowchart showing a part of manufacturing method of the package substrate of this invention. It is a flowchart showing a part of manufacturing method of the package substrate of this invention.

  An example of the manufacturing method of the package substrate of the present invention will be described below with reference to FIGS.

  First, as shown in FIG. 1, a multilayer metal foil 9 in which a first carrier metal foil 10, a second carrier metal foil 11, and a base metal foil 12 are laminated in this order is prepared.

  The first carrier metal foil 10 is for protecting the surface of the second carrier metal foil 11 (interface with the first carrier metal foil 10), and is physically peeled off at the interface with the second carrier metal foil 11. It is possible. As long as the surface of the second carrier metal foil 11 can be protected, the material and thickness are not particularly limited. However, in terms of versatility and handleability, the material is preferably copper foil or aluminum foil, and the thickness is preferably 1 to 35 μm. In addition, it is preferable to provide a release layer (not shown) for stabilizing the peel strength at the interface at the interface between the first carrier metal foil 10 and the second carrier metal foil 11. It is preferable that the peel strength is stabilized even when heating and pressurization are performed a plurality of times when laminated with the insulating resin. Examples of such a release layer include those in which a metal oxide layer and an organic agent layer disclosed in JP-A-2003-181970 are formed, and Cu-Ni-Mo alloys disclosed in JP-A-2003-094553. And those containing a metal oxide of Ni and W or a metal oxide of Ni and Mo shown in re-published patent WO2006 / 013735. When the first carrier metal foil 10 is physically peeled at the interface with the second carrier metal foil 11, the peel layer is peeled off in a state of being attached to the first carrier metal foil 10 side. What does not remain on the surface of the carrier metal foil 11 is desirable.

  The second carrier metal foil 11 serves as a seed layer for supplying a current to perform the pattern plating 18 on the surface after the first carrier metal foil 10 is peeled off, and the interface with the first carrier metal foil 10 and It can be physically peeled off at the interface with the base metal foil 12. It only needs to function as a seed layer together with the base metal foil 12, and the material and thickness are not particularly limited. However, in terms of versatility and handleability, the material is preferably copper foil or aluminum foil, and the thickness is 1 to 18 μm. Can be used. However, as will be described later, when the outer layer circuit 2 is formed (FIGS. 7 (12) and (13)), it is removed by etching, so that variation in the etching amount is reduced as much as possible to form a highly accurate fine circuit. For this purpose, an ultrathin metal foil of 1 to 5 μm is preferable. Moreover, it is preferable to provide a peeling layer (not shown) as described above at the interface with the first carrier metal foil 10 and the interface with the base metal foil 12 in order to stabilize the peeling strength at the interface. The release layer is preferably conductive so that the second carrier metal foil 11 and the base metal foil 12 are integrated to act as a seed layer.

  The base metal foil 12 is positioned on the side laminated with the base material 16 when the multilayer metal foil 9 is laminated with the base material 16 to produce the core substrate 17. It can be physically peeled off at the interface. When laminated with the base material 16, the material and the thickness are not particularly limited as long as they have adhesiveness with the base material 16, but the material is copper foil or aluminum foil in terms of versatility and handleability. The thickness is preferably 9 to 70 μm. Moreover, in order to stabilize the peeling strength at the interface, it is preferable to provide a peeling layer (not shown) as described above at the interface with the second carrier metal foil 11.

  The multilayer metal foil 9 is a multilayer metal foil 9 having three or more layers of metal foils (for example, as described above, the first carrier metal foil 10, the second carrier metal foil 11, and the base metal foil 12), At least two interfaces (for example, as described above, the interface between the first carrier metal foil 10 and the second carrier metal foil 11 and the interface between the second carrier metal foil 11 and the base metal foil 12) are physically separated. Use what is possible. In the process of laminating the base material 16 on the base metal foil 12 side of the multilayer metal foil 9 to form the core substrate 17, foreign matter such as resin powder may adhere to the surface of the first carrier metal foil 10. However, even if such foreign matter adheres, the second carrier metal that is not affected by foreign matter such as resin powder is obtained by physically peeling the first carrier metal foil 10 at the interface with the second carrier metal foil 11. Since the surface of the foil 11 is formed, a high-quality metal foil surface can be secured. Therefore, even when the pattern plating 18 is performed using the second carrier metal foil 11 as a seed layer, the occurrence of defects can be suppressed, so that the yield can be improved.

  Next, as shown in FIG. 2 (1), the base metal foil 12 side of the multilayer metal foil 9 and the base material 16 are laminated to form a core substrate 17. The base material 16 is laminated and integrated with the multilayer metal foil 9 to form the core substrate 17. The base material 16 is generally used as the insulating layer 3 of the semiconductor element mounting package substrate 1. Can be used. Examples of the substrate 16 include glass epoxy and glass polyimide. The core substrate 17 serves as a support substrate when the package substrate 1 is manufactured using the multilayer metal foil 9. By ensuring rigidity, workability is improved and damage during handling is prevented. The main role is to improve the yield. For this reason, it is desirable that the substrate 16 has a reinforcing material such as glass fiber. For example, a prepreg such as glass epoxy or glass polyimide is overlapped with the multilayer metal foil 9 and heated / heated using a hot press or the like. It can be formed by pressing and laminating and integrating. The multilayer metal foil 9 is laminated on both sides of the base material 16 (upper and lower sides in FIG. 2 (1)), and the subsequent steps are performed to advance the process of manufacturing the two package substrates 1 in one step. Therefore, man-hours can be reduced. Moreover, since the laminated board of a symmetrical structure can be comprised on both sides of the core board | substrate 17, a curvature can be suppressed and the damage | damage by workability | operativity, a catch to a manufacturing facility, etc. can also be suppressed.

  Next, as shown in FIG. 2 (2), the first carrier metal foil is physically peeled off at the interface between the first carrier metal foil 10 and the second carrier metal foil 11 of the multilayer metal foil 9. On the surface of the first carrier metal foil 10, there may be a case where foreign matters such as resin powder from a prepreg or the like that becomes a material of the base material 16 at the time of lamination adhere. For this reason, when forming a circuit using this first carrier metal foil 10, foreign matter such as resin powder adhered to the surface may cause defects such as disconnection or short circuit in the circuit, leading to a decrease in yield. there is a possibility. However, since the first carrier metal foil 10 is peeled and removed in this way, a circuit can be formed using the second carrier metal foil 11 to which no foreign matter such as resin powder adheres. The occurrence of defects can be suppressed, and the yield can be improved. In addition, since the first carrier metal foil can be physically peeled off, the peeling work can be easily performed by adjusting the peel strength at the interface between the first carrier metal foil 10 and the second carrier metal foil 11. it can. At this time, it is desirable that the peeling layer (not shown) at the interface between the first carrier metal foil 10 and the second carrier metal foil 11 of the multilayer metal foil 9 moves to the first carrier metal foil 10 side. Thereby, since the surface of the 2nd carrier metal foil 11 is exposed to the 2nd carrier metal foil 11 side after peeling the 1st carrier metal foil 10, it is on the 2nd carrier metal foil 11 performed by a post process. The formation of the plating resist and the pattern plating 18 are not hindered by the release layer.

  Here, in the multilayer metal foil 9, the peel strength at the interface between the second carrier metal foil 11 and the base metal foil 12 is greater than the peel strength at the interface between the first carrier metal foil 10 and the second carrier metal foil 11. It is desirable that the multilayer metal foil 9 be formed. This suppresses simultaneous peeling of the interface between the second carrier metal foil 11 and the base metal foil 12 when physically peeling at the interface between the first carrier metal foil 10 and the second carrier metal foil 11. be able to. The peel strength is 2 N / m to 50 N / m at the interface between the first carrier metal foil 10 and the second carrier metal foil 11 and the second carrier metal foil 11 and the base metal foil 12 at the initial stage before heating and pressing. The separation strength at the interface between the first carrier metal foil 10 and the second carrier metal foil 11 is the separation at the interface between the second carrier metal foil 11 and the base metal foil 12. If it is made smaller than the strength by 5 N / m to 20 N / m, it will not be peeled off by handling in the manufacturing process, but on the other hand, it is easy to peel off, and when peeling the first carrier metal foil 10 Since the second carrier metal foil 11 can be prevented from peeling off at the same time, workability is good.

  For example, as shown in Japanese Patent Application Laid-Open No. 2003-181970, Japanese Patent Application Laid-Open No. 2003-094553, and Republished Patent WO 2006/013735, the adjustment of the peel strength is performed on the second carrier metal foil 11 serving as the base of the release layer. It becomes possible by adjusting the roughness of the surface (interface with the first carrier metal foil 10), or by adjusting the plating solution composition and conditions for forming a metal oxide or alloy plating layer to be a release layer. .

  Next, as shown in FIG. 2 (3), pattern plating 18 is performed on the second carrier metal foil 11 remaining on the core substrate 17. As described above, the surface of the second carrier metal foil 11 (interface with the first carrier metal foil 10) does not adhere to foreign matters such as resin powder from the prepreg used at the time of lamination. Defects can be suppressed. The pattern plating 18 can be performed using electroplating after forming a plating resist (not shown) on the second carrier metal foil 11. As the plating resist, a photosensitive resist used in the manufacturing process of the package substrate 1 can be used. As electroplating, copper sulfate plating used in the manufacturing process of the package substrate 1 can be used.

  The multilayer metal foil 9 has a first carrier metal on the surface of a second carrier metal foil 11 provided with irregularities having an average roughness (Ra) of 0.3 μm to 1.2 μm in advance via a release layer (not shown). A multilayer metal foil 9 in which the foil 10 is laminated is desirable. Thereby, the surface of the 2nd carrier metal foil 11 after physically peeling the 1st carrier metal foil 10 with a peeling layer has the unevenness | corrugation whose average roughness (Ra) provided previously is 0.3 micrometer-1.2 micrometers. Have. Therefore, when forming a plating resist for the pattern plating 18 on the surface of the second carrier metal foil 11 (interface with the first carrier metal foil 10), the adhesion and resolution of the plating resist can be improved. This is advantageous for forming a high-density circuit. In addition, by providing unevenness on the surface of the second carrier metal foil 11 in advance, it is not necessary to roughen the surface of the second carrier metal foil 11 after the first carrier metal foil 10 is peeled off. The man-hour can be reduced.

  The surface roughness of the irregularities provided on the surface of the second carrier metal foil 11 is that the average roughness (Ra) is 0.3 to 1.2 μm, while improving the adhesion and resolution of the plating resist, This is desirable in terms of ensuring releasability after plating 18. When the average roughness (Ra) is less than 0.3 μm, the adhesion of the plating resist tends to be insufficient, and when the average roughness (Ra) exceeds 1.2 μm, the plating resist becomes difficult to follow and the adhesion is insufficient. Tend to occur. Further, when the line / space of the plating resist becomes finer than 15 μm / 15 μm, it is desirable that the average roughness (Ra) is 0.5 μm to 0.9 μm. Here, the average roughness (Ra) is an average roughness (Ra) defined by JIS B 0601 (2001), and can be measured using a stylus type surface roughness meter or the like. In addition, adjustment of average roughness (Ra) will contain the composition (additive etc.) of the electro copper plating at the time of forming copper foil as 2nd carrier metal foil, if the 2nd carrier metal foil 11 is copper foil. ) And adjusting conditions.

  Next, as shown in FIG. 3 (4), the insulating layer 3 is laminated on the second carrier metal foil 11 including the pattern plating 18 to form a laminated body 22. As the insulating layer 3, a layer generally used as the insulating layer 3 of the semiconductor element mounting package substrate 1 can be used. Examples of the insulating layer 3 include an epoxy resin and a polyimide resin. For example, an epoxy or polyimide adhesive sheet, a glass epoxy or a glass polyimide prepreg is heated and heated using a hot press or the like. It can be formed by pressing and laminating and integrating. Here, the laminated body 22 refers to one laminated on the second carrier metal foil 11 including the pattern plating 18 among those laminated and integrated. In the case where the metal foil to be the conductor layer 20 is further stacked on these resins to be the insulating layer 3 and simultaneously heated and pressurized to be laminated and integrated, this conductor layer 20 is also included. As will be described later, when the inner layer circuit 6 is formed by the conductor layer 20 or the interlayer connection 5 for connecting the conductor layer 20 is formed, the inner layer circuit 6 and the interlayer connection 5 are also included. That is, the laminate 22 is one formed on the second carrier metal foil 11 including the pattern plating 18 among those laminated and integrated with the core substrate 17.

  Next, as shown in FIGS. 3 (5) and 3 (6), the interlayer connection hole 21 may be formed to form the interlayer connection 5 and the inner layer circuit 6. The interlayer connection 5 can be formed, for example, by forming the interlayer connection hole 21 by using a so-called conformal method and then plating the interlayer connection hole 21. In this plating, electroless copper plating, electrolytic copper plating, filled via plating, or the like can be used as the thick plating after thin electroless copper plating is performed as the base plating. In order to reduce the thickness of the conductor layer 20 to be etched and make it easy to form a fine circuit, it is necessary to form a plating resist after the thin base plating and perform the thick plating by electrolytic copper plating or filled via plating. desirable. The inner layer circuit 6 can be formed, for example, by plating the interlayer connection hole 21 and then removing the unnecessary conductor layer 20 by etching.

  Next, as shown in FIGS. 4 (7) and (8) and FIGS. 5 (9) and (10), an insulating layer 3 and a conductor layer 20 are further formed on the inner circuit 6 and the interlayer connection 5, In the same manner as in FIGS. 3 (5) and (6), the inner layer circuit 6, the outer layer circuits 2, 7 and the interlayer connection 5 can be formed so as to have a desired number of layers.

  Next, as shown in FIG. 6 (11), the laminate 22 is physically separated from the core substrate 17 together with the second carrier metal foil 11 at the interface between the second carrier metal foil 11 and the base metal foil 12 of the multilayer metal foil 9. Exfoliate and separate. At this time, it is desirable that the peeling layer (not shown) at the interface between the second carrier metal foil 11 and the base metal foil 12 of the multilayer metal foil 9 is moved to the base metal foil 12 side. As a result, the surface of the second carrier metal foil 11 is exposed on the laminated body 22 side after the base metal foil 12 is peeled off, so that the etching of the second carrier metal foil 11 performed in a later step is hindered by the peel layer. It will not be done.

  Next, as shown in FIGS. 7 (12) and (13), etching is performed from the second carrier metal foil 11 side of the separated laminate 22, and at least a part of the second carrier metal foil 11 is removed. The surface of the pattern plating 18 forms a dent with respect to the surface of the insulating layer 3. 7 (12) to (14) show only the lower part of the stacked body 22 separated as shown in FIG. 6 (11). As a result, when the outer layer circuit 2 is formed, the side surface of the outer layer circuit 2 is not eroded by etching, so that no undercut occurs, so that the fine outer layer circuit 2 can be formed. Further, since the outer layer circuit 2 formed in the present invention is embedded in the insulating layer 3, not only the bottom surface of the outer layer circuit 2 but also the side surfaces on both sides are in close contact with the insulating layer 3, so that the fine circuit Even so, sufficient adhesion can be ensured. Furthermore, when an ultra-thin copper foil having a thickness of 1 μm to 5 μm is used as the second carrier metal foil 11, the second carrier metal foil 11 can be removed even with a slight etching amount, so that it is embedded in the insulating layer 3. The surface of the outer layer circuit 2 (corresponding to the surface of the noble metal plating 8) in which a dent is formed on the surface of the insulating layer 3 is flat, and when the underlying plating 23 and the noble metal plating 8 described later are performed thereon, Connection reliability at the time of wire bonding and flip chip connection can be ensured, and it is suitable for use as a connection terminal with a semiconductor element. Further, since the connection terminal with the semiconductor element can be provided in the outer layer circuit 2 at a position overlapping the interlayer connection 5 in plan view, the connection terminal with the semiconductor element is provided immediately above or immediately below the interlayer connection 5. It is possible to reduce the size and increase the density. The depth of the recess with respect to the surface of the insulating layer 3 is preferably about 3 μm to 7 μm because the thickness of the base plating and the noble metal plating described later can be secured.

  Next, as shown in FIG. 7 (14), the base plating 23 and the noble metal plating 8 are performed on the surface of the pattern plating 18 in which dents are formed on the surface of the insulating layer 3. It should be flush with the surface of the insulating layer 3. In flip chip connection using solder, if the surface and side surfaces of the outer circuit 2 that is the connection terminal are exposed, solder may wrap around the side surfaces of the connection terminals, which may cause a short circuit between the connection terminals. It is required that the outer layer circuit 2 to be a terminal is embedded in the insulating layer 3 and the connection terminal and the insulating layer 3 are flat. On the other hand, in the wire bonding connection, the nickel plating as the base plating 23 is required to have a certain thickness. In the present invention, since the base plating 23 and the noble metal plating 8 are provided on the surface of the pattern plating 18 in which a recess is formed on the surface of the insulating layer 3, the surface of the connection terminal can be obtained even if the nickel plating is thickened. However, the flatness with respect to the surface of the insulating layer 3 is not lost. For this reason, even in a package substrate in which flip chip connection and wire bond connection are mixed, it is possible to satisfy the connection reliability of both of them. Therefore, it is possible to provide a package substrate in which the flatness of the connection terminals and the insulating layer 3 and the thickness of the base plating 23 are ensured along with the miniaturization of the connection terminals. As the base plating 23, it is desirable to use nickel plating or nickel plating and palladium plating. The plating thickness is 3 μm to 7 μm for nickel and 0.1 μm to 0.5 μm for palladium plating. When the outer layer circuit 2 is made of copper, the precious metal plating can be performed by heating when mounting the semiconductor element. This is desirable in that diffusion to the eight layers can be suppressed and connection reliability can be ensured. As the noble metal plating 8, it is desirable to use gold plating or silver plating. These thicknesses are preferably 0.03 μm to 0.5 μm. In addition, as for nickel plating, palladium plating, and gold plating, any of electrolytic plating and electroless plating can be used.

  According to the method for manufacturing a package substrate of the present invention, a package substrate having a fine embedded circuit that is flat at a position overlapping the interlayer connection 5 and has a noble metal plating on the surface can be formed, and wire bonding connection and flip chip connection are possible. Even in the case where both are mixed, the package substrate 1 capable of ensuring the connection reliability can be formed.

  Examples of the present invention will be described below, but the present invention is not limited to the examples.

Example 1
First, as shown in FIG. 1, a multilayer metal foil 9 in which a first carrier metal foil 10, a second carrier metal foil 11, and a base metal foil 12 were laminated in this order was prepared. The first carrier metal foil 10 is a 9 μm copper foil, the second carrier metal foil 11 is a 3 μm ultrathin copper foil, and the base metal foil 12 is an 18 μm copper foil. A release layer was provided on the surface of the base metal foil 12 (interface with the second carrier metal foil 11) so that physical peeling was possible. Further, the surface of the second carrier metal foil 11 (interface with the first carrier metal foil 10) was provided with irregularities having an average roughness (Ra) of 0.3 μm to 1.2 μm in advance. In addition, a release layer was provided on the unevenness, that is, on the interface with the first carrier metal foil 10 so as to allow physical peeling. The peeling layer at the interface between the base metal foil 12 and the second carrier metal foil 11 and the interface between the second carrier metal foil 11 and the first carrier metal foil 10 is Ni 30 g / L, Mo 3.0 g / L, It formed by forming a metal oxide layer using the plating bath which has a composition of acid 30g / L. The peel strength was adjusted by adjusting the amount of metal oxide forming the peel layer by adjusting the current. The peel strength at this time was 47 N / m at the interface between the base metal foil 12 and the second carrier metal foil 11 and 29 N / m at the interface between the second carrier metal foil 11 and the first carrier metal foil 10.

  Next, as shown in FIG. 2 (1), the base metal foil 12 side of the multilayer metal foil 9 and the base material 16 were laminated to form a core substrate 17. A glass epoxy prepreg was used as the substrate 16, and the multilayer metal foils 9 were stacked on both upper and lower sides of the prepreg, and were laminated and integrated by heating and pressing using a hot press.

  Next, as shown in FIG. 2 (2), the first carrier metal foil 10 was physically peeled off at the interface between the first carrier metal foil 10 and the second carrier metal foil 11 of the multilayer metal foil 9.

  Next, as shown in FIG. 2 (3), pattern plating 18 was performed on the second carrier metal foil 11 remaining on the core substrate 17. The pattern plating 18 was formed using copper sulfate electroplating after forming a photosensitive plating resist on the second carrier metal foil 11. The line / space of the formed pattern plating 18 is 10 μm / 10 μm, 15 μm / 15 μm, 20 μm / 20 μm, and the thickness is 10 μm.

  Next, as shown in FIG. 3 (4), the insulating layer 3 was laminated on the second carrier metal foil 11 including the pattern plating 18 to form a laminated body 22. The insulating layer 3 was formed by laminating and integrating an epoxy adhesive sheet by heating and pressing using a hot press.

  Next, as shown in FIGS. 3 (5) and (6), the interlayer connection 5 and the inner layer circuit 6 were formed. The interlayer connection 5 was formed by forming the interlayer connection hole 21 using a conformal method and then plating the interior of the interlayer connection hole 21. In this plating, thin electroless copper plating was performed as a base plating, a photosensitive plating resist was formed, and thick plating was performed by copper sulfate electroplating. Thereafter, the inner layer circuit 6 was formed by removing the unnecessary conductor layer 20 by etching.

  Next, as shown in FIGS. 4 (7) and (8) and FIGS. 5 (9) and (10), an insulating layer 3 and a conductor layer 20 are further formed on the inner circuit 6 and the interlayer connection 5, The inner layer circuit 6, the outer layer circuits 2 and 7, and the interlayer connection 5 were formed to form a laminate 22 having four conductor layers 20.

  Next, as shown in FIG. 6 (11), the laminate 22 is physically separated from the core substrate 17 together with the second carrier metal foil 11 at the interface between the second carrier metal foil 11 and the base metal foil 12 of the multilayer metal foil 9. Peeled off and separated.

  Next, as shown in FIGS. 7 (12) and (13), etching is performed from the second carrier metal foil 11 side of the separated laminate 22, and at least a part of the second carrier metal foil 11 is removed. The surface of the pattern plating 18 formed a recess with respect to the surface of the insulating layer 3. The depth of the recess with respect to the surface of the insulating layer 3 was about 5.3 μm.

  Next, as shown in FIG. 7 (14), the base plating 23 and the noble metal plating 8 are performed on the surface of the pattern plating 18 in which dents are formed on the surface of the insulating layer 3. It was made to be flush with the surface of the insulating layer 3. As the base plating 23, electroless nickel plating (thickness 5 μm) and electroless palladium plating (thickness 0.2 μm) were performed. Further, as the noble metal plating 8, electroless gold plating (thickness: 0.1 μm) was performed.

(Example 2)
The peel strengths at the interface between the base metal foil 12 and the second carrier metal foil 11 and at the interface between the second carrier metal foil 11 and the first carrier metal foil 10 are all Ni 30 g / L, Mo 3.0 g / L, By changing the current when forming the metal oxide layer using a plating bath having a composition of acid 30 g / L, the amount of metal oxide forming the release layer was adjusted and changed. The peel strength at this time was 23 N / m at the interface between the base metal foil 12 and the second carrier metal foil 11, and 18 N / m at the interface between the second carrier metal foil 11 and the first carrier metal foil 10.

  The surface of the pattern plating 18 with respect to the surface of the insulating layer 3 (corresponding to the surface of the outer layer circuit 2) is changed by changing the etching amount from the second carrier metal foil 11 side of the laminated body 22 after separation produced in the same manner as in Example 1. )) Was set to a depth of about 3.1 μm.

  Next, as shown in FIG. 7 (14), electroless nickel plating (thickness 3 μm) and electroless as the base plating 23 on the surface of the pattern plating 18 in which a recess is formed on the surface of the insulating layer 3. Palladium plating (thickness 0.1 μm) was performed. Moreover, as the noble metal plating 8, electroless gold plating (thickness 0.1 μm) was performed. A package substrate was manufactured in the same manner as in Example 1 except for this.

(Example 3)
The peel strengths at the interface between the base metal foil 12 and the second carrier metal foil 11 and at the interface between the second carrier metal foil 11 and the first carrier metal foil 10 are all Ni 30 g / L, Mo 3.0 g / L, By changing the current when forming the metal oxide layer using a plating bath having a composition of acid 30 g / L, the amount of metal oxide forming the release layer was adjusted and changed. The peel strength at this time was 15 N / m at the interface between the base metal foil 12 and the second carrier metal foil 11, and 2 N / m at the interface between the second carrier metal foil 11 and the first carrier metal foil 10.

  The surface of the pattern plating 18 with respect to the surface of the insulating layer 3 (corresponding to the surface of the outer layer circuit 2) is changed by changing the etching amount from the second carrier metal foil 11 side of the laminated body 22 after separation produced in the same manner as in Example 1. )) Was about 8 μm deep.

  Next, as shown in FIG. 7 (14), electroless nickel plating (thickness 7 μm) and electroless are formed as the base plating 23 on the surface of the pattern plating 18 in which a recess is formed on the surface of the insulating layer 3. Palladium plating (thickness 0.5 μm) was performed. Further, as the noble metal plating 8, electroless gold plating (thickness 0.5 μm) was performed. A package substrate was manufactured in the same manner as in Example 1 except for this.

Example 4
The peel strengths at the interface between the base metal foil 12 and the second carrier metal foil 11 and at the interface between the second carrier metal foil 11 and the first carrier metal foil 10 are all Ni 30 g / L, Mo 3.0 g / L, By changing the current when forming the metal oxide layer using a plating bath having a composition of acid 30 g / L, the amount of metal oxide forming the release layer was adjusted and changed. The peel strength at this time was 68 N / m at the interface between the base metal foil 12 and the second carrier metal foil 11, and 48 N / m at the interface between the second carrier metal foil 11 and the first carrier metal foil 10.

  The surface of the pattern plating 18 with respect to the surface of the insulating layer 3 (corresponding to the surface of the outer layer circuit 2) is changed by changing the etching amount from the carrier metal foil 11 side of the separated laminate 22 produced in the same manner as in Example 1. The depth of the recess was about 5.3 μm.

  Next, as shown in FIG. 7 (14), electroless nickel plating (thickness 5 μm) and electroless electroplating as the base plating 23 on the surface of the pattern plating 18 in which a recess is formed on the surface of the insulating layer 3. Palladium plating (thickness 0.2 μm) was performed. Moreover, as the noble metal plating 8, electroless gold plating (thickness 0.1 μm) was performed. A package substrate was manufactured in the same manner as in Example 1 except for this.

(Example 5)
The peel strengths at the interface between the base metal foil 12 and the second carrier metal foil 11 and at the interface between the second carrier metal foil 11 and the first carrier metal foil 10 are all Ni 30 g / L, Mo 3.0 g / L, By changing the current when forming the metal oxide layer using a plating bath having a composition of acid 30 g / L, the amount of metal oxide forming the release layer was adjusted and changed. The peel strength at this time was 43 N / m at the interface between the base metal foil 12 and the second carrier metal foil 11 and 28 N / m at the interface between the second carrier metal foil 11 and the first carrier metal foil 10.

  The surface of the pattern plating 18 with respect to the surface of the insulating layer 3 (corresponding to the surface of the outer layer circuit 2) is changed by changing the etching amount from the second carrier metal foil 11 side of the laminated body 22 after separation produced in the same manner as in Example 1. )) Was set to a depth of about 3.1 μm.

  Next, as shown in FIG. 7 (14), electroless nickel plating (thickness 3 μm) and electroless as the base plating 23 on the surface of the pattern plating 18 in which a recess is formed on the surface of the insulating layer 3. Palladium plating (thickness 0.1 μm) was performed. Further, as the noble metal plating 8, electroless gold plating (thickness: 0.03 μm) was performed. A package substrate was manufactured in the same manner as in Example 1 except for this.

(Example 6)
The peel strengths at the interface between the base metal foil 12 and the second carrier metal foil 11 and at the interface between the second carrier metal foil 11 and the first carrier metal foil 10 are all Ni 30 g / L, Mo 3.0 g / L, By changing the current when forming the metal oxide layer using a plating bath having a composition of acid 30 g / L, the amount of metal oxide forming the release layer was adjusted and changed. The peel strength at this time was 22 N / m at the interface between the base metal foil 12 and the second carrier metal foil 11 and 4 N / m at the interface between the second carrier metal foil 11 and the first carrier metal foil 10.

  The surface of the pattern plating 18 with respect to the surface of the insulating layer 3 (corresponding to the surface of the outer layer circuit 2) is changed by changing the etching amount from the second carrier metal foil 11 side of the laminated body 22 after separation produced in the same manner as in Example 1. )) Was about 8 μm deep.

  Next, as shown in FIG. 7 (14), electroless nickel plating (thickness 7 μm) and electroless are formed as the base plating 23 on the surface of the pattern plating 18 in which a recess is formed on the surface of the insulating layer 3. Palladium plating (thickness 0.5 μm) was performed. Further, as the noble metal plating 8, electroless gold plating (thickness 0.5 μm) was performed. A package substrate was manufactured in the same manner as in Example 1 except for this.

  In Table 1, for Examples 1 to 6, the peel strength at the interface between the first carrier metal foil 10 and the second carrier metal foil 11, the peel strength at the interface between the second carrier metal foil 11 and the base metal foil 12, and handling The presence or absence of peeling of the first carrier metal foil 10 and the second carrier metal foil 11 is shown. The symbol “◯” in the column of peeling of the metal foil at the time of handling in Table 1 indicates that there was no peeling. In all of Examples 1 to 6, the interface between the first carrier metal foil 10 and the second carrier metal foil 11 and the interface between the second carrier metal foil 11 and the base metal foil 12 are peeled off by handling in the manufacturing process. There was no.

1: Semiconductor device mounting package substrate 2: outer layer circuit or embedded circuit 3: insulating layer 4: solder resist 5: interlayer connection 6: inner layer circuit 7: outer layer circuit 8: noble metal plating 9: multilayer metal foil 10: first carrier metal Foil 11: second carrier metal foil 12: base metal foil 16: base material 17: core substrate 18: pattern plating 20: conductor layer 21: interlayer connection hole 22: laminate 23: base plating

Claims (4)

  1. A first carrier metal foil, a second carrier metal foil, and a base metal foil are laminated in this order, and between the first carrier metal foil and the second carrier metal foil and between the second carrier metal foil and the base metal foil. Preparing a multilayer metal foil provided with a release layer between each of them, and laminating the base metal foil side of the multilayer metal foil and a base material to form a core substrate;
    Physically peeling the first carrier metal foil at the interface between the first carrier metal foil and the second carrier metal foil of the multilayer metal foil;
    Performing pattern plating on the second carrier metal foil remaining on the core substrate;
    Laminating an insulating layer on the second carrier metal foil including the pattern plating to form a laminate;
    Physically separating the laminate from the core substrate together with the second carrier metal foil at the interface between the second carrier metal foil and the base metal foil of the multilayer metal foil; and
    Etching is performed from the second carrier metal foil side of the separated laminate to remove at least a part of the second carrier metal foil, and the surface of the pattern plating forms a recess with respect to the surface of the insulating layer. The process of
    Performing a base plating and a noble metal plating on the surface of the pattern plating on which the dents are formed, such that the surface of the noble metal plating is flush with the surface of the insulating layer;
    Manufacturing method of semiconductor device mounting package substrate having
  2. In claim 1,
    A method of manufacturing a package substrate for mounting a semiconductor element, wherein the base plating is nickel plating or nickel plating and palladium plating, and the noble metal plating is gold plating or silver plating.
  3. In claim 1 or 2,
    The multilayer metal foil is a multilayer metal foil in which the peel strength at the interface between the second carrier metal foil and the base metal foil is greater than the peel strength at the interface between the first carrier metal foil and the second carrier metal foil. Manufacturing method of semiconductor device mounting package substrate.
  4. In any one of Claim 1 to 3,
    The multi-layer metal foil is a multi-layer metal foil in which the first carrier copper foil is laminated on the surface of the second carrier copper foil provided with irregularities having an average roughness (Ra) of 0.3 μm to 1.2 μm in advance. Method for manufacturing a package substrate.
JP2010218900A 2010-09-29 2010-09-29 Manufacturing method of package substrate for mounting semiconductor device Active JP5716948B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2010218900A JP5716948B2 (en) 2010-09-29 2010-09-29 Manufacturing method of package substrate for mounting semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2010218900A JP5716948B2 (en) 2010-09-29 2010-09-29 Manufacturing method of package substrate for mounting semiconductor device

Publications (2)

Publication Number Publication Date
JP2012074576A JP2012074576A (en) 2012-04-12
JP5716948B2 true JP5716948B2 (en) 2015-05-13

Family

ID=46170439

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2010218900A Active JP5716948B2 (en) 2010-09-29 2010-09-29 Manufacturing method of package substrate for mounting semiconductor device

Country Status (1)

Country Link
JP (1) JP5716948B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017059728A (en) * 2015-09-17 2017-03-23 味の素株式会社 Method for manufacturing wiring board
CN107241876B (en) * 2016-03-28 2019-05-07 上海美维科技有限公司 A kind of no core plate single side is sunken cord the processing method of printed circuit board

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4691763B2 (en) * 2000-08-25 2011-06-01 イビデン株式会社 Method for manufacturing printed wiring board
JP2008028302A (en) * 2006-07-25 2008-02-07 Sumitomo Bakelite Co Ltd Multi-layer circuit board and semiconductor device using it
JP5214139B2 (en) * 2006-12-04 2013-06-19 新光電気工業株式会社 Wiring board and manufacturing method thereof
JP5410660B2 (en) * 2007-07-27 2014-02-05 新光電気工業株式会社 Wiring board and its manufacturing method, electronic component device and its manufacturing method

Also Published As

Publication number Publication date
JP2012074576A (en) 2012-04-12

Similar Documents

Publication Publication Date Title
US7957154B2 (en) Multilayer printed circuit board
US7115818B2 (en) Flexible multilayer wiring board and manufacture method thereof
JPWO2010024233A1 (en) Wiring board capable of incorporating functional elements and method for manufacturing the same
JP5101169B2 (en) Wiring board and manufacturing method thereof
JP2008515241A (en) Interconnect element structure and manufacturing method, and multilayer wiring board including interconnect element
US8745860B2 (en) Method for manufacturing printed wiring board
US8177577B2 (en) Printed wiring board having a substrate with higher conductor density inserted into a recess of another substrate with lower conductor density
TW200930163A (en) Method for manufacturing printed wiring board
TW201041469A (en) Coreless packaging substrate, carrier thereof, and method for manufacturing the same
CN1454045A (en) Wiring transfer sheet material and producing method thereof, wiring substrate and producing method thereof
TWI308382B (en) Package structure having a chip embedded therein and method fabricating the same
US8445790B2 (en) Coreless substrate having filled via pad and method of manufacturing the same
JP4171499B2 (en) Electronic device substrate and manufacturing method thereof, and electronic device and manufacturing method thereof
EP2592915A1 (en) Laminated wiring board and manufacturing method for same
JP2013243345A (en) Ultrathin buried die module and method of manufacturing the same
US7377030B2 (en) Wiring board manufacturing method
US8069558B2 (en) Method for manufacturing substrate having built-in components
CN103119710B (en) The manufacture method of mounting semiconductor element base plate for packaging
JP6377661B2 (en) Manufacturing method of multilayer printed wiring board
TW200824055A (en) Carrier structure embedded with chip and method for fabricating thereof
JP4914474B2 (en) Multilayer printed circuit board manufacturing method
CN1254856C (en) Manufacturing method of circuit device
JP4460341B2 (en) Wiring board and manufacturing method thereof
JP2006019591A (en) Method for manufacturing wiring board and wiring board
US20130081866A1 (en) Printed wiring board

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20130826

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20140613

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20140619

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20140808

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20150219

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20150304