JP5769001B2 - Semiconductor device mounting package substrate and semiconductor package - Google Patents

Description

  The present invention relates to a semiconductor device mounting package substrate and a semiconductor package capable of increasing the density, and more particularly to a semiconductor device mounting package substrate and a semiconductor package provided with a semiconductor device having bumps and flip chip connection terminals.

  Flip chip connection is used as a method for electrically connecting the connection terminals of a semiconductor element and a package substrate for mounting a semiconductor element (hereinafter referred to as “package substrate”). In this flip chip connection, a preliminary solder is formed on the flip chip connection terminal of the package substrate for the purpose of forming a good solder fillet between the bump of the semiconductor element, and the preliminary solder and the bump of the semiconductor element are formed. In many cases, a method is used in which the amount of solder is secured by both solders and connected to bumps provided on a semiconductor element. On the other hand, along with miniaturization and high density of electronic components, it is necessary to arrange connection terminals with semiconductor elements at high density, and miniaturization of flip chip connection terminals is required.

  When the flip chip connection terminal is miniaturized, the area of the connection terminal on which the preliminary solder is formed is reduced, so that the amount of the preliminary solder formed on the flip chip connection terminal is also reduced. There is a problem that the formation of the solder fillet to be formed becomes insufficient and the connection reliability is lowered. Further, when an amount of preliminary solder sufficient for connection to a semiconductor element is formed on a fine flip chip connection terminal, as shown in FIG. 9, in a general manufacturing method, the flip chip connection terminal 26 is a package. Since it is formed in a convex shape with respect to the surface of the substrate 1, there is a problem in that the preliminary solder 19 wraps around the side surface of the flip chip connection terminal 26 and bridges the preliminary solder 19 between the adjacent flip chip connection terminals 26. is there. That is, even if the solder for forming the preliminary solder 19 on the flip chip connection terminal 26 is supplied, a considerable proportion of the solder is used to cover the side surface of the flip chip connection terminal 26 and is necessary for the connection. This not only reduces the proportion of the pre-solder 19 that can be used to form the solder fillet, but also creates a bridge with the adjacent flip chip connection terminal 26.

  As a method for solving such a problem, a method of increasing the amount of solder in this region by forming a wiring pattern in a region to be a flip chip connection terminal on a package substrate relatively long, and flip chip A method (Patent Document 2) is disclosed in which the amount of preliminary solder on a flip chip connection terminal is increased by partially increasing the width of a wiring pattern in a region to be a connection terminal as compared with other regions.

JP 2002-329744 A JP 2005-101137 A

  According to the methods disclosed in Patent Documents 1 and 2 described above, the amount of preliminary solder on the flip chip connection terminal for connection to a semiconductor element can be secured to some extent. However, as shown in FIG. 9, the circuit pattern forming the flip chip connection terminal 26 is a circuit pattern formed in a convex shape from the surface of the package substrate 1 (hereinafter, sometimes referred to as “convex circuit”). Only the bottom surface of the convex circuit 32 is in close contact with the surface of the insulating layer 3 of the package substrate 1. In addition, since the convex circuit 32 is generally formed by a method involving etching such as a semi-additive method, so-called undercut occurs, and as a result, the width of the circuit pattern is thicker than the top (surface side). Narrows in the middle of the direction and at the bottom (bottom side). For this reason, when the flip chip connection terminal 26 is miniaturized, the contact force is reduced due to a decrease in the contact area between the flip chip connection terminal 26 and the insulating layer 3 below and the width of the circuit pattern. There is a possibility that the flip chip connection terminal 26 may be peeled off only by applying a slight external force.

  The present invention has been made in view of the above-described problems, and can form a flip chip connection terminal that secures an adhesive force even if it is fine, and a preliminary solder necessary for flip chip connection with a bump of a semiconductor element. An object of the present invention is to provide a semiconductor device mounting package substrate and a semiconductor package that can cope with high density and have high reliability by providing flip-chip connection terminals with a sufficient amount.

The present invention relates to the following.
(1) An insulating layer, an embedded circuit provided so that the upper surface is exposed on the surface of the insulating layer and the side surface and the bottom surface are embedded in and in close contact with the insulating layer, and the insulating layer and the embedded circuit and a provided a photosensitive solder resist, the resolution of the embedded wiring patterns arranged in an opening opening width is larger than the limit of the solder resist to form a flip-chip connection terminal, the flip Chip connection terminals are covered with a pre-solder having a thickness of 3 μm or more and 20 μm or less , and the flip chip connection terminals have a longitudinal direction and a short direction in plan view, and are arranged side by side in the opening of the solder resist The dimension of the flip chip connection terminal in the short direction is 20 μm or less, and one side in the longitudinal direction of the flip chip connection terminal is an opening of the solder resist. Therefore, the other end of the flip chip connection terminal in the longitudinal direction is disposed in the opening of the solder resist, and one of the longitudinal directions is defined by the opening of the solder resist. The semiconductor device mounting package substrate having a dimension of less than the resolution limit of the solder resist or 100 μm or less.
(2) The package substrate for mounting a semiconductor element according to (1), wherein a via is connected to a bottom surface of an embedded wiring pattern forming a flip chip connection terminal.
(3) The package substrate for mounting a semiconductor element according to (1) or (2), wherein a convex shape is formed on a part of the flip chip connection terminal in the longitudinal direction.
(4) The package substrate for mounting a semiconductor element according to any one of (1) to (3), wherein a concave shape is formed in a part of the flip chip connection terminal in the longitudinal direction.
(5) In any one of (1) to (4), a semiconductor element mounting package substrate provided with embedded circuits extending on both sides or one side in the longitudinal direction of the flip chip connection terminal.
(6) The package substrate for mounting a semiconductor element according to any one of (1) to (5), wherein a part of the flip chip connection terminal has a portion extended in a short direction.
(7) A semiconductor package in which bumps of a semiconductor element are mounted on a flip chip connection terminal of a package substrate for mounting a semiconductor element according to any one of (1) to (6) by flip chip connection.

  According to the present invention, it is possible to form a flip chip connection terminal having a sufficient adhesion even if it is fine, and a flip chip connection terminal having an amount of preliminary solder necessary for flip chip connection with a bump of a semiconductor element. By providing, it is possible to provide a package substrate for mounting a semiconductor element and a semiconductor package which can cope with high density and have excellent reliability.

FIG. 4A is a plan view, FIG. 5B is a cross-sectional view taken along the line A-A ′, and FIG. 4C is a cross-sectional view taken along the line B-B ′. 2A is a plan view of the vicinity of a flip chip connection terminal of a package substrate for mounting a semiconductor element of the present invention, and FIG. 2A is a plan view of the vicinity of a flip chip connection terminal of a package substrate for mounting a semiconductor element of the present invention, and FIG. 2A is a plan view of the vicinity of a flip chip connection terminal of a package substrate for mounting a semiconductor element of the present invention, and FIG. 2A is a plan view of the vicinity of a flip chip connection terminal of a package substrate for mounting a semiconductor element of the present invention, and FIG. FIG. 4A is a plan view, FIG. 5B is a cross-sectional view taken along the line A-A ′, and FIG. 4C is a cross-sectional view taken along the line B-B ′. FIG. 4A is a plan view, FIG. 5B is a cross-sectional view taken along the line A-A ′, and FIG. 4C is a cross-sectional view taken along the line B-B ′. It is sectional drawing of the flip chip connection terminal vicinity of the package for semiconductor element mounting of this invention. It is (a) top view, (b) A-A 'sectional view, (c) B-B' sectional view in the vicinity of a flip chip connection terminal of a conventional package substrate for mounting semiconductor elements.

  An example of a package substrate for mounting a semiconductor element of the present invention will be described below with reference to FIGS.

  As a first example of a semiconductor device mounting package substrate (hereinafter referred to as a “package substrate”) of the present invention, as shown in FIG. 1, the upper surface is exposed on the surface of the insulating layer 3 and the insulating layer 3. Embedded circuit 2 provided in this manner, and solder resist 4 provided on insulating layer 3 and embedded circuit 2, and embedded circuit 2 disposed in opening 31 of solder resist 4. Forming a flip chip connection terminal 26, and the semiconductor chip mounting package substrate 1 in which the flip chip connection terminal 26 is covered with a preliminary solder 19 having a thickness of 3 μm or more. According to this configuration, the flip chip connection terminal 26 is formed by the embedded circuit 2 whose upper surface is exposed on the surface of the insulating layer 3. For this reason, since the side surface and the bottom surface of the flip chip connection terminal 26 are embedded and fixed in the insulating layer 3, the embedded circuit 2 forming the flip chip connection terminal 26 has a fine line / space level of 20 μm / 20 μm or less. Even with a simple circuit pattern, it is possible to form the flip-chip connection terminal 26 that secures the adhesion to the insulating layer 3. In the case of having the embedded circuit 2 extended on both sides in the longitudinal direction of the flip chip connecting terminal 26, the embedded circuit 2 fixes the flip chip connecting terminal 26 from both sides. However, in the present invention, compared to the convex circuit 32 as shown in FIG. 9, it is possible to form the flip-chip connection terminal 26 that ensures a close contact with the insulating layer 3 even if it is fine. For this reason, as shown in FIG. 5, it is possible to provide the embedded circuit 2 extended only on one side in the longitudinal direction of the flip chip connection terminal 26. In this case, the size of the flip chip connection terminal 26 is reduced. Therefore, it is desirable in that the density can be increased. Moreover, as shown in FIG. 6, it is also possible to provide both the embedded circuit 2 extended to the one side and both sides of the flip chip connection terminal 26 in the longitudinal direction. As described above, the embedded circuit 2 extended in the longitudinal direction of the flip chip connection terminal 26 may be provided on both sides of the flip chip connection terminal 26 in the longitudinal direction or may be provided on only one side. Can be increased. Further, since the flip chip connection terminal 26 is covered with the preliminary solder 19 having a thickness of 3 μm or more, it is possible to secure the amount of solder necessary for the flip chip connection with the bump 25 of the semiconductor element 15. Therefore, it is possible to provide the package substrate 1 for mounting a semiconductor element that can cope with high density and has excellent reliability.

  The insulating layer of the present invention refers to an insulating substrate, a core substrate, a film, an interlayer insulating layer, a buildup layer and the like formed using an organic insulating material. Examples of such an insulating layer include those formed by heating and pressing a prepreg obtained by impregnating a glass cloth with an epoxy resin or a polyimide resin.

  The embedded circuit of the present invention refers to a circuit provided so that at least a part of the bottom surface and side surfaces are embedded in the insulating layer, and at least the top surface is exposed on the surface of the insulating layer. In such an embedded circuit, for example, a metal foil is used as a power feeding layer, a predetermined circuit pattern is formed thereon by pattern electroplating, an insulating layer is formed on the circuit pattern, and the circuit pattern is embedded in the insulating layer. Thereafter, the metal foil serving as the power feeding layer is removed by etching or the like, so that the surface of the circuit pattern embedded in the pattern insulating layer is exposed from the insulating layer, which can be formed by a so-called transfer method.

  The solder resist of the present invention protects the surface of the package substrate so that the preliminary solder does not adhere to portions other than the embedded circuit serving as the flip chip connection terminal. Further, the opening provided in the solder girest defines a portion to be the flip chip connection terminal in the embedded circuit, so that the embedded circuit in the opening forms the flip chip connection terminal. As the solder resist, a photosensitive solder resist is preferable because a minute opening of a level of 100 μm in length × 100 μm in width for forming a flip chip connection terminal can be formed with high accuracy.

  The flip chip connection terminal of the present invention refers to a connection terminal used for mounting a semiconductor element on a package substrate by flip chip connection. Flip chip connection refers to a method of connecting the active element surface of a semiconductor element to the package substrate. Bumps as electrodes are formed on the semiconductor element, and the semiconductor element is turned over to match the mounting position on the package substrate. Thereafter, the bumps of the semiconductor element are connected to the flip chip connection terminals formed on the package substrate. The flip-chip connection terminal of the present invention is not only a connection part that actually contacts the bump of the semiconductor element, but is an embedded circuit connected to the bump of the semiconductor element, and includes an insulating layer within the opening of the solder resist. The part exposed on the surface. The surface of the flip chip connection terminal may be provided with protective plating such as nickel / gold plating or nickel / palladium / gold plating in order to prevent the surface from being oxidized and ensure wettability of the preliminary solder.

  The preliminary solder of the present invention refers to solder provided on a flip chip connection terminal for flip chip connection with a semiconductor element. The preliminary solder can be formed by a method of printing solder paste and reflowing, or other known methods. As an example of the solder paste, a solder particle such as Sn—Pb-based or Sn—Ag—Cu-based solder particles used for mounting electronic components is mixed with rosin or an organic solvent. A metal mask, a silk screen, or the like can be used for printing the solder paste. The reflow can be performed using infrared reflow, hot air reflow, VPS (vapor phase soldering) reflow, or the like generally used in mounting electronic components. Although the reflow conditions differ depending on the solder paste, for example, a Sn—Pb system may have a peak temperature of about 240 ° C., and a Sn—Ag—Cu system may have a peak temperature of about 260 ° C.

  In the package substrate of the present invention, the flip chip connection terminal is covered with a preliminary solder having a thickness of 3 μm or more. If the thickness of the preliminary solder is less than 3 μm, it is not sufficient to form a solder fillet between the flip chip connection terminal and the bump of the semiconductor element, and it is difficult to ensure connection reliability. On the other hand, when the thickness of the preliminary solder exceeds 20 μm, there is a possibility that the preliminary solder and the solder bridge on the adjacent flip chip connecting terminals are generated. For this reason, the thickness of the preliminary solder is desirably 3 μm or more and 20 μm or less. In general, since the top surface of the flip chip connection terminal is a long and narrow rectangle in plan view, the preliminary solder formed by reflowing solder paste or the like is formed in a substantially semi-cylindrical shape (kamaboko shape) due to the surface tension of the solder. Is done. For this reason, the thickness of the preliminary solder is formed to be the thickest at substantially the center in the longitudinal direction (length direction) and the short direction (width direction) of the flip chip connection terminal. Therefore, in the present invention, the thickness of the preliminary solder is determined so that the step between the solder resist surface and the solder surface is a non-contact type at approximately the center in the longitudinal direction (length direction) and the short direction (width direction) of the flip chip connection terminal. It was determined by measurement using a level difference measuring machine.

  As a second example of the package substrate of the present invention, as shown in FIG. 2, there is one in which a via 18 is connected to the bottom surface of the embedded circuit 2 including the flip chip connection terminal 26. Note that the preliminary solder 19 is omitted. In FIG. 2, vias 18 are formed on both the bottom surface of the flip chip connection terminal 26 and the bottom surface of the embedded circuit 2 extending from the flip chip connection terminal 26 in the longitudinal direction. 18 may be formed. That is, in this second example, the bottom surface of the flip chip connection terminal 26 embedded in the insulating layer 3, the bottom surface of the embedded circuit 2 extending in the longitudinal direction from the flip chip connection terminal 26, or both of them. A via 18 is formed on the bottom surface of. Since the via 18 is connected to the bottom surface in this way, the flip chip connection terminal 26 or the embedded circuit 2 extended in the longitudinal direction from the flip chip connection terminal 26 is fixed to the insulating layer 3 by the via 18. It is possible to further strengthen the adhesion between the flip chip connection terminal 26 and the insulating layer 3 than in the first example.

  In the present invention, the via is used to connect the layers of the wiring layer provided in multiple layers on the package substrate. For example, after a hole for interlayer connection of the wiring layer is formed by a laser or the like, plating or the like is formed in the hole. Can be formed. In order to increase the connection area between the bottom surface of the flip chip connection terminal and the bottom surface of the embedded circuit extending in the longitudinal direction from the flip chip connection terminal and the via, the via is preferably formed by so-called filled via plating.

  As a third example of the package substrate of the present invention, as shown in FIG. 3, there is one in which a convex shape 27 is formed on a part of the flip chip connection terminal 26 in the longitudinal direction. Note that the preliminary solder 19 is omitted. The convex shape 27 can be formed, for example, by forming a plating resist and pattern plating on a part of the portion that becomes the flip chip connection terminal 26 of the embedded circuit. Although not shown, for example, after forming an embedded circuit in which a part of the side surface and the upper surface protrude from the surface of the insulating layer 3, an etching resist is formed, and a part of the protruded embedded circuit is left protruding. The other portions can also be formed by etching so as to be flush with the surface of the insulating layer 3. The height of the convex shape 27 is desirably about 3 μm to 8 μm, and the range in which the convex shape 27 is provided is 50% to 100% of the dimension in the short direction (width direction) of the flip chip connection terminal 26, and the flip chip connection terminal It is desirable that it is about 10% to 70% of the dimension in the longitudinal direction (length direction) of 26. Thus, by forming the convex shape 27 on a part of the flip chip connection terminal 26 in the longitudinal direction, solder accumulates on the stepped portion of the convex shape 27 (not shown), so that compared to the case where the surface is flat, The amount of solder disposed on the flip chip connection terminal 26 can be increased. Further, the convex shape 27 becomes a trigger for attracting other portions of the solder, and the solder aggregates around the convex shape 27, so that a protruding solder pool is formed at a predetermined position in the longitudinal direction of the flip chip connection terminal 26. You can also. Therefore, a protruding portion on the flip chip connection terminal 26 can be provided in correspondence with the position of the bump of the semiconductor element mounted on the flip chip connection terminal 26. Therefore, the bump of the flip chip connection terminal 26 and the semiconductor element can be provided. Can be securely connected.

  As a fourth example of the package substrate of the present invention, as shown in FIG. 4, there is one in which a recessed shape 28 is formed in a part of the flip chip connection terminal 26 in the longitudinal direction. Note that the preliminary solder 19 is omitted. Although not shown in the drawing, the recessed shape 28 is formed by, for example, forming an embedded circuit whose upper surface is exposed from the surface of the insulating layer 3 and then forming an etching resist so that a part of the upper surface of the embedded circuit whose upper surface is exposed is insulated. It can be formed by etching so that it is recessed from the surface of the layer 3 and the other part remains as it is. The depth of the recessed shape 28 is desirably about 3 μm to 8 μm. The range of the recessed shape 28 is 50% to 100% of the dimension in the short direction (width direction) of the flip chip connection terminal 26, and the flip chip connection terminal 26. It is desirable that it is about 10% to 70% of the dimension in the longitudinal direction (length direction). By forming the concave shape 28 in this way, molten solder accumulates in this portion, so that the amount of solder (not shown) disposed on the flip chip connection terminal 26 can be increased. That is, the concave shape 28 serves as a container for storing solder, and since the solder accumulates in the concave shape 28, it is possible to form sufficient solder on the flip chip connection terminal 26 to form a solder fillet. .

  As a fifth example of the package substrate of the present invention, as shown in FIG. 5, there is one in which the tip of the flip chip connection terminal 26 is formed in the opening 31 of the solder resist 4. Note that the preliminary solder 19 is omitted. When a circuit pattern is formed by etching a metal foil adhered on the surface of the insulating layer 3 as in a conventional general package substrate, this circuit pattern is a convex circuit 32, and the flip formed Only the bottom surface of the chip connection terminal 26 is bonded to the insulating layer 3. Further, since the circuit pattern is formed by etching, the circuit pattern formed by the convex circuit 32 causes a so-called undercut in which the width on the bottom surface side is narrower than the surface side of the circuit pattern when viewed from the cross section. For this reason, when the size of the flip chip connection terminal 26 is miniaturized, the adhesion area between the bottom surface of the circuit pattern formed by the convex circuit 32 and the insulating layer 3 is reduced, so that the adhesive force with the insulating layer 3 is reduced, and the flip chip When connecting, a slight external force may be applied to cause peeling. Therefore, in order to secure the adhesion between the insulating layer 3 and the flip chip connection terminal 26, the circuit pattern is fixed from above by covering with the solder resist 4, and the flip chip connection terminal 26 is exposed from the opening 31 of the solder resist 4. Thus, a method of fixing both sides of the flip chip connection terminal 26 in the longitudinal direction with the solder resist 4 is adopted. However, in this method, since the width of the opening 31 of the solder resist 4 is defined by the resolution limit of the solder resist 4, it is necessary to make the flip chip connection terminal 26 longer than the resolution limit of the solder resist 4. It was. For this reason, the degree of freedom of circuit pattern routing is also limited. According to the fifth example of the package substrate 1 of the present invention, since the flip chip connection terminal 26 is formed by the embedded circuit whose upper surface is exposed on the surface of the insulating layer 3, the adhesion is ensured even if it is fine. It becomes possible. Therefore, it is not necessary to cover and fix the circuit pattern extended on both sides in the longitudinal direction of the flip chip connection terminal 26 with the solder resist 4 and fix the tip of the flip chip connection terminal 26 to the opening 31 of the solder resist 4. Can be formed inside. Therefore, since the flip chip connection terminal 26 can be miniaturized without being limited by the resolution of the solder resist 4, it is possible to achieve higher density and to improve the degree of freedom of circuit pattern design. .

  As a sixth example of the package substrate of the present invention, as shown in FIG. 6, a flip-chip connection terminal 26 provided with embedded circuits 2 extending on both sides or one side in the longitudinal direction can be mentioned. According to the sixth example of the package substrate of the present invention, similarly to the fifth example, the flip chip connection terminal 26 can be miniaturized without being limited by the resolution of the solder resist 4, so that higher density can be achieved. It is possible to increase the degree of freedom of circuit pattern design.

  As a seventh example of the package substrate of the present invention, as shown in FIG. 7, a part of the flip chip connection terminal 26 has a portion 33 extended in the short direction (width direction). The tip of the flip chip connection terminal 26 may be formed in the opening 31 of the solder resist 4. Note that the preliminary solder 19 is omitted. Since the flip chip connection terminal 26 has a portion 33 that is partially expanded in the short direction (width direction), the contact area with the insulating layer 3 is increased. Therefore, the flip chip connection terminal 26, the insulating layer 3, The amount of the preliminary solder 19 can be secured more, and the preliminary solder 19 in the portion 33 expanded in the short side direction (width direction) is affected by the surface tension. Since the solder pool is formed by pulling the solder of other parts, the solder pool can be stably formed at a predetermined position.

  As an example of the semiconductor package of the present invention, as shown in FIG. 8, a semiconductor element 15 is mounted on the package substrate 1 of the first to seventh examples by flip chip connection. The underfill material 23 is preferably filled between the bump 25 forming surface of the semiconductor element 15 and the insulating layer 3 having the flip chip connection terminal 26 of the package substrate 1 for mounting the semiconductor element. According to this, it becomes possible for the underfill material 23 to further strengthen the adhesion between the bump 25 forming surface of the semiconductor element 15 and the insulating layer 3 having the flip chip connection terminal 26. Therefore, it is possible to provide the semiconductor package 24 that can cope with high density and has excellent reliability.

  EXAMPLES Hereinafter, although an Example demonstrates this invention concretely, this invention is not limited to these Examples.

Example 1
Two prepreg GEA-679F (trade name, manufactured by Hitachi Chemical Co., Ltd.) having a nominal thickness of 0.06 mm, and a peelable copper foil FD in which an ultrathin copper foil thickness of 3 μm and a carrier copper foil thickness of 35 μm are bonded to both sides. -P3 / 35 (trade name, manufactured by Furukawa Circuit Foil Co., Ltd.) was constructed such that a 35 μm copper foil surface was bonded to the prepreg, temperature 175 ± 2 ° C., pressure 2.5 ± 0.2 MPa, holding time 60 A vacuum press was performed under the conditions of 1 minute to produce a copper clad laminate (MCL) having a surface of 3 μm copper foil, which was used as the first circuit board.

  A guide hole is formed on the first circuit board by a router processing machine manufactured by Hitachi Via Mechanics Co., Ltd., and the surface is etched by about 1 to 2 μm with a soft etching solution (containing hydrogen peroxide and sulfuric acid). A dry film resist NIT225 (trade name, manufactured by Nichigo Morton Co., Ltd.) was laminated at ± 10 ° C. and a pressure of 0.50 ± 0.02 MPa. After the circuit pattern was baked using a parallel exposure machine with the guide hole as a reference, the dry film resist was developed with a 1% by mass aqueous sodium carbonate solution, and the copper sulfate concentration was 60 to 80 g / L, and the sulfuric acid concentration was 150 to 200 g / Pattern copper electroplating with a thickness of 15 to 20 μm was applied on an L copper sulfate plating line, and the dry film resist was peeled off with an amine-based resist stripping solution to obtain a second circuit board.

  The copper pattern surface of the second circuit board is roughened using a copper surface roughening solution CZ-8100 (product name, manufactured by MEC Co., Ltd.), and an epoxy resin is applied to the glass cloth on both sides of the second circuit board. Through impregnated prepreg GEA-679F (trade name, manufactured by Hitachi Chemical Co., Ltd.) having a nominal thickness of 0.06 mm, 3 μm copper foil MT35S3 (trade name, manufactured by Mitsui Metal Mining Co., Ltd.) with 35 μm carrier copper foil After laminating with a vacuum press under conditions of pressure 2.5 ± 0.2 MPa, temperature 175 ± 2 ° C., holding time 60 minutes, a 35 μm carrier copper foil was peeled off to obtain a third circuit board.

  In the third circuit board, the inner layer guide pattern was recognized using an X-ray drilling machine, and drilling was performed at the center of the mark, and then unnecessary panel edges formed at the time of lamination were cut. The surface of the third circuit board was leveled, and a dry film resist NIT225 (trade name, manufactured by Nichigo Morton Co., Ltd.) was laminated at a temperature of 110 ± 10 ° C. and a pressure of 0.50 ± 0.02 MPa. Then, after pasting the negative mask, the circuit pattern is baked with a parallel exposure machine, the dry film resist is developed with a 1% by mass sodium carbonate aqueous solution to form an etching resist, and the copper without the etching resist is chlorinated. After removing with ferric aqueous solution, dry film resist is removed with sodium hydroxide aqueous solution and φ0.1mm conformal mask on the part to be non-through hole installation place to connect with the second circuit board And the position recognition pattern at the time of laser processing was formed, and it was set as the 4th circuit board.

  Conditions of beam irradiation diameter φ0.21 mm, frequency 500 Hz, pulse width 10 μs, number of irradiations 7 shots on both surfaces of the fourth circuit board by a carbon dioxide laser processing machine LC-1C / 21 (trade name, manufactured by Hitachi Via Mechanics Co., Ltd.) The holes were processed one by one, and non-through holes were formed on the second circuit board to form a fifth circuit board.

  The fifth circuit board is desmeared using an aqueous sodium permanganate solution having a temperature of 80 ± 5 ° C. and a concentration of 55 ± 10 g / L, and is plated with a thickness of 0.4 to 0.8 μm by electroless copper plating. Then, plating with a thickness of 15 to 20 μm was performed by electrolytic copper plating. As a result, the second circuit board (inner layer) and the fifth circuit board (outer layer) are electrically connected by the non-through hole. Next, the surface of the fifth circuit board was trimmed, and a dry film resist NIT225 (trade name, manufactured by Nichigo Morton Co., Ltd.) was laminated at a temperature of 110 ± 10 ° C. and a pressure of 0.50 ± 0.02 MPa. . Then, after pasting the negative mask, the circuit pattern is baked with a parallel exposure machine, the dry film resist is developed with a 1% by mass sodium carbonate aqueous solution to form an etching resist, and the copper without the etching resist is chlorinated. After removing with a ferric aqueous solution, the dry film resist was removed with a sodium hydroxide aqueous solution to form a circuit pattern to obtain a sixth circuit board. Here, the circuit pattern of the sixth circuit board is formed in a convex shape from the surface of the sixth circuit board.

  In the sixth circuit board, in the peelable copper foil FD-P3 / 35 (product name, manufactured by Furukawa Circuit Foil Co., Ltd.) in the first circuit board, physical force is applied to the boundary between the 3 μm copper foil and the 35 μm carrier copper foil. And peeled to obtain two seventh circuit boards. Here, in the seventh circuit board, the 3 μm copper foil which is the contact surface with the 35 μm carrier copper foil is arranged on one surface, and the convex circuit of the sixth circuit board is arranged on the other surface. A pattern (convex circuit) is arranged.

  35 μm carrier arranged on one surface of the seventh circuit board after covering the convex circuit pattern (convex circuit) of the sixth circuit board arranged on the other surface with an etching resist The 3 μm copper foil that was in contact with the copper foil is removed with a soft etching solution (containing hydrogen peroxide and sulfuric acid). Thereby, an embedded circuit is formed on one surface. Further, when the etching resist covering the other surface is removed, the convex circuit pattern (convex circuit) of the sixth circuit board is arranged on the other surface. Then, nickel-gold plating finish was performed as solder resist formation and protective plating to obtain an eighth circuit board. Here, in the eighth circuit board, an opening is provided in the solder resist on one surface (one surface of the seventh circuit board), and the line / space is 20 μm / 20 μm (40 μm pitch) in this opening. Embedded circuit serving as a flip-chip connection terminal. The dimension in the longitudinal direction of the flip chip connection terminal (the length of the flip chip connection terminal) defined by the opening of the solder resist is about 100 μm.

  Preliminary solder was formed by printing and reflowing a solder paste on the embedded circuit serving as the flip-chip connection terminal with respect to the eighth circuit board to obtain a ninth circuit board. For the solder paste for the preliminary solder, Sn-Ag-Cu-based eco solder M705 (trade name, manufactured by Senju Metal Industry Co., Ltd., Eco solder is a registered trademark) is used, and an infrared reflow apparatus is used for reflow. , Under the conditions of a peak temperature of 260 ° C.

  A tenth circuit board was obtained by cutting the package size into a ninth circuit board. As shown in FIG. 1, the tenth circuit board includes an insulating layer 3, an embedded circuit 2 provided so that the upper surface is exposed on the surface of the insulating layer 3, and the insulating circuit 3 and the embedded circuit. 2 and the embedded circuit 2 in the opening 31 provided in the solder resist 4 forms a package substrate for mounting a semiconductor element on which the flip chip connection terminal 26 is formed. . Further, the thickness of the preliminary solder 19 covering the flip chip connection terminal 26 is 3 to 5 μm. Here, the thickness of the solder is a solder jist and a flip chip before and after forming the preliminary solder 19 using Hi-Somet (trade name, made by Union Optical Co., Ltd., registered trademark), which is a non-contact level difference measuring machine. It measured by measuring the level | step difference with the connection terminal 26. FIG.

  The tenth circuit board is a package substrate for mounting a semiconductor element having a two-layer structure. After the sixth circuit board is formed, a second insulating resin laminate is formed on the copper pattern of the sixth circuit board. After repeating the process of forming copper plating and wiring by providing non-through holes and completing circuit formation of the desired number of layers, peeling of carrier copper foil, removal of ultra thin copper foil and cutting to package size By performing the applying process, a package substrate for mounting a semiconductor element having a three-layer structure, a four-layer structure,..., An n-layer structure can be formed.

  As shown in FIG. 8, after producing the 10th circuit board (package substrate 1), the semiconductor element 15 was mounted by flip chip connection. In the flip chip connection, the flip chip connection terminal 26 on the tenth circuit board and the bump 25 of the semiconductor element 15 (Sn-3.0% Ag-0.5% Cu solder formed on the copper pillar, 40 μm). After positioning so that the pitch and the height are 25 μm), flip chip connection was performed using an ultrasonic flip chip bonder SH-50MP (product name, manufactured by Altex Co., Ltd.). The crimping conditions for flip chip connection were held for 4 seconds while raising the temperature to 230 ° C. and applying 50 g per bump while using ultrasonic waves. Thereafter, an underfill agent 23 is filled between the surface of the semiconductor element 15 where the bumps 25 are formed and the insulating layer 3 having the flip chip connection terminals 26 of the tenth circuit board (package substrate 1). Obtained.

(Example 2)
The thickness of the preliminary solder covering the flip chip connection terminal is 7 to 10 μm. A tenth circuit board and a semiconductor package were obtained in the same manner as in Example 1 except for the above.

(Example 3)
The thickness of the preliminary solder covering the flip chip connection terminal is 17 to 20 μm. A tenth circuit board and a semiconductor package were obtained in the same manner as in Example 1 except for the above.

(Comparative Example 1)
The thickness of the preliminary solder covering the flip chip connection terminal is 1 to 2 μm. A tenth circuit board and a semiconductor package were obtained in the same manner as in Example 1 except for the above.

(Reference Example 1)
The thickness of the preliminary solder covering the flip chip connection terminal is 25 to 28 μm. A tenth circuit board and a semiconductor package were obtained in the same manner as in Example 1 except for the above.

Example 4
In the same manner as in Example 1, an eighth circuit board was formed. Here, as shown in FIG. 2, an opening 31 is provided in the solder resist 4, and the embedded circuit 2 to be the flip chip connection terminal 26 is disposed in the opening 31. A via 18 is connected to the bottom surface of the embedded circuit 2 including the flip chip connection terminal 26. Thereafter, the ninth circuit board, the tenth circuit board (package board), and the semiconductor package were formed in the same manner as in Example 1.

(Example 5)
In the same manner as in Example 1, a seventh circuit board was formed. In this seventh circuit board, before removing the 3 μm copper foil that was in contact with the 35 μm carrier copper foil with a soft etching solution (containing hydrogen peroxide and sulfuric acid), contact with the 35 μm carrier copper foil. A convex shape was formed by forming a plating resist on the surface of the 3 μm copper foil, which was the surface, and pattern copper electroplating a part of the portion to be the flip chip connection terminal of the embedded circuit. Thereafter, the 3 μm copper foil that was in contact with the 35 μm carrier copper foil was removed with a soft etching solution (containing hydrogen peroxide and sulfuric acid), followed by solder resist formation and nickel-gold plating finishing as protective plating. And an eighth circuit board was formed. Here, as shown in FIG. 3, an opening 31 is provided in the solder resist 4, and the embedded circuit 2 serving as the flip chip connection terminal 26 is disposed in the opening 31. Further, a convex shape 27 is formed on a part of the flip connection terminal 26 in the longitudinal direction, and the height of the convex shape 27 is about 5 μm. The range of the convex shape 27 is 100% of the dimension in the short direction of the flip chip connection terminal 26 and about 30% of the dimension in the longitudinal direction of the flip chip connection terminal 26. Thereafter, the ninth circuit board, the tenth circuit board (package board), and the semiconductor package were formed in the same manner as in Example 1.

(Example 6)
In the same manner as in Example 1, a seventh circuit board was formed. In the seventh circuit board, the 3 μm copper foil that was in contact with the 35 μm carrier copper foil was removed with a soft etching solution (containing hydrogen peroxide and sulfuric acid), and the upper surface was exposed from the surface of the insulating layer. After the embedded circuit was formed, an etching resist was formed, and etching was performed so that a part of the upper surface of the embedded circuit with the upper surface exposed was recessed from the surface of the insulating layer and the other part remained as it was. Thereafter, solder resist formation and nickel-gold plating finishing as protective plating were performed to obtain an eighth circuit board. Here, as shown in FIG. 4, an opening 31 is provided in the solder resist 4, and the embedded circuit 2 serving as the flip chip connection terminal 26 is disposed in the opening 31. Further, a concave shape 28 is formed in a part of the flip connection terminal 26 in the longitudinal direction, and the depth of the concave shape 28 is about 5 μm. The range of the recessed shape 28 is 100% of the dimension in the short direction of the flip chip connection terminal 26 and about 30% of the dimension in the longitudinal direction of the flip chip connection terminal 26. Thereafter, the ninth circuit board, the tenth circuit board (package board), and the semiconductor package were formed in the same manner as in Example 1.

(Example 7)
In the same manner as in Example 1, an eighth circuit board was formed. Here, as shown in FIG. 5, an opening 31 is provided in the solder resist 4, and the embedded circuit 2 to be the flip chip connection terminal 26 is disposed in the opening 31. The tip of the flip chip connection terminal 26 is formed in the opening 31 of the solder resist 4. Thereafter, the ninth circuit board, the tenth circuit board (package board), and the semiconductor package were formed in the same manner as in Example 1.

(Example 8)
In the same manner as in Example 1, an eighth circuit board was formed. Here, as shown in FIG. 6, an opening 31 is provided in the solder resist 4, and the embedded circuit 2 to be the flip chip connection terminal 26 is disposed in the opening 31. In addition, the embedded circuit 2 is provided that extends to both sides or one side of the flip chip connection terminal 26 in the longitudinal direction. Thereafter, the ninth circuit board, the tenth circuit board (package board), and the semiconductor package were formed in the same manner as in Example 1.

Example 9
In the same manner as in Example 1, an eighth circuit board was formed. Here, as shown in FIG. 7, an opening 31 is provided in the solder resist 4, and the embedded circuit 2 serving as the flip chip connection terminal 26 is disposed in the opening 31. Further, a part of the flip chip connection terminal 26 in the longitudinal direction forms a portion 33 extended in the short direction (width direction). That is, the flip chip connection terminal 26 forms a portion 33 that is partially expanded in the lateral direction (width direction). Thereafter, the ninth circuit board, the tenth circuit board (package board), and the semiconductor package were formed in the same manner as in Example 1.

(Comparative Example 2)
In the same manner as in Example 1, a seventh circuit board was obtained. Here, the seventh circuit board is provided with a 3 μm copper foil that is a contact surface with the 35 μm carrier copper foil on one surface, and the other surface is formed by a convex circuit of the sixth circuit board. A circuit pattern is arranged.

  In this seventh circuit board, after covering the circuit pattern by the convex circuit of the sixth circuit board disposed on the other surface with an etching resist, the 35 μm carrier copper foil disposed on one surface and The 3 μm copper foil that was the contact surface was removed with a soft etching solution (containing hydrogen peroxide and sulfuric acid). Thereby, an embedded circuit is formed on one surface. When the etching resist covering the other surface is removed, a circuit pattern formed by the convex circuit of the sixth circuit board is arranged on the other surface. Thereafter, solder resist formation and nickel-gold plating finishing as protective plating were performed to obtain an eleventh circuit board. Here, in the eleventh circuit board, an opening is provided in the solder resist on the other surface (the other surface of the seventh circuit board), and the line / space is 20 μm / 20 μm (40 μm pitch) in this opening. The circuit pattern by the convex circuit which becomes the flip-chip connection terminal is arranged.

  Preliminary solder was formed by printing and reflowing a solder paste on a circuit pattern of a convex circuit serving as a flip-chip connection terminal with respect to the eleventh circuit board to obtain a twelfth circuit board. For the solder paste for the preliminary solder, Sn-Ag-Cu-based eco solder M705 (trade name, manufactured by Senju Metal Industry Co., Ltd., Eco solder is a registered trademark) is used, and an infrared reflow apparatus is used for reflow. , Under the conditions of a peak temperature of 260 ° C.

  The thirteenth circuit board was obtained by cutting the twelfth circuit board into a package size. As shown in FIG. 9, the thirteenth circuit board includes an insulating layer 3, a circuit pattern formed by a convex circuit 32 provided on the surface of the insulating layer 3, and a circuit formed on the insulating layer 3 and the convex circuit 32. A solder resist 4 provided on the pattern, and a circuit pattern formed by the convex circuit 32 in the opening 31 provided in the solder resist 4 forms a package substrate on which the flip chip connection terminal 26 is formed. Further, the thickness of the preliminary solder 19 covering the flip chip connection terminal 26 is 3 to 5 μm. Thereafter, a semiconductor package was obtained in the same manner as in Example 1.

(Comparative Example 3)
The thickness of the preliminary solder covering the flip chip connection terminal is 17 to 20 μm. Except for this, a thirteenth circuit board and semiconductor package were obtained in the same manner as in Comparative Example 3.

  Table 1 shows the results of examining the cross-sectional shape of the flip chip connection terminal, the solder thickness, and the presence or absence of a solder bridge for the package substrates of Examples 1 to 9, Reference Example 1, and Comparative Examples 1 to 3. Moreover, the result of having investigated the state of the solder fillet about the semiconductor package of Examples 1-9, Reference example 1, and Comparative Examples 1-3 is shown.

  From the observation result of the cross-sectional shape of the flip chip connection terminal, in Examples 1 to 9, the side surface and the bottom surface of the flip chip connection terminal are embedded and closely adhered to the insulating layer, the cross-sectional shape is almost rectangular, and the undercut is recognized. There wasn't. On the other hand, in Comparative Examples 2 and 3, since it is a convex circuit, only the bottom surface of the Philip chip connection terminal was in close contact with the insulating layer. Further, undercuts were observed in the cross-sectional shape of the flip chip connection terminal, and the width at the narrowest portion was less than half the top width (width on the front surface side).

  From the measurement results of the solder thickness, in Examples 1 to 9, the solder thickness was 3 to 20 μm, and from the confirmation result of the solder bridge, no solder bridge was generated within this solder thickness range. On the other hand, in Comparative Example 1, the solder thickness was as thin as 1 to 2 μm, and no solder bridge was generated. In Reference Example 1, the solder thickness was as thick as 25 to 28 μm, and a solder bridge was generated between adjacent flip chip connection terminals. In Comparative Example 3, the solder thickness was 17 to 20 μm, but because it was a convex circuit, the solder wraps around the side surface of the flip chip connection terminal, and a solder bridge was generated.

  From the results of confirming the solder fillet of the semiconductor package, in Examples 1 to 9, Reference Example 1 and Comparative Example 3, the solder fillet formed between the bumps of the semiconductor element is the bump of the semiconductor element and the flip chip of the package substrate. The solder was wet and spread on both of the connection terminals, and the state was good. On the other hand, in Comparative Examples 1 and 2, there were portions where the solder wettability was insufficient in some of the bumps of the semiconductor element or the flip chip connection terminals of the package substrate, and the formation of solder fillets was insufficient.

  The cross-sectional shape of the flip chip connection terminal was obtained by preparing a microsection and observing the cross section with a metal microscope. The thickness of the solder on the flip-chip connection terminal is determined by flipping the solder jist and the solder jist before and after forming the preliminary solder using Hi-Somet (trade name, made by Union Optical Co., Ltd., registered trademark). It measured by measuring the level | step difference with a chip connection terminal. The presence or absence of the solder bridge and the state of the solder fillet were confirmed by observing at a magnification of 10 using a stereomicroscope.

1: Semiconductor device mounting package substrate or package substrate or tenth circuit substrate 2: Embedded circuit 3: Insulating layer 4: Solder resist 8: Protection plating 15: Semiconductor device 18: Via 19: Pre-solder 23: Underfill material 24: Semiconductor package 25: Bump 26: Flip chip connection terminal 27: Convex shape 28: Concave shape 31: Opening (of solder resist) 32: Convex circuit 33: Part extended in short direction

Claims (7)

An insulating layer, an embedded circuit provided so that a top surface is exposed on a surface of the insulating layer and a side surface and a bottom surface are embedded in and in close contact with the insulating layer; and provided on the insulating layer and the embedded circuit. and a photosensitive solder resist, the embedded circuit disposed in an opening opening width is larger than the limit of resolution of the solder resist to form a flip-chip connection terminal, this flip-chip connection terminal Covered with a pre-solder having a thickness of 3 μm to 20 μm,
The flip chip connection terminals have a longitudinal direction and a short direction in plan view, and are arranged side by side in the opening of the solder resist,
The dimension of the flip chip connecting terminal in the short direction is 20 μm or less;
One longitudinal direction of the flip chip connection terminal is defined by the opening of the solder resist, the longitudinal direction of the other tip of the flip chip connection terminal is arranged in the opening of the solder resist opening of the solder resist A package substrate for mounting a semiconductor element, wherein a dimension in the longitudinal direction of the flip-chip connection terminal , one of which is defined by the longitudinal direction, is less than a resolution limit of the solder resist or 100 μm or less.   2. The package substrate for mounting a semiconductor element according to claim 1, wherein vias are connected to the bottom surface of the embedded circuit forming the flip chip connection terminals.   3. The package substrate for mounting a semiconductor element according to claim 1, wherein a convex shape is formed on a part of the flip chip connection terminal in the longitudinal direction.   4. The package substrate for mounting a semiconductor element according to claim 1, wherein a concave shape is formed in a part in a longitudinal direction of the flip chip connection terminal.   5. The package substrate for mounting a semiconductor element according to claim 1, wherein an embedded circuit having a portion extended to both sides or one side in the longitudinal direction of the flip chip connection terminal is provided.   6. The package substrate for mounting a semiconductor element according to claim 1, wherein a part of the flip chip connection terminal is extended in a short direction.   7. A semiconductor package in which bumps of a semiconductor element are mounted on a flip chip connection terminal of the package substrate for mounting a semiconductor element according to claim 1 by flip chip connection.

Images