TW201222727A - Method of forming integrated circuit structure and integrated circuit structure - Google Patents

Method of forming integrated circuit structure and integrated circuit structure Download PDF

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Publication number
TW201222727A
TW201222727A TW100108779A TW100108779A TW201222727A TW 201222727 A TW201222727 A TW 201222727A TW 100108779 A TW100108779 A TW 100108779A TW 100108779 A TW100108779 A TW 100108779A TW 201222727 A TW201222727 A TW 201222727A
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Taiwan
Prior art keywords
strip
gate
layer
conductive
dielectric layer
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TW100108779A
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English (en)
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TWI463603B (zh
Inventor
Chien-Chih Ho
Chih-Ping Chao
Hua-Chou Tseng
Chun-Hong Chen
Chia-Yi Su
Kalnitsky Alexander
Jye-Yen Cheng
Harry Haklay Chuang
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Taiwan Semiconductor Mfg
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Publication of TW201222727A publication Critical patent/TW201222727A/zh
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Publication of TWI463603B publication Critical patent/TWI463603B/zh

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    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
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    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
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    • H01L29/0642—Isolation within the component, i.e. internal isolation
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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

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201222727 六、發明說明： 【發明所屬之技術領域】 本揭露一般是有關於半導體裝置之領域，且特別是有 關於金屬閘極電晶體、積體電路、系統、和其製造方法。 【先前技術】 半導體積體電路（1C)工業已歷經快速成長。1C材料 與設計方面的技術進步已產生了多個1C世代，其中每一 世代具有相較於前一世代更小且更複雜的電路。然而， 此些進步已增加了處理與製造1C的複雜度，且為了實現 上述之進步’在1C處理與製造方面亦需有類似的發展。 牡H知展的進程（Course)中’當幾何尺寸[亦即使用 製造私序所能產生的最小元件（或線）]已經縮小時，功能 密度（亦即每一晶片面積中内連裝置的數量）大致上已經 增加。此微縮化製程—般藉由增加生產效率和降低相關 的成本來提供利益。此微縮化亦提供相對高的功率消耗 :罢其可藉由使用如互補式金屬氧化物半 裝置之低功率消耗裝置來解決。 ） 在此微縮化趨勢巾，p #田々你 互補式金屬氧化物半導體/置之各料來做為 質。互補4入厘& 閘極電極和閘極介電 物和多晶;物:有閉極氧化 電常數（k)開極介電 、'寸持續遞減，以南介 物和多晶⑪閘極電極，極電極來取代閘極氧化 隨著技術持續地^ m能已成為一種需求。 在、.個小，例如，對於28奈米（nm) 201222727 技術節點和更小之節 能造成高閘極電阻之問題。===電極可 ϊ =金屬氧化物半導體裝置之電性性能= 氧化物半導财頻下運轉之射頻互補式金屬 訊、和穩2置（队_)之最大振錢率（“>〇、雜 【發明内容】 之方Π之由;目二=提供一種形成積體電 帶，來降低整體^厚度且平行閘極帶之傳導 包含實施例’―種形成積體電路結構之方法 介fit 寬度之閘極帶位於基材上之第一内層 乂：：第二：成人具有第二寬度之傳導帶於間極帶之 y第一内層介電層於第一内層介電 =及形成傳導插塞於第二内層介電層之中:二 ^據本發明另—實施例，—種形成積體電路結構之方 材：：：成具有第一寬度之間極帶，其中閘極帶位於基 内層介電層之中。形成圖案化層於閘極帶之 傳導C匕層具有溝渠開口位於間極帶之上。形成 成第開口之中’其中傳導帶具有第二寬度。形 介電層於傳導帶之上。以及形成傳導插塞於 第一内層7丨電層之中、且於傳導帶之上。 依據本發明又一實施例，—種積體電路結構包含第一 201222727 層位於基材之上，間極帶位於第—内 之中’其令開極帶具有第—宽度。第二内 閘極帶和第一内層介電層 θ ; 接觸插塞位於第二内層 ’ μ料帶介於接職塞和_帶之間， 八中傳導τ具有第二寬度。 明特別有利於藉由後閘極方法形成之射頻互補 ，金屬氧化物半導體裝置，本發明之優點為可改善互補 式金屬氧化物半導體裝置之電性性能。 【實施方式】 可了解的是以下的揭露提供了許多不同的實施例或 」子’以執行本發明之不同特徵。以下所描述之構件與 :排的特定例子係用以簡化本揭露。當然這些僅為例 ，2非為限制。此外，在描述中，第一特徵之形成於 徵之上或上可能包含第—與第二特徵以直接接觸 笛一^形成的實施例’1亦可包含額外特徵可能形成在 與第—特徵之間而使第—與第二特徵並未直接接觸 、—施例除此之外，本揭露在不同例子中可重覆參考 子及/或文字。此重覆係為了簡化和清晰之目的，並益 指定不同實施湘之_及/或討論之配置。 ’ 關於第2圖至第7Λ圖，依照第1圖之方法100在 ，種製造階段之—種半導體裝i 2GG之-實施例的各種 剖面示意圖和透視圖係在以下共同描述。此半導體裝置 200 /會示。—積體電路、或其部分，其可包含記憶體單元 及/或邏輯單凡。此半導體裝置2〇〇可包含被動元件如電 201222727 阻、電容、電感器及/或保險絲；和主動元件如 效電日日體(PFETs)、N通道場效電晶體（NFETs)、 體f效應電晶體(M〇SFETS)、互補式金屬氧化 物+導體、射頻互補式金屬氧化物半導體（rfcm 言 ，壓電晶體；其他合適的元件；及/或其組合。可理解： 是，此方法之額外實施例可於方法1〇〇之前、期間、及/ 或之後’提供額外的步驟，且可取代或移除—些描述於 下之步驟。進一步了解的是，半導體裝置之額外實 施例可增加額外的特徵於半導體裝置200中，且可取代 或移除一些描述於下之特徵（> 睛參照第1圖和第2圖，方法100以步驟1〇2開始， 其中提供-基材700。在本實施例中，基材·係一含 石夕之半導體基材。替代地，基材7〇〇包含含石夕及/或錯之 兀素半導體；包含碳化矽、砷化鎵、磷化鎵、磷化銦、 神化銦、及/或録化鋼之複合半導體；包含錯化邦㈣、 磷化鎵砷（GaAsP) '砷化鋁銦（A1InAs)、砷化鋁鎵 (AlGaAs)、砷化鎵銦（GainAs)、磷化鎵銦（Gainp)、及/ 或磷石申化鎵銦（GaInAsP)之合金半導體；或其組合物。此 合金半導體基材可具有梯度分布的錯切（SiGe)特徵， 其中此梯度分布的鍺切特徵之々和鍺組合從—地區之 比例更改至另一地區之另—比例。此合金錄化石夕可形 成於矽基材之上。此鍺化矽基材可為受應變。此外，此 半導體基材可為絕緣體上半導體（s〇I)。在一些例子中， 此半導體基材可包含摻雜的“。在其他料中，此碎 基材可包含多層複合半導體結構。 201222727 基材700可根據設計要求（例如p型井或n 含各種摻雜區。此摻雜區可^ ^ ^ ^ ^ ^ ^ ^ 型摻質;如型摻 雜區可直接形成於基材7()()中、在P井結構中、在1井 ==一D結構中、或使用凸起結構。： =裝置200可包含N通道場效電晶體及/或p通道場效 ，晶體裝置m此基材7()()可包含配置給每—n通道 场效電晶體裝置及/或丨> 通道場效電晶體裝置中之特 置之各種摻雜區。 ^ 凊再次參照第1圖，通稱為ILDG之内層介電声 (ILD)116可„又置在基材7()()之上。此内層介電層116可 包含介電材料，如氧化物、氮化物、氮氧化物、低让介 電材料、超低k介電材料、極低k介電材料、另一介電 質材料、或其組合。此内層介電層Π6可藉由，例如， 化學氣相沉積（CVD)製程、高密度電漿化學氣相沉積 (HDPCVD)製程、高深寬比製程（HARp)、旋轉塗佈製程、 其他/儿積製知、及/或其任何組合。在其他實施例中，額 外的介電層（未繪示）可形成於内層介電層116之下或之 上。 ^在實施例中，第—閘極帶200a和第二閘極帶2〇〇b 形成於内層介電層116中和基材7〇〇之上。第一閘極帶 2〇〇a可依序包含閘極介電質丨20和閘極電極122。第- 閘極帶200b可依序包含閘極介電質140和閘極電極 142。此第一和第二閘極帶200a和200b可分別具有藉由 沉積形成之寬度W】a和W丨b。 201222727 在實施例中，開極介電質120和 人 如氧切、氮氧化砂、氮化碎、高k介電材y電材—料二 =二％或其組—示的高k介電材= (mao)、乳化铪鈦（HfTi (Hfzr0)、其他合適的材料、或其組合物。門極人:： 120和140可為多層結構，例如，包含内=电質 面層上之“介電材料層。例示内界面；= 由熱處理或原子層沉積製程形成之成長氧化:Γ 14〇=電極122和142分別形成於問極介電質120和 之上，母一閘極電極丨22和14〇可包含呈 傳導層。因此，陶極122* 142:可稱；功 ==函數層包含任何適當的材料，如此-來可 :t 數層以具有適當的功函數來加強相關裝置之性 X例如通道場效晶體裝置之p型功函數 ’屬（P_meta1)’可使用氣化鈦（TiN)錢化！旦（TaN)。另一 f面’若需要N通道場效電品«置之η型功函數金屬 :=al) ’可使用组(Ta)、銘化紐（ιίλι)、氮化鈦铭⑺篇） =風化组（raCN)。此功函數層可包含摻雜的傳導氧化 在實施例中，閘極間隙壁126和M6形成於内層介 電層116巾’且藉由適當的製程分別锻於第一閘極帶 200a和第二閘極帶2()0b之相對側壁上。此閘極間隙壁 126和146可包含介電材料，如氧化物、氮化物、說氧 化物、另一介電材料、或其組合物。在另一實施例中， 201222727 = 適當的製程形成於閘極帶200a與間 間。此襯極帶2〇〇b與間極間隙壁146之 的介電材料。“Μ於雜㈣壁126和146之適合 开；2 f ^例中’他性傳輸結構124和電性傳輸結構144 I θ介電? 116之中，且分別位於閘極電極122 J…之上。此每—電性傳輸結構124和144可包含傳 人：：：鋁：銅、鎢、金屬合金、金屬矽化物、其他 。“、才料、或其組合物。此電性傳輸結構124和144 可藉由積和化學機械研磨製程（CMp)來形成。 ，、在一些實施例中，共用源極或共用汲極區111(以下 稱為源極/汲極區川）可能位於基材谓中，且介於第一 和第二閘極帶200a和2〇0b之間。源極/没極區113和ιΐ5 可分別形成於鄰近第-和第二間極帶2〇〇a和2嶋。第 一閘極帶200a與源極/汲極區U1和113形成第一金屬 氧化物半導各裝置，且第二閘極帶和源極/汲極區 111與115形成第二金屬氧化物半導體裝置。 、請參照第1圖和第3圖，方法100以步驟1〇4持續 進行’其中傳等層130形成於内層介電| 116、第一和 第二閘極帶200a和200b、及電性傳輸結構124和144 之上。傳導層130可為金屬層，如鋁、銅、鎢；金屬合 ，層’、如氮化鈦、鎢化鈦（丨I \v)、氮化鉅；其他合適的材 料；或其組合物。在一些實施例中，傳導層13〇具有介 於約100埃至約10,0()()埃之厚度。 請參照第1圖和笫4圖，方法丨〇〇以步驟丨〇6持續 10 201222727 進行，其中藉由圖案化製程圖案化傳導層130,來形成 專導帶132和134。傳導帶丨32形成於第一閘極帶2〇〇a 和電性傳輸結構124之上°傳導帶134形成於第二閘極 帶200b和電性傳輸結構M4之上。例如，此圖案化製程 包含藉由旋轉塗佈之適當製程形成光阻層（未繪示）於；傳 導，13 0之上，且接著曝光與顯影此光阻層來形成光阻 特徵。然後，藉由乾似彳製程將光阻特徵之圖案傳遞至 下層的傳導層13()來形成傳Φ帶132和134。在-些實 施例導帶132矛口 134可分別具有寬度，和·。 在貫轭例中，莧汶W3a和W3b分別大於寬度wia和 wib。在其他實施例中，寬度W3a對寬度wia之比例及 /或W3b對寬度Wlb之比職圍介於約】和約6之間。 替代地，當傳導層丨30使用和電性傳輸結構124與 144相同之材料時，^將用以形成傳導層之步驟1〇4 省略。例如’相關的製程流程可包含沉積鋁層於内層介 電層116之中和之上、及於第—和第二閘極帶雇和 200b之上，移除紹層位於内禮介電層丨16之部分，來形 成平坦化的表面；以及圖案化此平坦化⑽層，來形成 電性傳輸結構124和144和傅導帶132和134。繪示於 第4圖之結構之透视圆絲示於笫4A圖之中。 /明參照第1圖和笫5圖，方法_以步驟1〇8持續 進行’其中通稱為❹丨之额外的内層介電層15〇形成 於傳導帶132和134與内層介電眉，u6之上。此額外的 内層介電層15〇可&今介/( 一 匕;丨 '匕材枓，如羊L化物、化物、 氮氧化物低k介屯材料、越低丨〈介電材料、極低让介 201222727 電材料、另—介電材料、或其組合物。此額外的内層介 電層150可藉由化學氣相沉積製程、高密度電漿化學氣 1沉積製程、高深寬比製程、旋轉塗佈製程、另一=積 製程、及/或任何其他組合。在實施例中，額外的内層介 電150層可包含和使用於内層介電層116相同之材^。 請參照第1圖和第6圖，方法100以步驟11〇和ιΐ2 1續進行，其中接觸開口（未緣示）藉由-般使用祕刻 製程形成，額外的内層介電層150及/或内層介電層116 之中。在實施例中，至少三個接觸開口形成於傳導帶132 和134與共用源極/汲極區U1之上。接著，填充傳導層 (未繪示+)於接觸開口之中及額外的内層介電層15〇^ 上。接著，可提供化學機械研磨製程來完全的移除傳導 額外的㈣介電層15()之上之部分，而形成接觸 ^ 〇於額外的内層介電層150及/或内層介電層116 、—》月參照第1圖與第7圖’方法】〇〇以步驟⑴持續 、/亍/、中通稱為Ml之金屬線170形成於接觸插塞16〇 ’’、曰示於第7圖之結構之透視圖係綠示於第7 a圖。 關於第9圖至第14圖’根據第8圖之方法在不 半導體裝置4〇0之一實施例之各種剖面示 :圖係共同地在以下描述。半導體裝置_繪示積體電 導t其可包含記憶體單元及/或邏輯電路。半 ^置400可包含被動元件，如電阻、電容、電感器、 、f ;和主動元件’如P通道場效電晶體、N通 U效電晶體、金屬氧化物半導體場效電晶體、互補式 12 201222727 體電式金屬氧化物半導 前、法之額外實施例可於方法之 :-些描述於下之步驟。進一步瞭解的是，：=】 4〇〇之額外音始办丨7以丨 亍等篮装罝 之中，了：： 增加額外的特徵於半導體裝置400 π取代或移除一些描述於下之特徵。 進行圖和第9圖’方法細以步驟搬開始 且 ^ y、導體裝置400之結構，半導體裝置400 :有和—第丨圖相同之項目以相同參考數字加上1〇〇來表 二在貫施例中，設置内層介電層216於基材刪之上。 在實施例中’設置包含位於閘極介電質22〇上之閘極電 和2之第閘極▼ 300a、以及包含位於閘極介電質24〇 上之閘極電極242之第二閘極帶3〇〇b於内層介電層 之:。每一第一閘極帶3〇〇a和第二閘極帶3〇%分別具 有寬度W2a和W2b。在實施例中，共用源極/汲極區2n 位於基材800中，且介於第一閘極帶％〇a和第二閘極帶 300b之間。源極/汲極區213和215可分別鄰近於第一閘 極帶300a和第二閘極帶3〇〇b。在實施例中，設置閘極 間隙壁226和246於内層介電層216之中，且分別置於 第一閘極帶300a和第二閘極帶3〇〇b之相對側壁上。在 貫施例中，设置電性傳輸結構224和244於内層介電層 116之中’且分別設於閘極電極222和242之上。 請參照第8圖和第1〇圖，方法3〇〇以步驟3〇4持續 進行’其中圖案化層21 8形成於内層介電層216之上。 13 201222727 中，圖幸仆I ’圖案化層218係介電層。在另-實施例 用相同鉍钮㈢218包含—材料，其與内層介電層216使 218a=t°在t施例中，圖案化層218具有溝渠開口 閘極页3〇〇a之上、和溝渠開口 218b於第二 ;4aT ::之上。溝渠開口 218a和2186分別具有寬度 約1〇〇口诠在實施例中’此圖案化層218具有範圍從 約100埃至約10,000埃之間之厚度。 月’ ’、，、第8圖至第丨丨圖，方法3〇〇以步驟雇持續 進订，其中傳導層230形成於溝渠開口 218a和218b之 中’且位於圖案化層218之上。傳導層23〇可為金屬層， ，鋁、銅、鎢；金屬合金層，如氮化鈦、鎢化鈦、氮化 鈕，其他合適的材料；或其組合物。 、—請參照第8圖和第12圖，方法300以步驟3〇8持續 進仃，其中移除傳導層位於圖案化層218之上之部分， 以形成傳導帶232和234。此傳導帶234位於電性傳輸 二構244之上，且第一閘極帶3〇〇a具有寬度W4a。傳導 帶234位於電性傳輸結構244之上’且第二閘極帶3〇〇b 具有寬度W4b。在實施射，此移除製程包含化學機械 研磨製程’因此’傳導帶232和234具有實f 化層218共平面之平坦化的表面。 >、 請參照第8圖和第13圖，方法3〇〇以步驟31〇至 314持續進行，其中額外的内層介電層25〇形成於傳導 帶232和234、與圖案化層218之上。額外的内層介電 層250可包含介電材料，如氧化物、氮化物、氮氧化物、 低k介電材料、超低k介電材料、極低k介電材料、其 14 201222727 他介電材料、或其組合物。在實施射，額外的内層介 包ΐ —材料，其與内層介電層216使用相同 。接者，猎由蝕刻製程形成接觸開口 外的内層介電層25〇、圖案化層218、及/或内層介)二 彳！'施例中，至少三個接觸開口形成於接觸 咿和34與共用源極/汲極區211之上。之後，填 ;專導層(未繪：)於接觸開口之中與額外的内層介電層 德道2上才妾著’可提供化學機械研磨製程來完整移除 傳導層於額外的内層介電層250之上之部分’而护成接 觸:二6〇於額外的内層介電層25〇、圖案化層⑽及 /或内層介電層216之中。 請：：第8圖和第14圖，方法3〇〇以步㈣持續 進:丁 ’八中金屬線270形成於接觸插塞26〇之上。終示 於第14圖之結構之透視圖係與綠示於第圖之相^。 本發明之實_具#許乡優勢鏡。藉由 ί夠=且Γί閘極帶之傳導帶’可降低整體的問極電 月:。此特別有利於藉由後閘極方法形成之射 二 屬氧化物半導體裳置’原因在於當這些 = 定性的降低。 敢大振羞頻率、雜訊和穩 雖然己詳述本㈣與其優點，應轉的是 Γ::Γ請專利範圍所定義之實施例的精神:範： ’仏各種之更動、替代與潤飾。再者，㈣ 並不受限於說明書所述之製程、機m造、組成= 201222727 k、方法和步驟的特定實施例。在此技術領域中具有通 常知識者可自本揭露了解到：現存或日後所發展之進^ 與在此所描述之實施例實質相同之功能或達到相同結= 的製私、機台、製造、組成、手段、方法和步驟，均可 根據本揭露來加以應用。因此，所附之申請專利範 欲：這些製程、機台、製造、組成、手段、方法和步； 包含在其範圍内。此外，每個申請專利範圍構成—個獨 立的實施例，各申請專利範圍與實施例的組合落 露的範圍内。 揭 【圖式簡單說明】 k上述結合所附圖式所作的詳細描述，可對本揭露 之各態樣有更佳的了解。強調的是，根據此產業中之標 準常規，不同的特徵未依比例繪示且僅做為說明目的^ 用。事實上，為了使討論更清楚，各特徵的尺寸都可任 意地增加或減少。 第1圖係繪示依照本揭露之一實施例之一種製造積 體電路裝置之方法的流程圖。 第2圖到第7A圖係繪示依照第丨圖之方法在各種 製造階段之一種積體電路裝置之實施例之各種剖面示意 圖和透視圖。 第8圖係繪示依照本揭露之另—實施之一 積體電路裝置之方法的流程圖。 第9圖至第14圖係繪示依照第8圖之方法在各種製 造階段期間之一種積體電路裝置之實施例之各種剖面^ 201222727 意圖。 【主要元件符號說明】 100 :方法 102 ： 104 :步驟 106 ： 108 :步驟 110 ： 111 :源極/汲極區 112 ： 113 :源極/汲極區 114 ： 115 .源極/ >及極區 116 ： 120 :閘極介電質 122 ： 124 :電性傳輸結構 126 ： 130 :傳導層 132 ： 134 :傳導帶 140 ： 142 :閘極電極 144 ： 146 :閘極間隙壁 150 ： 160 :接觸插塞 170 ： 200 :半導體裝置 200a 200b :第二閘極帶 211 ： 213 :源極/汲極區 215 ： 216 :内層介電層 218 ： 218a :溝渠開口 218b 220 :閘極介電質 222 ： 224 :電性傳輸結構 226 ： 230 :傳導層 232 ： 234 :傳導帶 240 ： 步驟 步驟 步驟 步驟 步驟 内層介電層 閘極電極 閘極間隙壁 傳導帶 閘極介電質 電性傳輸結構 内層介電層 金屬線 :第一閘極帶 源極/ >及極區 源極/ >及極區 圖案化層 :溝渠開口 閘極電極 閘極間隙壁 傳導帶 閘極介電質 17 201222727 242 ： 246 ： 260 ： 300 ： 300b 304 ： 308 ： 312 ： 316 ： 700 ： Ml : Wlb W2b W3b W4b 閘極電極 244 ： 電性傳輸結構 閘極間隙壁 250 ： 内層介電層 接觸插塞 270 金屬線 方法 300a :第一閘極帶 :第一閘極帶 302 步驟 步驟 306 步驟 步驟 310 步驟 步驟 314 步驟 步驟 400 半導體裝置 基材 800 :基材 金屬線 Wla :寬度 :寬度 W2a :寬度 :寬度 W3a :寬度 :寬度 W4a :寬度 :寬度 18

Claims (1)

  1. 201222727 七、申請專利範圍： i 一種形成積體電路結構之方法，包含·· 形成具有一第一寬度之一閘極帶位於一基材上之 一内層介電層之中； 弟 形成具有—第二寬度之—傳導帶於該間極帶之上； 形成-第二内層介電層於該第一内 導帶之上；以及 s々ΧΊ哥 形成-傳導插塞於該第二内層介電層之中、和該傳 守市上。 以及 步^:請求項1所述之方法’其中形成該傳導帶之該 •形成一傳導層於該閘極帶和該第—内層介電層 帶 圖案化該傳導層，來形成該傳導 3.如請求項1所述之方法，其中該傳導帶包 鋁、銅、氮化鈦、氮化钽、鎢化鈦、或其組合之一材=、 4·如請求項丨所述之方法，其中該傳導 介於100埃至1〇,〇〇0埃之一厚度。 '、已圍 閘極 5.如請求項1所述之方法，其中該 閘極帶係 金屬 19 201222727 々6.如請求項丨所述之方法，其中該第二寬度對該第 一寬度之一比例範園介於1至6之間。 7_如請求項1所述之方法，更包含： 形成一電性傳輸結構介於該閘極帶和該傳導帶 間。 8·如請求項7所述之方法， 在呂及/或金屬石夕。 其中該電性傳輸結構係 9. 一種形成積體電路結構之方法， 形成具有一第一寬度之一閘極帶， 於一基材上之一第一内層介電層之中； 包含： 其中5亥閘極帶位 形成一圖案化層於該閘極帶之上 具有一溝渠開口位於該閘極帶之上； 其中該圖案化層 形成一傳導帶於該溝渠開口之中 有—第二寬度； 其中該傳導帶具 形成一 形成一 傳導帶之上 第二内層介電層於該傳導帶之上 傳導插塞於該第二内層介電層之 :以及 中、且於該 ί0. 一種積體電路結構，包含： 第一内層介電層位於一基材之上； 20 201222727 一閘極帶位於該第一内層介電層之中 帶具有一第一寬度； 其中該閘極 第一内層介電層位於該閘極帶和該一 層之上； 内層介電 —接觸插塞位於該第 一傳導帶介於該接觸 傳導帶具有一第二寬度。 一内層介電層之中；以及 插塞和該閘極帶之間，其中該 21
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US9620421B2 (en) 2017-04-11
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US20120119306A1 (en) 2012-05-17
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US10068836B2 (en) 2018-09-04
US20170213780A1 (en) 2017-07-27

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