TWI463603B - 形成積體電路結構之方法與積體電路結構 - Google Patents

形成積體電路結構之方法與積體電路結構 Download PDF

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TWI463603B
TWI463603B TW100108779A TW100108779A TWI463603B TW I463603 B TWI463603 B TW I463603B TW 100108779 A TW100108779 A TW 100108779A TW 100108779 A TW100108779 A TW 100108779A TW I463603 B TWI463603 B TW I463603B
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gate
strip
dielectric layer
conductive
inner dielectric
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TW100108779A
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TW201222727A (en
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Chienchih Ho
Chihping Chao
Huachou Tseng
Chunhong Chen
Chiayi Su
Kalnitsky Alexander
Jyeyen Cheng
Harry Haklay Chuang
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Taiwan Semiconductor Mfg Co Ltd
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Description

形成積體電路結構之方法與積體電路結構
本揭露一般是有關於半導體裝置之領域，且特別是有關於金屬閘極電晶體、積體電路、系統、和其製造方法。
半導體積體電路(IC)工業已歷經快速成長。IC材料與設計方面的技術進步已產生了多個IC世代，其中每一世代具有相較於前一世代更小且更複雜的電路。然而，此些進步已增加了處理與製造IC的複雜度，且為了實現上述之進步，在IC處理與製造方面亦需有類似的發展。
在IC發展的進程(Course)中，當幾何尺寸[亦即使用製造程序所能產生的最小元件(或線)]已經縮小時，功能密度(亦即每一晶片面積中內連裝置的數量)大致上已經增加。此微縮化製程一般藉由增加生產效率和降低相關的成本來提供利益。此微縮化亦提供相對高的功率消耗值，其可藉由使用如互補式金屬氧化物半導體(CMOS)裝置之低功率消耗裝置來解決。
在此微縮化趨勢中，已使用各種不同的材料來做為互補式金屬氧化物半導體裝置之閘極電極和閘極介電質。互補式金屬氧化物半導體裝置一般形成有閘極氧化物和多晶矽閘極電極。隨著特徵尺寸持續遞減，以高介電常數(k)閘極介電質和金屬閘極電極來取代閘極氧化物和多晶矽閘極電極，以改善裝置性能已成為一種需求。
隨著技術持續地在縮小，例如，對於28奈米(nm)技術節點和更小之節點，具有窄寬度之金屬閘極電極可能造成高閘極電阻之問題。此高閘極電阻之問題可能影響互補式金屬氧化物半導體裝置之電性性能。例如，此高閘極電阻可能會降低在高頻下運轉之射頻互補式金屬氧化物半導體裝置(RFCMOS)之最大振盪頻率(fmax)、雜訊、和穩定性。
本發明之一目的就是在提供一種形成積體電路結構之方法，藉由形成具有足夠厚度且平行閘極帶之傳導帶，來降低整體的閘極電阻。
依據本發明一實施例，一種形成積體電路結構之方法包含形成具有第一寬度之閘極帶位於基材上之第一內層介電層之中，形成具有第二寬度之傳導帶於閘極帶之上。形成第二內層介電層於第一內層介電層和傳導帶之上，以及形成傳導插塞於第二內層介電層之中、和傳導帶之上。
依據本發明另一實施例，一種形成積體電路結構之方法包含形成具有第一寬度之閘極帶，其中閘極帶位於基材上之第一內層介電層之中。形成圖案化層於閘極帶之上，其中圖案化層具有溝渠開口位於閘極帶之上。形成傳導帶於溝渠開口之中，其中傳導帶具有第二寬度。形成第二內層介電層於傳導帶之上。以及形成傳導插塞於第二內層介電層之中、且於傳導帶之上。
依據本發明又一實施例，一種積體電路結構包含第一內層介電層位於基材之上，閘極帶位於第一內層介電層之中，其中閘極帶具有第一寬度。第二內層介電層位於閘極帶和第一內層介電層之上，接觸插塞位於第二內層介電層之中，以及傳導帶介於接觸插塞和閘極帶之間，其中傳導帶具有第二寬度。
本發明特別有利於藉由後閘極方法形成之射頻互補式金屬氧化物半導體裝置，本發明之優點為可改善互補式金屬氧化物半導體裝置之電性性能。
可了解的是以下的揭露提供了許多不同的實施例或例子，以執行本發明之不同特徵。以下所描述之構件與安排的特定例子係用以簡化本揭露。當然這些僅為例子，並非為限制。此外，在描述中，第一特徵之形成於第二特徵之上或上可能包含第一與第二特徵以直接接觸的方式形成的實施例，且亦可包含額外特徵可能形成在第一與第二特徵之間而使第一與第二特徵並未直接接觸的實施例。除此之外，本揭露在不同例子中可重覆參考數字及/或文字。此重覆係為了簡化和清晰之目的，並無指定不同實施例間之關連及/或討論之配置。
關於第2圖至第7A圖，依照第1圖之方法100在各種製造階段之一種半導體裝置200之一實施例的各種剖面示意圖和透視圖係在以下共同描述。此半導體裝置200繪示一積體電路、或其部分，其可包含記憶體單元及/或邏輯單元。此半導體裝置200可包含被動元件如電阻、電容、電感器及/或保險絲；和主動元件如P通道場效電晶體(PFETs)、N通道場效電晶體(NFETs)、金屬氧化物半導體場效應電晶體(MOSFETs)、互補式金屬氧化物半導體、射頻互補式金屬氧化物半導體(RFCMOS)、高電壓電晶體；其他合適的元件；及/或其組合。可理解的是，此方法之額外實施例可於方法100之前、期間、及/或之後，提供額外的步驟，且可取代或移除一些描述於下之步驟。進一步了解的是，半導體裝置200之額外實施例可增加額外的特徵於半導體裝置200中，且可取代或移除一些描述於下之特徵。
請參照第1圖和第2圖，方法100以步驟102開始，其中提供一基材700。在本實施例中，基材700係一含矽之半導體基材。替代地，基材700包含含矽及/或鍺之元素半導體；包含碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦、及/或銻化銦之複合半導體；包含鍺化矽(SiGe)、磷化鎵砷(GaAsP)、砷化鋁銦(AlInAs)、砷化鋁鎵(AlGaAs)、砷化鎵銦(GaInAs)、磷化鎵銦(GaInP)、及/或磷砷化鎵銦(GaInAsP)之合金半導體；或其組合物。此合金半導體基材可具有梯度分布的鍺化矽(SiGe)特徵，其中此梯度分布的鍺化矽特徵之矽和鍺組合從一地區之一比例更改至另一地區之另一比例。此合金鍺化矽可形成於矽基材之上。此鍺化矽其材可為受應變。此外，此半導體基材可為絕緣體上半導體(SOI)。在一些例子中，此半導體基材可包含摻雜的磊晶。在其他例子中，此矽基材可包含多層複合半導體結構。
基材700可根據設計要求(例如p型井或n型井)包含各種摻雜區。此摻雜區可以如硼(B)或氟化硼(BF)之p型摻質；如磷或砷之n型摻質；或其組合來摻雜。此摻雜區可直接形成於基材700中、在p井結構中、在n井結構中、在雙井(dual-well)結構中、或使用凸起結構。半導體裝置200可包含N通道場效電晶體及/或P通道場效電晶體裝置，且因此基材700可包含配置給每一N通道場效電晶體裝置及/或P通道場效電晶體裝置中之特定裝置之各種摻雜區。
請再次參照第1圖，適稱為ILD0之內層介電層(ILD)116可設置在基材700之上。此內層介電層116可包含介電材料，如氧化物、氮化物、氮氧化物、低k介電材料、超低k介電材料、極低k介電材料、另一介電質材料、或其組合。此內層介電層116可藉由，例如，化學氣相沉積(CVD)製程、高密度電漿化學氣相沉積(HDPCVD)製程、高深寬比製程(HARP)、旋轉塗佈製程、其他沉積製程、及/或其任何組合。在其他實施例中，額外的介電層(未繪示)可形成於內層介電層116之下或之上。
在實施例中，第一閘極帶200a和第二閘極帶200b形成於內層介電層116中和基材700之上。第一閘極帶200a可依序包含閘極介電質120和閘極電極122。第二閘極帶200b可依序包含閘極介電質140和閘極電極142。此第一和第二閘極帶200a和200b可分別具有藉由沉積形成之寬度W1a和W1b。
在實施例中，閘極介電質120和140包含介電材料，如氧化矽、氮氧化矽、氮化矽、高k介電材料、另一合適的介電材料、或其組合物。例示的高k介電材料包含氧化鉿(HfO2 )、氧化鉿矽(HfSiO)、氮氧鉿矽(HfSiON)、氧化鉿鉭(HfTaO)、氧化鉿鈦(HfTiO)、氧化鉿鋯(HfZrO)、其他合適的材料、或其組合物。閘極介電質120和140可為多層結構，例如，包含內界面層和形成於內界面層上之高k介電材料層。例示內界面層可為藉由熱處理或原子層沉積製程形成之成長氧化矽層。
閘極電極122和142分別形成於閘極介電質120和140之上，每一閘極電極122和140可包含具有適當功函數之傳導層。因此，閘極電極122和142亦可稱為功函數層。此功函數層包含任何適當的材料，如此一來可調整功函數層以具有適當的功函數來加強相關裝置之性能。例如，若需要P通道場效電晶體裝置之p型功函數金屬(p-metal)，可使用氮化鈦(TiN)或氮化鉭(TaN)。另一方面，若需要N通道場效電晶體裝置之n型功函數金屬(n-metal)，可使用鉭(Ta)、鋁化鉭(TiAl)、氮化鈦鋁(TiAlN)或碳氮化鉭(TaCN)。此功函數層可包含摻雜的傳導氧化材料。
在實施例中，閘極間隙壁126和146形成於內層介電層116中，且藉由適當的製程分別鍍於第一閘極帶200a和第二閘極帶200b之相對側壁上。此閘極間隙壁126和146可包含介電材料，如氧化物、氮化物、氮氧化物、另一介電材料、或其組合物。在另一實施例中，襯墊(未繪示)可藉由適當的製程形成於閘極帶200a與閘極間隙壁126之間和閘極帶200b與閘極間隙壁146之間。此襯墊可包含不同於閘極間隙壁126和146之適合的介電材料。
在實施例中，電性傳輸結構124和電性傳輸結構144形成於內層介電層116之中，且分別位於閘極電極122和142之上。此每一電性傳輸結構124和144可包含傳導材料，如鋁、銅、鎢、金屬合金、金屬矽化物、其他合適的材料、或其組合物。此電性傳輸結構124和144可藉由沉積和化學機械研磨製程(CMP)來形成。
在一些實施例中，共用源極或共用汲極區111(以下稱為源極/汲極區111)可能位於基材700中，且介於第一和第二閘極帶200a和200b之間。源極/汲極區113和115可分別形成於鄰近第一和第二閘極帶200a和200b。第一閘極帶200a與源極/汲極區111和113形成第一金屬氧化物半導體裝置，且第二閘極帶200b和源極/汲極區111與115形成第二金屬氧化物半導體裝置。
請參照第1圖和第3圖，方法100以步驟104持續進行，其中傳導層130形成於內層介電層116、第一和第二閘極帶200a和200b、及電性傳輸結構124和144之上。傳導層130可為金屬層，如鋁、銅、鎢；金屬合金層，如氮化鈦、鎢化鈦(TiW)、氮化鉭；其他合適的材料；或其組合物。在一些實施例中，傳導層130具有介於約100埃至約10,000埃之厚度。
請參照第1圖和第4圖，方法100以步驟106持續進行，其中藉由圖案化製程圖案化傳導層130，來形成傳導帶132和134。傳導帶132形成於第一閘極帶200a和電性傳輸結構124之上。傳導帶134形成於第二閘極帶200b和電性傳輸結構144之上。例如，此圖案化製程包含藉由旋轉塗佈之適當製程形成光阻層(未繪示)於傳導層130之上，且接著曝光與顯影此光阻層來形成光阻特徵。然後，藉由乾蝕刻製程將光阻特徵之圖案傳遞至下層的傳導層130來形成傳導帶132和134。在一些實施例中，傳導帶132和134可分別具有寬度W3a和W3b。在一實施例中，寬度W3a和W3b分別大於寬度W1a和W1b。在其他實施例中，寬度W3a對寬度W1a之比例及/或W3b對寬度W1b之比例範圍介於約1和約6之間。
替代地，當傳導層130使用和電性傳輸結構124與144相同之材料時，可將用以形成傳導層130之步驟104省略。例如，相關的製程流程可包含沉積鋁層於內層介電層116之中和之上、及於第一和第二閘極帶200a和200b之上；移除鋁層位於內層介電層116之部分，來形成平坦化的表面；以及圖案化此平坦化的鋁層，來形成電性傳輸結構124和144和傳導帶132和134。繪示於第4圖之結構之透視圖係繪示於第4A圖之中。
請參照第1圖和第5圖，方法100以步驟108持續進行，其中通稱為ILD1之額外的內層介電層150形成於傳導帶132和134與內層介電層116之上。此額外的內層介電層150可包含介電材料，如氧化物、氮化物、氮氧化物、低k介電材料、超低k介電材料、極低k介電材料、另一介電材料、或其組合物。此額外的內層介電層150可藉由化學氣相沉積製程、高密度電漿化學氣相沉積製程、高深寬比製程、旋轉塗佈製程、另一沉積製程、及/或任何其他組合。在實施例中，額外的內層介電150層可包含和使用於內層介電層116相同之材料。
請參照第1圖和第6圖，方法100以步驟110和112持續進行，其中接觸開口(未繪示)藉由一般使用的蝕刻製程形成於額外的內層介電層150及/或內層介電層116之中。在實施例中，至少三個接觸開口形成於傳導帶132和134與共用源極/汲極區111之上。接著，填充傳導層(未繪示)於接觸開口之中及額外的內層介電層150之上。接著，可提供化學機械研磨製程來完全的移除傳導層位於額外的內層介電層150之上之部分，而形成接觸插塞160於額外的內層介電層150及/或內層介電層116之中。
請參照第1圖與第7圖，方法100以步驟114持續進行，其中通稱為M1之金屬線170形成於接觸插塞160之上。繪示於第7圖之結構之透視圖係繪示於第7A圖。
關於第9圖至第14圖，根據第8圖之方法300在不同製程階段之半導體裝置400之一實施例之各種剖面示意圖係共同地在以下描述。半導體裝置400繪示積體電路、或其部分，其可包含記憶體單元及/或邏輯電路。半導體裝置400可包含被動元件，如電阻、電容、電感器、及/或保險絲；和主動元件，如P通道場效電晶體、N通道場效電晶體、金屬氧化物半導體場效電晶體、互補式金屬氧化物半導體電晶體、射頻互補式金屬氧化物半導體電晶體、高電壓電晶體；其他合適的元件；及/或其組合。可理解的是，此方法之額外實施例可於方法300之前、期間、及/或之後，提供額外的步驟，且可取代或移除一些描述於下之步驟。進一步瞭解的是，半導體裝置400之額外實施例可增加額外的特徵於半導體裝置400之中，且可取代或移除一些描述於下之特徵。
請參照第8圖和第9圖，方法300以步驟302開始進行，其中提供半導體裝置400之結構，半導體裝置400具有和第1圖相同之項目以相同參考數字加上100來表示。在實施例中，設置內層介電層216於基材800之上。在實施例中，設置包含位於閘極介電質220上之閘極電極222之第一閘極帶300a、以及包含位於閘極介電質240上之閘極電極242之第二閘極帶300b於內層介電層216之中。每一第一閘極帶300a和第二閘極帶300b分別具有寬度W2a和W2b。在實施例中，共用源極/汲極區211位於基材800中，且介於第一閘極帶300a和第二閘極帶300b之間。源極/汲極區213和215可分別鄰近於第一閘極帶300a和第二閘極帶300b。在實施例中，設置閘極間隙壁226和246於內層介電層216之中，且分別置於第一閘極帶300a和第二閘極帶300b之相對側壁上。在實施例中，設置電性傳輸結構224和244於內層介電層116之中，且分別設於閘極電極222和242之上。
請參照第8圖和第10圖，方法300以步驟304持續進行，其中圖案化層218形成於內層介電層216之上。在一實施例中，圖案化層218係介電層。在另一實施例中，圖案化層218包含一材料，其與內層介電層216使用相同材料。在實施例中，圖案化層218具有溝渠開口218a於第一閘極帶300a之上、和溝渠開口218b於第二閘極帶300b之上。溝渠開口218a和218b分別具有寬度W4a和W4b。在實施例中，此圖案化層218具有範圍從約100埃至約10,000埃之間之厚度。
請參照第8圖至第11圖，方法300以步驟306持續進行，其中傳導層230形成於溝渠開口218a和218b之中，且位於圖案化層218之上。傳導層230可為金屬層，如鋁、銅、鎢；金屬合金層，如氮化鈦、鎢化鈦、氮化鉭；其他合適的材料；或其組合物。
請參照第8圖和第12圖，方法300以步驟308持續進行，其中移除傳導層位於圖案化層218之上之部分，以形成傳導帶232和234。此傳導帶234位於電性傳輸結構244之上，且第一閘極帶300a具有寬度W4a。傳導帶234位於電性傳輸結構244之上，且第二閘極帶300b具有寬度W4b。在實施例中，此移除製程包含化學機械研磨製程，因此，傳導帶232和234具有實質上和圖案化層218共平面之平坦化的表面。
請參照第8圖和第13圖，方法300以步驟310至314持續進行，其中額外的內層介電層250形成於傳導帶232和234、與圖案化層218之上。額外的內層介電層250可包含介電材料，如氧化物、氮化物、氮氧化物、低k介電材料、超低k介電材料、極低k介電材料、其他介電材料、或其組合物。在實施例中，額外的內層介電層250可包含一材料，其與內層介電層216使用相同材料。接著，藉由蝕刻製程形成接觸開口(未繪示)於額外的內層介電層250、圖案化層218、及/或內層介電層216之中。在實施例中，至少三個接觸開口形成於接觸帶232和234與共用源極/汲極區211之上。之後，填充傳導層(未繪示)於接觸開口之中與額外的內層介電層250之上，接著，可提供化學機械研磨製程來完整移除傳導層於額外的內層介電層250之上之部分，而形成接觸插塞260於額外的內層介電層250、圖案化層218、及/或內層介電層216之中。
請參照第8圖和第14圖，方法300以步驟316持續進行，其中金屬線270形成於接觸插塞260之上。繪示於第14圖之結構之透視圖係與繪示於第7A圖之相同。
本發明之實施例具有許多優勢特徵。藉由形成具有足夠厚度且平行閘極帶之傳導帶，可降低整體的閘極電阻。因此，改善互補式金屬氧化物半導體裝置之電性性能。此特別有利於藉由後閘極方法形成之射頻互補式金屬氧化物半導體裝置，原因在於當這些裝置在高頻下運轉時，高閘極電阻可導致電性最大振盪頻率、雜訊和穏定性的降低。
雖然己詳述本發明與其優點，應理解的是此處可在不脫離所附申請專利範圍所定義之實施例的精神和範圍下，做各種之更動、替代與潤飾。再者，本申請之範圍並不受限於說明書所述之製程、機台、製造、組成、手段、方法和步驟的特定實施例。在此技術領域中具有通常知識者可自本揭露了解到：現存或日後所發展之進行與在此所描述之實施例實質相同之功能或達到相同結果的製程、機台、製造、組成、手段、方法和步驟，均可根據本揭露來加以應用。因此，所附之申請專利範圍意欲將這些製程、機台、製造、組成、手段、方法和步驟包含在其範圍內。此外，每個申請專利範圍構成一個獨立的實施例，各申請專利範圍與實施例的組合落在本揭露的範圍內。
100．．．方法
102．．．步驟
104．．．步驟
106．．．步驟
108．．．步驟
110．．．步驟
111．．．源極/汲極區
112．．．步驟
113．．．源極/汲極區
114．．．步驟
115．．．源極/汲極區
116．．．內層介電層
120．．．閘極介電質
122．．．閘極電極
124．．．電性傳輸結構
126．．．閘極間隙壁
130．．．傳導層
132．．．傳導帶
134．．．傳導帶
140．．．閘極介電質
142．．．閘極電極
144．．．電性傳輸結構
146．．．閘極間隙壁
150．．．內層介電層
160．．．接觸插塞
170．．．金屬線
200．．．半導體裝置
200a．．．第一閘極帶
200b．．．第二閘極帶
211．．．源極/汲極區
213．．．源極/汲極區
215．．．源極/汲極區
216．．．內層介電層
218．．．圖案化層
218a．．．溝渠開口
218b．．．溝渠開口
220．．．閘極介電質
222．．．閘極電極
224．．．電性傳輸結構
226．．．閘極間隙壁
230．．．傳導層
232．．．傳導帶
234．．．傳導帶
240．．．閘極介電質
242．．．閘極電極
244．．．電性傳輸結構
246．．．閘極間隙壁
250．．．內層介電層
260．．．接觸插塞
270．．．金屬線
300．．．方法
300a．．．第一閘極帶
300b．．．第一閘極帶
302．．．步驟
304．．．步驟
306．．．步驟
308．．．步驟
310．．．步驟
312．．．步驟
314．．．步驟
316．．．步驟
400．．．半導體裝置
700．．．基材
800．．．基材
M1．．．金屬線
W1a．．．寬度
W1b．．．寬度
W2a．．．寬度
W2b．．．寬度
W3a．．．寬度
W3b．．．寬度
W4a．．．寬度
W4b．．．寬度
從上述結合所附圖式所作的詳細描述，可對本揭露之各態樣有更佳的了解。強調的是，根據此產業中之標準常規，不同的特徵未依比例繪示且僅做為說明目的使用。事實上，為了使討論更清楚，各特徵的尺寸都可任意地增加或減少。
第1圖係繪示依照本揭露之一實施例之一種製造積體電路裝置之方法的流程圖。
第2圖到第7A圖係繪示依照第1圖之方法在各種製造階段之一種積體電路裝置之實施例之各種剖面示意圖和透視圖。
第8圖係繪示依照本揭露之另一實施例之一種製造積體電路裝置之方法的流程圖。
第9圖至第14圖係繪示依照第8圖之方法在各種製造階段期間之一種積體電路裝置之實施例之各種剖面示意圖。
100．．．方法
102．．．步驟
104．．．步驟
106．．．步驟
108．．．步驟
110．．．步驟
112．．．步驟
114．．．步驟

Claims (9)

  1. 一種形成積體電路結構之方法，包含：形成具有一第一寬度之一閘極帶位於一基材上之一第一內層介電層之中；形成具有一第二寬度之一傳導帶於該閘極帶之上，其中該第二寬度對該第一寬度之比值為約1至約6；形成一第二內層介電層於該第一內層介電層和該傳導帶之上；以及形成一傳導插塞於該第二內層介電層之中、和該傳導帶之上。
  2. 如請求項1所述之方法，其中形成該傳導帶之該步驟包含：形成一傳導層於該閘極帶和該第一內層介電層之上；以及圖案化該傳導層，來形成該傳導帶。
  3. 如請求項1所述之方法，其中該傳導帶包含鎢、鋁、銅、氮化鈦、氮化鉭、鎢化鈦、或其組合之一材料。
  4. 如請求項1所述之方法，其中該傳導帶具有範圍介於100埃至10,000埃之一厚度。
  5. 如請求項1所述之方法，其中該閘極帶係一金屬 閘極。
  6. 如請求項1所述之方法，更包含：形成一電性傳輸結構介於該閘極帶和該傳導帶之間。
  7. 如請求項6所述之方法，其中該電性傳輸結構係鋁及/或金屬矽。
  8. 一種形成積體電路結構之方法，包含：形成具有一第一寬度之一閘極帶，其中該閘極帶位於一基材上之一第一內層介電層之中；形成一圖案化層於該閘極帶之上，其中該圖案化層具有一溝渠開口位於該閘極帶之上；形成一傳導帶於該溝渠開口之中，其中該傳導帶具有一第二寬度，其中該第二寬度對該第一寬度之比值為約1至約6；形成一第二內層介電層於該傳導帶之上；以及形成一傳導插塞於該第二內層介電層之中、且於該傳導帶之上。
  9. 一種積體電路結構，包含：一第一內層介電層位於一基材之上；一閘極帶位於該第一內層介電層之中，其中該閘極 帶具有一第一寬度；一第二內層介電層位於該閘極帶和該第一內層介電層之上；一接觸插塞位於該第二內層介電層之中；以及一傳導帶介於該接觸插塞和該閘極帶之間，其中該傳導帶具有一第二寬度，其中該第二寬度對該第一寬度之比值為約1至約6。
TW100108779A 2010-11-17 2011-03-15 形成積體電路結構之方法與積體電路結構 TWI463603B (zh)

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