TW201216432A - Semiconductor device and manufacturing method for the same - Google Patents

Semiconductor device and manufacturing method for the same Download PDF

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Publication number
TW201216432A
TW201216432A TW100128610A TW100128610A TW201216432A TW 201216432 A TW201216432 A TW 201216432A TW 100128610 A TW100128610 A TW 100128610A TW 100128610 A TW100128610 A TW 100128610A TW 201216432 A TW201216432 A TW 201216432A
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Taiwan
Prior art keywords
semiconductor device
electrode
film
barrier metal
protective film
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Application number
TW100128610A
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English (en)
Inventor
Tatsuo Migita
Hirokazu Ezawa
Soichi Yamashita
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Toshiba Kk
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Publication date
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Publication of TW201216432A publication Critical patent/TW201216432A/zh

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201216432 六、發明說明： 【發明所屬之技術領域】 本實施形態一般係關於半導體裝置及半導體裝置之製造 方法。 本申請案主張2010年8月31曰提出申請之日本專利申請 案第2010-195092號之優先權之利益，該申請案之全部内 谷以引用的方式併入本文中。 【先前技術】 為達成半導體器件之高集成化與高功能化，日益要求器 件之動作速度之提高及記憶體之大容量化。根據器件所 需，替代1晶片之eDRAM，亦已開發以層疊式晶片堆疊 (CoC)連接將邏輯電路與大容量Dramk裝化之晶片。 例如’以CoC連接邏輯電路與大容量dram之情形下， 為達成寬頻帶之傳送速度，要求於晶片内之特定區域形成 多個凸塊。為形成多個凸塊，要求儘可能微細地形成凸塊 間距及凸塊直徑。 又於半導體基板上形成重佈線或凸塊等之際，會有藉 由光微影步驟於感光性材料形成圖案開口之情形。此時， 根據底層之表面狀態，會有因光之亂反射等導致感光性材 料之感光狀態不斷變化之情形，而有開口形狀變形、開口 直徑產生偏差之情形。 若開口形狀變形、開口直和吝在值& Ί直仨產生偏差，則形成於該開口 部分之凸塊之高度會有偏差，成為c〇c連接之可靠性降低 之主要原因，故要求適宜地管理感光性材料之底層之表面 157987.doc 201216432 狀態。 【發明内容】 根據實施形態’本發明之半導體裝置設置有焊墊電極、 保護膜、底層阻障金屬膜、及電極配線部。焊墊電極係形 成於半導體基板。保護膜係以使上述焊墊電極之表面露出 之方式形成於上述半導體基板上。底層阻障金屬膜係形成 於上述焊墊電極及上述保護膜上。電極配線部係介隔上述 底層阻障金屬膜而形成於上述焊墊電極上。又，上述底層 阻障金屬膜之表面反射率在波長8〇〇 nm下為3〇%以上；上 述電極配線部之直徑為140 μηι以下。 【實施方式】 以下，茲參照圖面說明實施形態之半導體裝置及半導體 裝置之製造方法。另，本發明並非限定於該等實施形態。 圖1⑷〜(c)、圖2⑷〜⑷、圖3(a)〜(c)、及圖4⑷〜⑷係顯 示一實施形態之半導體裝置之製造方法的剖面圖。 圖1 (a)中，於基材層1上形成有焊墊電極2，且以覆蓋焊 墊電極2之方式形成有保護膜3。另，作為基材層1，可使 用形成有例如邏輯電路或DRAM等之積體電路之半導體基 板又，焊墊電極2之材料，可使用例如鋁或以鋁為主成 伤之金屬。又，保護膜3之材料，可使用例如氧化矽膜或 氮氧化碎膜或氮化矽膜等之無機絕緣體。 然後，藉由利用光微影技術，於保護膜3上形成於焊墊 電極2上具有開口部4a之抗蝕劑圖案4。 其後如圖1 〇)所示，以抗蝕劑圖案4為遮罩，對保護 157987.doc 201216432 膜3進行RIE荨之各向異性钱刻’藉此於保護膜3上形成開 口部3a。此處，於保護膜3上形成開口部3a之際，因焊墊 電極2之表面被蝕刻，使得焊墊電極2之蝕刻殘渣飛散， 故會於抗蝕劑圖案4之表面附著蝕刻殘渣2a。 其後，如圖1 (c)所示，利用灰化等之方法，除去保護膜3 上之抗蝕劑圖案4。此處，在除去抗蝕劑圖案4之際，蝕刻 殘渣2a殘留於保護膜3上，故於保護膜3之表面附著有蝕刻 殘潰2a。 其後，如圖2(a)所示，藉由蝕刻保護膜3之表面，使蝕刻 殘渣2a脫除，而自保護膜3之表面除去蝕刻殘渣&。另， 作為保護膜3之表面之蝕刻方法，例如在保護膜3之表面由 氧化膜或氮化膜構成之情形了，可利用以稀氮氣酸為藥液 之濕式姓刻。 其後，如圖2(b)所示，藉由利用濺鍍、鍍敷、eVD、 ALD或蒸鍍等之方法，於焊墊電極2及保護膜3上形成底層 阻障金屬膜5 〇此外，作為底層阻障金屬膜5，可使用例如 Τι與其上之Cu之積層構造。另，亦可使用TiN、Tiw、w、
Ta、Cr、Co等材料替代Ti.。亦可使用A1、pd、Au、Ag等 材料替代Cu。 此處，除去保護膜3之表面之蝕刻殘渣2a之後，於保護 膜3上形成底層阻障金屬膜5，藉此’相較於不除去保護膜 3之表面之蝕刻殘渣2a之情形，可緩和底層阻障金屬膜5之 表面粗度，從而可增加底層阻障金屬膜5之表面反射率。 其後’如圖2⑷所示，藉由利用旋塗等之方法，於底層 157987.doc 201216432 阻？早金屬膜5上形成抗钮劑膜6 ^此外，抗蚀劑膜6之材料 可使用負型感光性抗蝕劑。 其後，如圖3(a)所示，藉由以形成有遮光膜12之光罩^ 為遮罩進行抗餘劑膜6之曝光’於抗蝕劑膜6形成配置於圖 3(b)之開口部6a之周圍之潛像6,。 此處’抗触劑膜6之材料為負型感光性抗蝕劑之情形 時，曝光光源RI在開口部6a被遮蔽，曝光光源ri入射至開 口部6a之周圍之抗蝕劑膜6 ^其後，曝光光源RI透射抗蝕 劑膜6，到達底層阻障金屬膜5之表面後，根據底層阻障金 屬膜5之表面粗度，而使曝光光源幻產生亂反射，亂反射 光RF入射至作為開口部6a被除去之抗蝕劑膜6之部分。 其後’如圖3(b)所示’藉由進行抗蝕劑膜6之顯影，於 抗姓劑膜6形成配置於焊墊電極2上之開口部6a。另，開口 6a之開口直在為140 μιη以下時，抗鞋劑膜6之底層之表 面反射率在波長800 nm下為80%以上較佳。 又，開口部6a之開口直徑為40 μιη以下時，抗蝕劑臈6之 底層之表面反射率在波長80〇 nm下為90%以上較佳，又， 開口部6a之開口直徑為2〇 μηι以下時，抗蝕劑臈6之底層之 表面反射率在波長.8〇〇 ηιη下為98%以上較佳。 此處，在圖3(a)之步驟中，當亂反射光RF入射於作為開 口部6a被除去之抗蝕劑膜6之部分後，亦會於該部分形成 潛像6’，由於開口部以之直徑變小’故開口部以之直徑會 產生偏差。 此時，藉由於保護膜3上形成底層阻障金屬膜5之前，除 J57987.doc 201216432 去保護膜3之表面之蝕刻殘渣2a，可增大抗蝕劑膜6之底層 之表面反射率*因此’可減低透射抗蝕劑膜6之曝光光源 RI在抗蝕劑膜6之底層之亂反射，從而減低亂反射光]；117入 射至作為開口部6a被除去之抗钱劑膜6之部分。其結果， 可抑制開口部6a之直徑變小，減低開口部6a之直徑之偏 差。 此處，當開口部6a之開口直徑為MO μιη以下時，將抗蝕 劑膜6之底層之表面反射率在波長8〇〇 nm下設為8〇%以上 是因為，若表面反射率小於80%，則殘留於保護膜3之表 面之蝕刻殘渣2a的量會增多，會使開口部6a之直徑之偏差 的影響增大。 又，當開口部6a之開口直徑減小時增大表面反射率是因 為，開口部6a之直徑之偏差對埋入開口部6a之突出電極之 高度之偏差的影響增大。 其後，如圖3(c)所示，利用電解鍍敷，於開口部依序 埋入P早壁層7及焊錫層8、9，藉此，介隔底層阻障金屬臈$ 而於:fcp塾電極2上形成突出電極。此外，例如，障壁層7之 材料可使用Ni ·，焊錫層8之材料可使用Cu ;焊錫層9之材料 可使用Sn。 , 其後，如圖4(a)所示，利用灰化等之方法，除去底層陌 障金屬膜5上之抗触劑膜6。 其後，如圖4(b)所示，以包含障壁層7及焊錫層8、9之 大出電極為遮罩而蝕刻底層阻障金屬膜5，藉此，除去包 含障壁層7及焊錫層8、9之突出電極之周圍之底層阻障金 157987.doc 201216432 屬膜5。 其後，如圖4(c)所示，藉由回焊焊錫層8、9，將焊錫層 8、9合金化’於障壁層7上形成合金焊錫層1〇。 以上之步驟可在基材層1為晶圓之狀態下進行。且，以 上之步驟之後’藉由將該晶圓單片化，可切出半導體晶 片。 此處’藉由減低開口部6a之直徑之偏差’即使依序埋入 開口部6a之障壁層7及焊錫層8、9的量不論開口部6a之直 徑而保持一定之情形，仍可減低包含障壁層7及焊錫層8、 9之突出電極之高度的偏差，可提高c〇c連接之可靠性。 此時’當包含障壁層7及焊錫層8、9之突出電極之直徑 為140 μπι以下時，底層阻障金屬膜5之表面反射率在波長 800 nm下為80%以上較佳。又，當包含障壁層7及焊錫層 8、9之突出電極之直徑為40 μιη以下時，底層阻障金屬臈$ 之表面反射率在波長8〇〇 nm下為90%以上較佳。又，包含 障壁層7及焊錫層8、9之突出電極之直徑為2〇 μηι&下時， 底層阻障金屬膜5之表面反射率在波長8〇〇 nm下為98%以 上較佳。 此外，在上述實施形態令，雖說明了使用焊錫球作為突 出電極之方法，但亦可使用鎳凸塊、金凸塊或鋼凸塊等。 又，在上述實施形態中，雖說明了使用丁丨與以之積層構造 作為底層阻障金屬膜5之方法，但亦可以單體使用Ti =
Cu’可使用Cr、Pt、w等作為單體，或使用該等金屬之積 層構造。Ti亦可使用其他TiN、Tiw、w、Ta、Cr、c〇等之 157987.doc 201216432 材料，或其積層構造。 又，作為CoC連接之突出電極之接合方法，可使用焊錫 接合或合金接合等之金屬接合，亦可使用ACF(Anisotropic Conductive Film : 各向異性導電膜）接合、NCF (Nonconductive Film :非導電膜）接合、ACP(Anisotropic Conductive Paste :各向異性導電膠）接合、NCP (Nonconductive Paste:非導電膠）接合等。 圖5係顯示Ti/Cu膜相對波長800 nm的反射率與其表面狀 態之關係之圖。 圖5中，作為未有蝕刻殘渣2a時之抗蝕劑膜6之底層之樣 本W1，係使用於條斑之Si基板上以濺鍍形成Ti/Cu膜（膜厚 為200/300 μπι)者。該樣本W1之表面反射率在波長800 nm 下為98.3%。 其後，作為有蝕刻殘渣2a時之抗蝕劑膜6之底層之樣本 W3，係使用在圖1(b)及圖1(c)之步驟中獲得之樣本上以濺 鍍形成Ti/Cu膜（膜厚為200/300 μιη)者。此外，該樣本W3 中，使用氮化矽膜作為保護膜3。又，根據該樣本W3，可 確認蝕刻殘渣2a附著於保護膜3上，Ti/Cu膜之表面粗糙。 該樣本W3之表面反射率在波長800 nm下為3 0.9%。 此外，樣本W1、W 3之表面反射率之測定，係使用反射 率分光膜厚計FE-3 000(大塚電子製造）。 如此，Ti/Cu膜下之钮刻殘漬2a之有無，與Ti/Cu膜之表 面反射率之間係相關的，即隨著Ti/Cu膜下之蝕刻殘渣2a 的增大，Ti/Cu膜之表面反射率會降低。因此，藉由測量 157987.doc 201216432
Ti/Cu膜之表面反射率，可評價Ti/Cu膜下之蝕刻殘渣2a之 量，從而可預測形成於Ti/Cu膜上之抗蝕劑開口部之直徑 之偏差。 圖6係顯示抗蝕劑膜之底層之反射率與抗蝕劑開口直徑 之關係的剖面圖及表面圖。 圖6中，作為抗蝕劑膜之底層，準備了在波長為8〇〇 nm 下表面反射率為98%、78%、27%之樣本◊此外，為使抗 蝕劑之底層之表面反射率發生變化，而變化抗蝕劑膜之底 層之表面粗度。 然後’於該等底層上以旋塗塗布抗触劑膜，在同一曝光 條件及同一顯影條件下於該等抗蝕劑膜形成開口部。且， 以電子掃描顯微鏡觀察形成於該等抗蝕劑膜之開口部之上 面形狀及剖面形狀。 其結果為：表面反射率為98%之樣本中，開口直徑為 21.0 μπι ;表面反射率為78%之樣本中，開口直徑為19 8 μιη ;表面反射率為27%之樣本中，開口直徑為17 6 μιη， 可禮認開口直徑隨著表面反射率降低而減小。 此外’在上述實施形態中，雖說明了以抗蝕劑膜6之底 層之表面反射率規定用以減低開口部6a之直徑之偏差的抗 蝕劑膜6之底層之表面狀態的方法，但亦可使用將抗蝕劑 膜ό之底層之表面反射率換算為表面粗度之值的方法。 又，上述實施形態中，雖以使用突出電極作為電極配線 部之情形為例進行了說明，但亦可以使用支柱、重佈線或 焊墊等作為電極配線部。 157987.doc •10- 201216432 以上說明了本發明之若干實施形態，但該等實施形態僅 作為例而k不者，並無限定發明之辄圍之意圖。該等新額 之實施形態可以其他各種形態實施’在不脫離發明要旨之 範圍内’可進行各種省略、置換、變更。該等實施形態或 其變形’包含於發明之範圍或要旨，且包含於專利申請範 圍所記載之發明及其均等之範圍中。 【圖式簡單說明】 圖Ua)-(c)係顯示一實施形態之半導體裝置之製造方法 的剖面圖。 圖2(a)-(c)係顯示一實施形態之半導體裝置之製造方法 的剖面圖。 圖3(a)-(c)係顯示一實施形態之半導體裝置之製造方法 的刮面圖。 圖4(a)-(c)係顯示一實施形態之半導體裝置之製造方法 的剖面圖》 圖5(a)、（b)係顯示Ti/Cu膜相對波長800 nm的反射率與 其表面狀態之關係之圖。 圖6係顯示抗蝕劑膜之底層之反射率與抗蝕劑開口直徑 之關係的剖面圖及表面圖。 【主要元件符號說明】 1 基材層 2 焊墊電極 2a 飯刻殘潰 3 保護膜 157987.doc 201216432 3a 開口部 4 抗蝕劑圖案 4a 開口部 5 底層阻障金屬膜 6 抗姓劑膜6 6' 潛像 6a 開口部 7 障壁層 8 焊錫層 9 焊錫層 10 合金焊錫層 RF 亂反射光 RI 曝光光源 W1 樣本1 W3 樣本2 157987.doc -12-

Claims (1)

  1. 201216432 七、申請專利範圍： 1. 一種半導體裝置，其特徵為包含： 焊墊電極’其係形成於半導體基板； 保護膜’其係以露出上述焊墊電極之表面之方式而形 成於上述半導體基板上； 底層阻障金屬膜’其係形成於上述焊墊電極及上述保 護膜上；及 電極配線部’其係介隔上述底層阻障金屬膜而形成於 上述焊墊電極上；且， 上述底層阻障金屬膜之表面反射率在波長8〇〇 nm下為 3〇%以上，上述電極配線部之直徑為140 μηι以下。 2. 如清求項1之半導體裝置，其中上述底層阻障金屬膜之 表面反射率在波長8〇〇 nm下為80%以上，上述電極配線 部之直徑為4〇 μη!以下。 3. 如明求項1之半導體裝置，其中上述底層阻障金屬膜之 表面反射率在波長800 nm下為98%以上，上述電極配線 部之直徑為20 μηι以下。 4. 如請求項1之半導體裝置，其中上述電極配線部為突出 電極。 5. 如請求項4之半導體裝置，其中上述突出電極為焊錫 球。 , 6. 如請求項丨之半導體裝置，其中上述電極配線部為支 柱、重佈線或焊墊。 7. 如請求項1之半導體裝置，其係上述底層阻障金屬膜之 157987.doc 201216432 下層選自 Ti、TiN、TiW、W、Ta、Cr、c〇Ti中任一者， 且上述金屬膜之上層選自Cu、A卜Pd、Au、Ag中任一 者之積層構造。 8·如請求们之半導體裝置’其中於上述半導體基板上形 成有積體電路。 9.如請求们之半導體裝置’其中上述保護膜為無機絕緣 體。 1〇‘如請求項1之半導體裝置，其中上述保護膜之飯刻殘逢 自上述保護膜之表面被除去。 U. 一種半導體裝置之製造方法，其特徵為包含： 於半導體基板上形成焊墊電極之步驟； 以覆蓋上述焊墊電極之方式於上述半導體基板上形成 保護膜之步驟； 於上述保護膜上形成於上述焊墊電極上具有第i開口 部之第1抗叙劑圖案之步驟； 藉由以上述第1抗蝕劑圖案為遮罩蝕刻上述保護膜， 而於上述保護膜上形成使上述焊墊電極露出之第2開口 部之步驟； 除去形成有上述第2開口部之上述保護膜上之上述第ι 抗蝕劑圖案之步驟； 藉由姓刻上述保護膜之表面，而自上述㈣以表面 除去上述焊墊電極之蝕刻殘渣之步驟； 於上述焊塾電極上及已自表面除去上述谭塾電極之钱 刻殘渣之保護膜上形成底層阻障金屬膜之步驟，· 157987.doc 201216432 於上述底層阻障金屬膜上形成於上述焊墊電極上具有 第3開口部之第2抗蝕劑圖案之步驟； 於上述底層阻障金屬膜上形成埋入上述第3開口部之 電極配線部之步驟； 除去形成有上述電極配線部之上述底層阻障金屬獏上 . 之上述第2抗钱劑圖案之步驟；及 藉由以上述電極配線部為遮罩蝕刻上述底層阻障金屬 膜，而除去上述電極配線部之周圍之上述底層阻障金屬 膜之步驟。 I2·如請求項11之半導體裝置之製造方法，其中上述第2抗 钮劑圖案之底層之表面反射率在波長8〇〇 nrn下為3〇%以 上’上述第3開口部之開口直徑為14〇 μιη以下。 13. 如請求項U之半導體裝置之製造方法，其中上述第2抗 钱劑圖案之底層之表面反射率在波長800 nm下為80%以 上’上述第3開口部之開口直徑為40 μηι以下。 14. 如請求項U之半導體裝置之製造方法，其中上述第2抗 钮劑圖案之底層之表面反射率在波長8〇〇 nm下為98%以 上’上述第3開口部之開口直徑為20 μπι以下。 '丨5.如請求項11之半導體裝置之製造方法，其中上述電極配 . 線部為突出電極。 16.如請求項15之半導體裝置之製造方法，其中上述突出電 極為焊锡球。 17·如請求項11之半導體裝置之製造方法’其中上述電極配 線部為支柱、重佈線或焊墊。 157987.doc 201216432 18. 19. 20. 如請求項11之半導體裝置之製造方法，其係上述底層阻 障金屬膜之下層選自Ti、TiN、TiW、W、Ta、Cr、CoTi 中任一者’且上述金屬膜之上層選自Cu、Al、Pd、Au、 Ag中任一者之積層構造。 如請求項11之半導體裝置之製造方法，其中於上述半導 體基板上形成有積體電路。 如請求項11之半導體裝置之製造方法’其中上述保護獏 為無機絕緣體，利用以稀氫氧酸為藥液之濕式触刻自上 述保護膜之表面除去上述焊墊電極之蝕刻殘渣。 157987.doc
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US10923437B2 (en) 2014-04-14 2021-02-16 Renesas Electronics Corporation Semiconductor device and method of manufacturing the same

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KR101782503B1 (ko) * 2011-05-18 2017-09-28 삼성전자 주식회사 솔더 범프 붕괴를 억제하는 반도체 소자의 범프 형성방법
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US10847408B2 (en) 2019-01-31 2020-11-24 Sandisk Technologies Llc Warpage-compensated bonded structure including a support chip and a three-dimensional memory chip
US11114406B2 (en) * 2019-01-31 2021-09-07 Sandisk Technologies Llc Warpage-compensated bonded structure including a support chip and a three-dimensional memory chip

Family Cites Families (9)

* Cited by examiner, † Cited by third party
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JP4130706B2 (ja) * 1998-02-23 2008-08-06 ソニー株式会社 バンプ製造方法および半導体装置の製造方法
JP3785290B2 (ja) * 1999-06-15 2006-06-14 松下電器産業株式会社 半導体装置およびその製造方法
US20040110365A1 (en) * 2002-12-10 2004-06-10 Taiwan Semiconductor Manufacturing Company Method of forming a planarized bond pad structure
JP2004356129A (ja) * 2003-05-27 2004-12-16 Nichia Chem Ind Ltd 半導体装置及びその製造方法
JP2005175128A (ja) * 2003-12-10 2005-06-30 Fujitsu Ltd 半導体装置及びその製造方法
US8076680B2 (en) * 2005-03-11 2011-12-13 Seoul Semiconductor Co., Ltd. LED package having an array of light emitting cells coupled in series
US7585754B2 (en) * 2008-01-10 2009-09-08 Winbond Electronics Corp. Method of forming bonding pad opening

Cited By (4)

* Cited by examiner, † Cited by third party
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US10923437B2 (en) 2014-04-14 2021-02-16 Renesas Electronics Corporation Semiconductor device and method of manufacturing the same
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US11482498B2 (en) 2014-04-14 2022-10-25 Renesas Electronics Corporation Semiconductor device and method of manufacturing the same
US11810869B2 (en) 2014-04-14 2023-11-07 Renesas Electronics Corporation Semiconductor device and method of manufacturing the same

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