JP2012054366A - 半導体装置および半導体装置の製造方法 - Google Patents

半導体装置および半導体装置の製造方法 Download PDF

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Publication number
JP2012054366A
JP2012054366A JP2010195092A JP2010195092A JP2012054366A JP 2012054366 A JP2012054366 A JP 2012054366A JP 2010195092 A JP2010195092 A JP 2010195092A JP 2010195092 A JP2010195092 A JP 2010195092A JP 2012054366 A JP2012054366 A JP 2012054366A
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Japan
Prior art keywords
film
opening
barrier metal
protective film
pad electrode
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JP2010195092A
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Inventor
Tatsuo Uda
達夫 右田
Hirokazu Ezawa
弘和 江澤
Soichi Yamashita
創一 山下
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Toshiba Corp
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Toshiba Corp
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Priority to JP2010195092A priority Critical patent/JP2012054366A/ja
Priority to TW100128610A priority patent/TW201216432A/zh
Priority to US13/217,746 priority patent/US20120049367A1/en
Priority to CN2011102547048A priority patent/CN102386164A/zh
Publication of JP2012054366A publication Critical patent/JP2012054366A/ja
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Abstract

【課題】半導体チップ上に形成される電極配線部の径のばらつきを低減する。
【解決手段】バリア層７およびハンダ層８、９からなる電極配線部の径が１４０μｍ以下の場合、アンダーバリアメタル膜５の表面反射率が波長８００ｎｍにおいて３０％以上になるようにする。
【選択図】 図４

Description

本発明の実施形態は半導体装置および半導体装置の製造方法に関する。
半導体デバイスの高集積化と高機能化を達成するために、デバイスの動作速度の向上やメモリの大容量化が要求されている。デバイスによっては１チップのｅＤＲＡＭに代えて、ロジック回路と大容量ＤＲＡＭをＣｈｉｐ Ｏｎ Ｃｈｉｐ（ＣｏＣ）接続でパッケージ化したチップも開発されている。
例えば、ロジック回路と大容量ＤＲＡＭをＣｏＣ接続する場合、広帯域の転送速度を達成するには、チップ内の特定のエリアに多数のバンプを形成することが求められる。多数のバンプを形成するためには、バンプピッチおよびバンプ径をできるだけ微細に形成することが要求される。
また、半導体基板上に再配線やバンプ等を形成する際には、フォトリソグラフィー工程によって感光性材料にパターン開口が形成される場合がある。その際に下地の表面状態によっては、光の乱反射等により感光性材料の感光状態が変わってくることがあり、開口形状が歪んだり、開口径がばらついたりすることがある。
開口形状が歪んだり、開口径がばらついたりすると、その開口部分に形成されるバンプの高さがばらつくようになり、ＣｏＣ接続における信頼性の低下の要因となるため、感光性材料の下地の表面状態を適正に管理することが要求される。
特開２００５−３１０９６０号公報
本発明の一つの実施形態の目的は、半導体チップ上に形成される電極配線部の径のばらつきを低減することが可能な半導体装置および半導体装置の製造方法を提供することである。
実施形態の半導体装置によれば、パッド電極と、保護膜と、アンダーバリアメタル膜と、電極配線部とが設けられている。パッド電極は、半導体チップに形成されている。保護膜は、前記パッド電極の表面が露出するようにして前記半導体チップ上に形成されている。アンダーバリアメタル膜は、前記パッド電極および前記保護膜上に形成されている。電極配線部は、前記アンダーバリアメタル膜を介して前記パッド電極上に形成されている。また、前記アンダーバリアメタル膜の表面反射率が波長８００ｎｍにおいて３０％以上、前記電極配線部の径が１４０μｍ以下である。
図１（ａ）〜（ｃ）は、一実施形態に係る半導体装置の製造方法を示す断面図である。 図２（ａ）〜（ｃ）は、一実施形態に係る半導体装置の製造方法を示す断面図である。 図３（ａ）〜（ｃ）は、一実施形態に係る半導体装置の製造方法を示す断面図である。 図４（ａ）〜（ｃ）は、一実施形態に係る半導体装置の製造方法を示す断面図である。 図５は、波長８００ｎｍに対するＴｉ／Ｃｕ膜の反射率とその表面状態との関係を示す図である。 図６は、レジスト膜の下地の反射率とレジスト開口径との関係を示す断面図および表面図である。
以下、実施形態に係る半導体装置および半導体装置の製造方法について図面を参照しながら説明する。なお、これらの実施形態により本発明が限定されるものではない。
図１〜図４は、一実施形態に係る半導体装置の製造方法を示す断面図である。
図１（ａ）において、基材層１上には、パッド電極２が形成されるとともに、パッド電極２が覆われるようにして保護膜３が形成されている。なお、基材層１としては、例えば、ロジック回路またはＤＲＡＭなどの集積回路が形成された半導体基板を用いることができる。また、パッド電極２の材料は、例えば、ＡｌまたはＡｌを主成分とした金属を用いることができる。また、保護膜３の材料は、例えば、シリコン酸化膜またはシリコン酸窒化膜またはシリコン窒化膜などの絶縁体を用いることができる。
そして、フォトリソグラフィー技術を用いることにより、パッド電極２上に開口部４ａを有するレジストパターン４を保護膜３上に形成する。
次に、図１（ｂ）に示すように、レジストパターン４をマスクとして、ＲＩＥなどの異方性エッチングを保護膜３に行うことにより、保護膜３に開口部３ａを形成する。ここで、保護膜３に開口部３ａを形成する際にパッド電極２の表面がエッチングされ、パッド電極２のエッチング残渣２ａが飛散することにより、レジストパターン４の表面にエッチング残渣２ａが付着する。
次に、図１（ｃ）に示すように、アッシングなどの方法により、保護膜３上のレジストパターン４を除去する。ここで、レジストパターン４を除去した際に、エッチング残渣２ａが保護膜３上に残り、保護膜３の表面にエッチング残渣２ａが付着する。
次に、図２（ａ）に示すように、保護膜３の表面をエッチングすることにより、エッチング残渣２ａをリフトオフし、保護膜３の表面からエッチング残渣２ａを除去する。なお、保護膜３の表面のエッチング方法としては、例えば、保護膜３の表面が酸化膜または窒化膜から構成されている場合、希フッ酸を薬液としたウェットエッチングを用いることができる。
次に、図２（ｂ）に示すように、スパッタ、メッキ、ＣＶＤ、ＡＬＤまたは蒸着などの方法を用いることにより、パッド電極２および保護膜３上にアンダーバリアメタル膜５を形成する。なお、アンダーバリアメタル膜５としては、例えば、Ｔｉと、その上のＣｕとの積層構造を用いることができる。なお、Ｔｉの代わりに、ＴｉＮ、ＴｉＷ、Ｗ、Ｔａ、Ｃｒ、Ｃｏ等の材料を使用することもできる。Ｃｕの代わりに、Ａｌ、Ｐｄ、Ａｕ、Ａｇ等の材料を使用することもできる。
ここで、保護膜３の表面のエッチング残渣２ａを除去してから保護膜３上にアンダーバリアメタル膜５を形成することにより、保護膜３の表面のエッチング残渣２ａを除去しない場合に比べて、アンダーバリアメタル膜５の表面粗さを緩和することができ、アンダーバリアメタル膜５の表面反射率を増加させることができる。
次に、図２（ｃ）に示すように、スピンコートなどの方法を用いることにより、アンダーバリアメタル膜５上にレジスト膜６を形成する。なお、レジスト膜６の材料は、ネガ型感光性レジストを用いることができる。
次に、図３（ａ）に示すように、遮光膜１２が形成されたレチクル１１をマスクとしてレジスト膜６の露光を行うことにより、図３（ｂ）の開口部６ａの周囲に配置された潜像６´をレジスト膜６に形成する。
ここで、レジスト膜６の材料がネガ型感光性レジストの場合、開口部６ａでは露光光ＲＩが遮蔽され、開口部６ａの周囲のレジスト膜６に露光光ＲＩが入射される。そして、露光光ＲＩがレジスト膜６を透過し、アンダーバリアメタル膜５の表面に達すると、アンダーバリアメタル膜５の表面粗さに応じて露光光ＲＩが乱反射し、開口部６ａとして除去されるレジスト膜６の部分に乱反射光ＲＦが入射する。
次に、図３（ｂ）に示すように、レジスト膜６の現像を行うことにより、パッド電極２上に配置された開口部６ａをレジスト膜６に形成する。なお、開口部６ａの開口径が１４０μｍ以下の場合、レジスト膜６の下地の表面反射率が波長８００ｎｍにおいて８０％以上であることが好ましい。
また、開口部６ａの開口径が４０μｍ以下の場合、レジスト膜６の下地の表面反射率が波長８００ｎｍにおいて９０％以上であることが好ましい。また、開口部６ａの開口径が２０μｍ以下の場合、レジスト膜６の下地の表面反射率が波長８００ｎｍにおいて９８％以上であることが好ましい。
ここで、図３（ａ）の工程において、開口部６ａとして除去されるレジスト膜６の部分に乱反射光ＲＦが入射すると、その部分にも潜像６´が形成され、開口部６ａの径が小さくなることから、開口部６ａの径にバラツキが発生する。
この時、アンダーバリアメタル膜５を保護膜３上に形成する前に、保護膜３の表面のエッチング残渣２ａを除去することにより、レジスト膜６の下地の表面反射率を増大させることができる。このため、レジスト膜６を透過した露光光ＲＩがレジスト膜６の下地にて乱反射されるのを低減することができ、開口部６ａとして除去されるレジスト膜６の部分に乱反射光ＲＦが入射するのを低減させることができる。この結果、開口部６ａの径が小さくなるのを抑制することができ、開口部６ａの径のバラツキを低減することができる。
ここで、開口部６ａの開口径が１４０μｍ以下の場合、レジスト膜６の下地の表面反射率が波長８００ｎｍにおいて８０％以上としたのは、表面反射率が８０％より小さくなると、保護膜３の表面に残ったエッチング残渣２ａの量が多くなり、開口部６ａの径のバラツキの影響が大きくなるからである。
また、開口部６ａの開口径が小さくなると、表面反射率が大きくなるようにしたのは、開口部６ａの径のバラツキが開口部６ａに埋め込まれる突出電極の高さのバラツキに与える影響が大きくなるからである。
次に、図３（ｃ）に示すように、電解メッキにてバリア層７およびハンダ層８、９を開口部６ａに順次埋め込むことにより、アンダーバリアメタル膜５を介してパッド電極２上に突出電極を形成する。なお、例えば、バリア層７の材料はＮｉ、ハンダ層８の材料はＣｕ、ハンダ層９の材料はＳｎを用いることができる。
次に、図４（ａ）に示すように、アッシングなどの方法により、アンダーバリアメタル膜５上のレジスト膜６を除去する。
次に、図４（ｂ）に示すように、バリア層７およびハンダ層８、９からなる突出電極をマスクとして、アンダーバリアメタル膜５をエッチングすることにより、バリア層７およびハンダ層８、９からなる突出電極の周囲のアンダーバリアメタル膜５を除去する。
次に、図４（ｃ）に示すように、ハンダ層８、９をリフローすることにより、ハンダ層８、９を合金化し、バリア層７上に合金ハンダ層１０を形成する。
以上の工程は基材層１がウェハの状態で行うことができる。そして、以上の工程の後、このウェハを個片化することより、半導体チップを切り出すことができる。
ここで、開口部６ａの径のバラツキを低減することにより、開口部６ａに順次埋め込まれるバリア層７およびハンダ層８、９の量が開口部６ａの径に寄らずに一定に保たれる場合においても、バリア層７およびハンダ層８、９からなる突出電極に高さのバラツキを低減することができ、ＣｏＣ接続における信頼性を向上させることができる。
この時、バリア層７およびハンダ層８、９からなる突出電極の径が１４０μｍ以下の場合、アンダーバリアメタル膜５の表面反射率が波長８００ｎｍにおいて８０％以上であることが好ましい。また、バリア層７およびハンダ層８、９からなる突出電極の径が４０μｍ以下の場合、アンダーバリアメタル膜５の表面反射率が波長８００ｎｍにおいて９０％以上であることが好ましい。また、バリア層７およびハンダ層８、９からなる突出電極の径が２０μｍ以下の場合、アンダーバリアメタル膜５の表面反射率が波長８００ｎｍにおいて９８％以上であることが好ましい。
なお、上述した実施形態では、突出電極としてハンダボールを用いる方法について説明したが、ニッケルバンプ、金バンプまたは銅バンプなどを用いるようにしてもよい。また、上述した実施形態では、アンダーバリアメタル膜５として、ＴｉとＣｕとの積層構造を用いる方法について説明したが、ＴｉまたはＣｕを単体で用いるようにしてもよいし、Ｃｒ、Ｐｔ、Ｗなどを単体として用いるようにしてもよし、これらの金属の積層構造を用いるようにしてもよい。
また、ＣｏＣ接続における突出電極の接合方法としては、半田接合や合金接合などの金属接合を用いるようにしてもよいし、ＡＣＦ（Ａｎｉｓｏｔｒｏｐｉｃ Ｃｏｎｄｕｃｔｉｖｅ Ｆｉｌｍ）接合、ＮＣＦ（Ｎｏｎｃｏｎｄｕｃｔｉｖｅ Ｆｉｌｍ）接合、ＡＣＰ（Ａｎｉｓｏｔｒｏｐｉｃ Ｃｏｎｄｕｃｔｉｖｅ Ｐａｓｔｅ）接合、ＮＣＰ（Ｎｏｎｃｏｎｄｕｃｔｉｖｅ Ｐａｓｔｅ）接合などを用いるようにしてもよい。
図５は、波長８００ｎｍに対するＴｉ／Ｃｕ膜の反射率とその表面状態との関係を示す図である。
図５において、エッチング残渣２ａのない時のレジスト膜６の下地のサンプルＷ１として、ベアのＳｉ基板上にＴｉ／Ｃｕ膜（膜厚２００／３００μｍ）をスパッタにて形成したものを用いた。このサンプルＷ１の表面反射率は波長８００ｎｍにおいて９８．３％だった。
次に、エッチング残渣２ａのある時のレジスト膜６の下地のサンプルＷ３として、図１（ｂ）および図１（ｃ）の工程にて得られたサンプル上にＴｉ／Ｃｕ膜（膜厚２００／３００μｍ）をスパッタにて形成したものを用いた。なお、このサンプルＷ３では、保護膜３としてシリコン窒化膜を用いた。また、このサンプルＷ３では、エッチング残渣２ａが保護膜３上に付着し、Ｔｉ／Ｃｕ膜の表面が荒れているのが確認できた。このサンプルＷ３の表面反射率は波長８００ｎｍにおいて３０．９％だった。
なお、サンプルＷ１、Ｗ３の表面反射率の測定は、反射率分光膜厚計ＦＥ−３０００（大塚電子製）を用いた。
このように、Ｔｉ／Ｃｕ膜下のエッチング残渣２ａの有無と、Ｔｉ／Ｃｕ膜の表面反射率との間には相関があり、Ｔｉ／Ｃｕ膜下のエッチング残渣２ａが増大するに従ってＴｉ／Ｃｕ膜の表面反射率が低下する。このため、Ｔｉ／Ｃｕ膜の表面反射率を計測することにより、Ｔｉ／Ｃｕ膜下のエッチング残渣２ａの量を評価することができ、Ｔｉ／Ｃｕ膜上に形成されるレジスト開口部の径のバラツキを見積もることができる。
図６は、レジスト膜の下地の反射率とレジスト開口径との関係を示す断面図および表面図である。
図６において、レジスト膜の下地として、波長８００ｎｍでの表面反射率が９８％、７８％、２７％のサンプルを用意した。なお、レジストの下地の表面反射率を変化させるために、レジスト膜の下地の表面粗さを変化させた。
そして、これらの下地上にスピンコートにてレジスト膜を塗布し、同一の露光条件および同一の現像条件でこれらのレジスト膜に開口部を形成した。そして、これらのレジスト膜に形成された開口部の上面形状および断面形状を電子走査顕微鏡で観察した。
この結果、表面反射率が９８％のサンプルでは開口径が２１．０μｍ、表面反射率が７８％のサンプルでは開口径が１９．８μｍ、表面反射率が２７％のサンプルでは開口径が１７．６μｍとなり、表面反射率が低下するに従って開口径が小さくなることが確認できた。
なお、上述した実施形態では、開口部６ａの径のバラツキを低減するためのレジスト膜６の下地の表面状態を、レジスト膜６の下地の表面反射率にて規定する方法について説明したが、レジスト膜６の下地の表面反射率を表面粗さに換算した値を用いるようにしてもよい。
また、上述した実施形態では、電極配線部として突出電極を用いた場合を例にとって説明したが、電極配線部としてピラー、再配線またはパッドなどを用いるようにしてもよい。
本発明のいくつかの実施形態を説明したが、これらの実施形態は、例として提示したものであり、発明の範囲を限定することは意図していない。これら新規な実施形態は、その他の様々な形態で実施されることが可能であり、発明の要旨を逸脱しない範囲で、種々の省略、置き換え、変更を行うことができる。これら実施形態やその変形は、発明の範囲や要旨に含まれるとともに、特許請求の範囲に記載された発明とその均等の範囲に含まれる。
１ 基材層、２ パッド電極、２ａ エッチング残渣、３ 保護膜、３ａ、４ａ 開口部、４ レジストパターン、５ アンダーバリアメタル膜、６ レジスト膜、６ａ 開口部、７ バリア層、８、９ ハンダ層、１０ 合金ハンダ層

Claims (5)

  1. 半導体チップに形成されたパッド電極と、
    前記パッド電極の表面が露出するようにして前記半導体チップ上に形成された保護膜と、
    前記パッド電極および前記保護膜上に形成されたアンダーバリアメタル膜と、
    前記アンダーバリアメタル膜を介して前記パッド電極上に形成された電極配線部とを備え、
    前記アンダーバリアメタル膜の表面反射率が波長８００ｎｍにおいて３０％以上、前記電極配線部の径が１４０μｍ以下であることを特徴とする半導体装置。
  2. 前記アンダーバリアメタル膜の表面反射率が波長８００ｎｍにおいて８０％以上、前記電極配線部の径が４０μｍ以下であることを特徴とする請求項１に記載の半導体装置。
  3. 半導体基板上にパッド電極を形成する工程と、
    前記パッド電極が覆われるようにして前記半導体基板上に保護膜を形成する工程と、
    前記パッド電極上に第１の開口部を有する第１のレジストパターンを前記保護膜上に形成する工程と、
    前記第１のレジストパターンをマスクとして前記保護膜をエッチングすることにより、前記パッド電極を露出させる第２の開口部を前記保護膜に形成する工程と、
    前記第２の開口部が形成された前記保護膜上の前記第１のレジストパターンを除去する工程と、
    前記保護膜の表面をエッチングすることにより、前記パッド電極のエッチング残渣を前記保護膜の表面から除去する工程と、
    前記パッド電極上および前記パッド電極のエッチング残渣が表面から除去された保護膜上にアンダーバリアメタル膜を形成する工程と、
    前記パッド電極上に第３の開口部を有する第２のレジストパターンを前記アンダーバリアメタル膜上に形成する工程と、
    前記第３の開口部に埋め込まれた電極配線部を前記アンダーバリアメタル膜上に形成する工程と、
    前記電極配線部が形成された前記アンダーバリアメタル膜上の前記第２のレジストパターンを除去する工程と、
    前記電極配線部をマスクとして前記アンダーバリアメタル膜をエッチングすることにより、前記電極配線部の周囲の前記アンダーバリアメタル膜を除去する工程とを備えることを特徴とする半導体装置の製造方法。
  4. 前記第２のレジストパターンの下地の表面反射率が波長８００ｎｍにおいて３０％以上、前記第３の開口部の開口径が１４０μｍ以下であることを特徴とする請求項３に記載の半導体装置の製造方法。
  5. 前記第２のレジストパターンの下地の表面反射率が波長８００ｎｍにおいて８０％以上、前記第３の開口部の開口径が４０μｍ以下であることを特徴とする請求項４に記載の半導体装置の製造方法。
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