TW201207967A - Method of forming an integrated circuit device - Google Patents

Method of forming an integrated circuit device Download PDF

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Publication number
TW201207967A
TW201207967A TW099141650A TW99141650A TW201207967A TW 201207967 A TW201207967 A TW 201207967A TW 099141650 A TW099141650 A TW 099141650A TW 99141650 A TW99141650 A TW 99141650A TW 201207967 A TW201207967 A TW 201207967A
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TW
Taiwan
Prior art keywords
opening
layer
photoresist film
photoresist
forming
Prior art date
Application number
TW099141650A
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English (en)
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TWI423357B (zh
Inventor
Chen-Cheng Kuo
Chen-Shien Chen
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Taiwan Semiconductor Mfg
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Publication of TW201207967A publication Critical patent/TW201207967A/zh
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Publication of TWI423357B publication Critical patent/TWI423357B/zh

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

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201207967 六、發明說明： 【發明所屬之技術領域】 本發明係關於一種製造積體電路元件的方法，更特 別關於一種製造半導體積體電路中凸塊結構的方法。 【先前技術】 現有的積體電路係由橫向排列之百萬個主動元件如 電晶體及電容所組成。這些元件在初步製程中彼此絕 # 緣，但在後段製程中將以内連線連接元件以形成功能電 路。一般的内連線結構包含橫向内連線如金屬線路，與 垂直内連線如通孔與接點。現有的積體電路其效能與密 度的上限取決於内連線。在内連線結構的頂部上方了每 一晶片表面上各自有對應的接合墊。經由接合墊，晶片 可電性連接至封裝基板或其他晶粒。接合墊可應用^打 線接合或覆晶接合。在覆晶封裝中，凸塊可在封裝結構 的導線架或基板，與晶片的輸出/輸入墊之間形成電性接 鲁觸。上述凸塊結構除了凸塊本身，還具有凸塊與輸出/輸 入墊之間的凸塊下冶金層（UBM) ^ UBM通常含有黏著 層、阻p早層、與潤濕層依序形成於輸入/輸出墊上。凸塊 的刀類可依材質分為焊料凸塊、金凸塊、銅柱凸塊、或 混合金屬凸塊。近來發展的銅柱凸塊技術中，採用銅柱 凸塊而非焊料凸塊將電子構件連接至基板。銅柱凸塊的 2距較小，其短路橋接的可能性較低，可降低電路的電 谷負載並提高電子構件的操作頻率。 在才木用銅柱的完全覆晶封裝中，+論是測試或組裝 0503-A35493TWF/hsuhuche 201207967 後使用均發現熱應力問題如超低介電常數(ELK)之介電 材料的分層，或底填材料、保護層、及預焊材料的碎裂。 上述材料分層會碎裂的原因為銅柱周圍的上述材料，在 熱循時會產生實質上的熱應力。當積體電路元件的尺 寸持續縮減’終端與銅柱之間的間距亦隨之縮減。如此 -來’採用銅柱的相關熱應力問題必然增加。在習知採 用銅柱的積體電路覆晶封裝中，先以單—光阻層如乾膜 或濕膜搭配微影製程在UB M層上定義一開口，再以電鑛 法沉積銅層以形成具有垂直侧壁或傾斜側壁之銅柱。然 習知方法難以增加銅柱的底部尺寸，且無法將應力 /刀攤至UBM層與保護層之間的界面。綜上所述，目前虽 =種改良的積體電路覆晶連線如銅柱以解決熱應力的 問喊。 【發明内容】 明-實施例提供一種積體電路元件的形成方 社構成凸塊下冶金層於半導體基板上；形成光阻 :構於凸塊下冶金層上，其中光 與位於第-光阻膜上的第二光阻臈，且第丄= 敏性不g於第二光阻膜之光敏性；形、 中以露出部份的凸塊下冶金層，其中開：包括二： 位=第—緣膜中及第二開口位於第二光阻】 層於光阻結構之開口中，且導電 j導電 ”凸鬼下^層；以及移除光⑽構，其中導電層形成 0503-A35493TWF/hsiJhuche 4 201207967 導電柱。 不赞明又一 -貫她例提供一種積體電路元件 法’包括形成凸塊下冶金層 ：件的形成方 光阻臈於凸塊下冶金層上 m’形成第- 第一光敏性.1 光阻膜具有第一厚度與 職⑨’形成第—光阻膜於第―光 。 光阻膜具有第二厚度與第、 第二 於篦一忠紐敏性，其中第二光敏性* 第7^敏性’且第二厚度大於第-厚大 程至第二光阻膜與第—光阻膜 仃曝光製
光阻膜以形成第一開口；移除未光:部份第二 以露出部份凸塊下；Λ + Μ '、 +先的°Η”第—光阻膜 Η刀凸塊下/ 口金層’形成第二開口於 下’以及形成第三開口於第二開 圍繞第二開σ，且Μ π π + 八甲第—光阻膜 頂邱亩" 1之底部直徑大於第二開口之 =直徑；形成銅層於第一開口、第二開口、與= :電性連接至露出的部份凸塊下冶金層；以二 2阻軸第—光_，其中_形成練。 法，===提供一種積體電路元件的形成方 光阻==二層於半導體基板上;形成第- f 一光敏性；形成第二光阻膜於第-光阻膜上，曰f:、 於筮, 第一先破性；其中第—光斂性大 於第m且第二厚度切第—厚度 私至第二光阻膜與第一光 订+光1 阻膜以m „尤阻膜，移除曝光的部份第二光 膜Μ成第-開口；移除曝光的部 出部份凸塊下冶金層，形成第二開口於第一開η 及形成第三開口於第二開： ' 并宁第一先阻膜圍繞第 〇5〇3^A35493TWF/hsuhuche 5 201207967 :開口 ’且第二開口之底部直徑大於第二開口之頂部直 電性連接至霞中沾立 第二開口、與第三開口中以 阻膜與第-光阻膜，其中銅層形成鋼柱。先 【實施方式】 用於揭露形成銅柱的方法，其基腳形狀可應 曰圓等級的晶片尺寸封裝(WLCPS)、三 及/或任何進階的封裝技術領域。圖示 說明實施例。圖示及對應說明盡可能採用 厚目同或類似的部份。圖示中結構的形狀及 =可此會誇大以突顯結構特點。下列說明將直接針對 二的，成要素或操作要素。可以理解的是本技藝人 告:自仃㈣或變化未特別顯示或敘述的要素。此外， 虽某層被在另-層上時，指的可能是直接位於另一層上 或兩者間隔有其他層。 =下述說明中，「―實施例」指的是特定特徵、結 、’至少-實施例中包含的實施例所連結的結構。因 此’不同段落中的「一實施例」指的不一定是同一實施 例。此外，-或多個實施财的特定特徵、結構、 點可由任何合適態樣組合。可以理解的是，下述圖示並 非依比例繪示，僅用以方便說明而已。 、’ 第1八至1G圖係本發明一實施例中，採用負光阻形 成積體電路中銅柱的製程剖視圖。如第丨圖所示，半導 體基板10可用以形成凸塊以製備積體電路元件，且積 〇503^A35493TWF/hsuhuch, 6 201207967 電路可形成於半導體基板’10中及/或其上。半導體基板 10的定義為半導體材料，包括但不限定於基體矽、半導 體晶圓、絕緣層上矽（SOI)基板、或矽鍺基板。其他適用 於半導體基板10之半導體材料可採用ΠΙ族、IV族、或 v知元素。半導體基板丨〇可更包含複數個絕緣結構（未圖 示），如淺溝槽絕緣（STI)結構或區域氧化石夕（L〇c〇s)結 構。絕緣結構可絕緣複數個微電子元件（未圖示）。上述形 成於半導體基板10中的微電子元件可為金氧半場效電晶 體（MOSFET)、互補式金氧半（CM〇s)電晶體、雙極性接 面電晶體（BJT)、高電壓電晶體、高頻電晶體、p通道及/ 或η通道場效電晶體、或其他電晶體，電阻，二極體， 電容，電感，炼、絲，或其他合適元件。不同的微電子元 件的形成方法可包含不同製程如沉積、蝕刻、佈植、微 影、回火、或他合適製程。微電子㈣可藉由内連線形 成積體電路7L件如邏輯元件、記憶元件（例如靜態隨機存 取記憶體，SRAM)、射頻（RF)元件、輸入/輸出（1 =7系統（S〇C)元件、上述之組合、或其他合適型態的 積體Ϊ =具有層間介電層與金屬結構形成於 、未掺雜之石夕酸鹽玻璃=介電常數之介電材料、 /夂疏圾別USG)、虱化矽、氮氧化矽 一般㊉用材料。低介電常數 -八他 小於約3.9,或小於約28„材料其介電常_可 銅或:合金組成。金屬結構與層間介 本技藝人士所熟知，在此不贅述。 ㈣成方法為 0503^A35493TWF/hsuhuch, 7 201207967 、，電區12為形成於最頂層之層間介電層 ·
二C導電線路的一部份，其露出的表面可視 二/订平坦化製程如化學機械研磨（C ;12•的材料可為但不限定於銅♦銅合金、 的導電材料。在某些實施例中，導電區12作為墊區以 it接it二可將每一晶片中的積體電路連接至外部 :仵1内:車：貫施例中，導電區12為再佈線層，亦稱為 後保濩内連線(ppj)線路。 保護層14係形成於半導體基板1〇上。圖案化保 層14可形成開口露出部份的導電區12,以利後續製程形 成凸塊。在某些實施例中’保護層14之組成可為未掺雜 石夕酸鹽玻璃（USG)、氮化石夕、氮氧化咬、氧化石夕、或上述 之^合。在某些實施例中，保護層14之組成為高分子層 如環氧樹脂、聚亞醯胺、雙苯並環丁烧(BCB)、聚苯并噁 嗤(PBO)、或其他較軟的有機介電材料。 尚分子層16係形成於保護層14上。圖案化高分子 層16可形成開口露出部份的導電區12，以利後續製程 成凸塊。高分子層16中的開π可小於、等於、或大於保 4層14中的開口。在某些實施例中，高分子層16之組 成為高分子如環氧樹脂\聚亞醯胺、雙苯並環丁烷 (BCB)、聚苯并^坐(ρΒ0)、或其他較軟的有機介電材料。 在某些實施例中，高分子層16為聚亞醯胺層。在某些實 施例中，高分子層16為聚笨并噁唑(ρΒ〇)層。 第1Α圖亦顯示凸塊下冶金18形成於半導 體基板10上。UBM層18係形成於導電區12的露出部 〇503^A35493TWF/hsuhuche 8 201207967 9
声16 伸至问刀子層16上。在某些實施例中，UBM 層b包含作為擴散阻障層或黏著層的第—層，其組成可 ^勿二氮化鈦、氮化組、或類似物，且其形成方： ^ H 或韻法。第—層之沉積厚度 於約人5〇〇A至2000A之間。在某些實施例中，麵層 1二？為晶種層的第二層，其組成可為銅或銅合金， 於ΐ ^方法可為PVD或濺鍍法。第二層之沉積厚度介 於約500A至10000A之間。 如第1B圖所示，光阻結構2〇係形成於仙撾層18 二光=結構2〇為堆疊結構’包含至少兩層不同光敏性 Ϊ阻膜。母—光阻膜可為正光阻膜或負光阻膜，取決 阻膜在曝糾的化學變化性。若纽膜在曝光 I、有較佳的化學穩定性’則此光阻膜為負光阻膜。若 $用負光阻’則未曝光之負光阻部份將被顯影移除。若 曝：後具有較差的化學穩定性，則此光阻膜為 馬移^ 光阻’則曝光之正光阻部份將被顯 〜移除。在一實施例中，光阻結構20包含第-光阻膜22, 22上的第二光阻膜24°第一光阻膜 24 Α备ί阻’具有第一光敏性及第一厚度。第二光阻膜 比第-本了 ’具有第二光敏性及第二厚度。第二光敏性.. 笛一性大，且第一厚度小於第二厚度。舉例來說， ::阻膜22之第一厚度約介於3_至15,之間，而 光阻膜24之第二厚度約介於40μιη至85μηι之間。 :著如第1C圖所示’進行單一曝光製程以圖案化光 、“冓20’其曝光光源可為深紫外線(鬧、中紫外線 05O3-A35493TWF/hsuhuch( 9 9 201207967
(MUV)、或χ光射線。在其他實施例中’光阻結構之 曝光源為電子束微影的能量化電子。搭配光罩26，光子 或電子能量可使光阻結構2〇的曝光部份之組成產生化學 變化，例如交聯、斷鏈、或移除支鏈等等。光阻可進= 預烘烤或後㈣製程，這將最大化光阻巾曝光部份與未 曝光部份之間的化學性質變化差異。由於第一光阻膜U 與第二光阻膜24為負光阻，光阻結構2〇其未曝光的部 份將被顯影移除以露出部份的UBM層丨8。 上述微影製程將形成開口 2〇a於光阻結構2〇中。開 口 20a包含藉由移除未曝光的第一光阻膜22所形成的第 一開口 22a，以及藉由移除未曝光的第二光阻膜24所形 成的第二開口 24a。第二開口 24a具有實質上垂直的側壁 2^。在第一開口 22&中，更包含被UBM層18露出的部 份所包圍之較低部份2 2 a 1，以及被第一光阻膜2 2保留的 部份所包圍的較高部份22as。總體來說，較高部份22a2 、底。卩直徑Dlb大於頂部直徑Dlt，且第一電阻膜22保留 的部份其傾斜的側壁表面22s與1；3河層18之夾角㊀小'於 〇度如此一來，鳥嘴開口 22b將形成於第一光阻膜22 ^⑽熥層18的界面之間。此外，第一開口 &其較高 邛伤22a2的底部直徑比第二開口 24a的直徑寬。在某 些實施例中，直徑D〗b與直徑A的差距大於約3μιη。在 後續製程中’導電材料將填人開口中，即完成具有基聊 形狀的導電柱。 如第1D圖所示，將具有焊料潤濕性的導電材料形成 於開口 22a及24a _。在某些實施例令，係將銅層28填 〇503-A35493TWF/hsuhuche m 201207967 入第一開22a以接觸其下的1；]8]^層18。沉積“層28的 作法可連續性地將其填入第二開口 24a直到預定的高 度。在本揭露中’所謂的銅層實質上包含純元素銅、含 有無可避免之雜質的銅、或次要成份為鈕、銦、錫、鋅、 錳、鉻、鈦、鍺、鋰、鉑、鎂、鋁、或锆的銅合金。銅 層28#的形成方法可為濺鑛、印刷、電鑛、無電電鑛、或 化予氣相/儿積法（CVD)。舉例來說，電化學電鍵法（Ecp) 可用以形成銅層28。在某些實施例中，Ecp製程之起始 =積速率較慢以達到「填隙」效果，這可幫助電鐘銅層 ΤΤ'Τ^Δ嘴開口 22b ’進而使銅層28之基腳形狀能貼近 曰18 °在一實施例十，鋼層28之高度H]定義為最 :表面至最高表面的距離，可大㈣叫。在某些實施例 一銅層28之回度％大於4〇卿。舉例來說，銅層π =度印介於約40μηι至5〇卿之間，或介於扣㈣至 70μιη之間，但銅層28之古洚u , 之间度Η!可大於或小於上述範 =某：實施例中’第二開口叫實質上填入銅層28, f 之上表面低於第二光阻膜24的上表面。在其 =貫施例中（未圖示），可控制銅層的沉積製程以將其填入 開口 24a ’並使銅層的上表古 、 24的上表面。 表面阿於或專南於第二光阻膜 ·、 接著如第1E圖所示，蓋屛如ή m笛-μ 〇… 層與焊料層32係成功地 开y成於第一開口 24a中的銅層μ 施例中，蓋層30可作為擴散阻^上^上。在某些實 擴散至接合材料如焊料心丄章过層接^避免鋼柱中的銅 主道舻其妃…广金上边接合材料係用以接合 丰導體基板1〇至外部結構。避免銅擴散可增加封裝的接 0503^A35493T\VF/hsuhuche 201207967 =可包含下列材料中至少-者:錄、 材料或、繼、鎳金、其他類似 至H)Um ^ 合金。蓋層3〇之厚度約介於_ 甘間0在某些實施例中，蓋層30為多声姓構， :::::層包含下列材料中至少-者.d 例中，i声3、〇tt主合金、或纪為主合金。在某些實施 電聲製程\ ^ 録合金膜，其形成方法可為電極 電鍍，無電電鍍製程、或含浸電鍍製程。 ㈣ί料層32可為踢、錫銀、錫錯、銅之重量％小於0.3% 且' 銅、錫銀鋅、錫鋅、錫鉍銦、錫銦、锡金、錫妒、 铲：：錫鋅銦、錫銀錫、或類似物，其形成方法可為電 二=Ϊ實焊料:。在 :。在某些實施例中，無船焊料層為:：的 重量％的锡銀。 3篁小於2.5 接著如第1F圖所示，移除光阻結構2() =i°cT圖層所2_8形成^。接著移除露出的職層18。 第1G圖所不，以銅柱（銅層28)作為遮罩， 的部份11刪層18並露出其下方的高分子層16。示路出 如IMG圖所示，完成的凸塊結構包含圖0案 18”、_ 28、蓋層30、與焊料層32。鋼層μ 口面為柱狀的上層部份28a、剖面為梯形的ς有 二、以及被圖案化麵層18，，包圍的底層部。 層錢28a具有寬度W,及垂直側壁心。。上 具有頂寬w2、底寬w3、及傾斜側壁28 a = 28b 甲間部份28b °5〇3-A35493TWF/hsuhuche ,2 201207967
的底寬W3大於頂寬W2,且底寬W3亦大於上層部份28a 的寬度I。上層部份28a之寬度W1實質上可等同於中 間部份28b之底寬w2。在某些實施例中，中間部份挪 的底寬W3比頂寬W2大了約3μπι。侧壁28s自較寬的上 部朝較窄的下部傾斜直到接觸圖案化^^^撾層18”，兩者 之炎角小於90度。上述傾斜的側壁28s使柱狀結構其垂 直的侧壁28v底部具有基腳形狀。此外，銅層28覆蓋圖 案化UBM層18”的部份較寬，可保留較多的ubm材料 不致被移除。在複雜的積體電路構件中，上述實施例中 的銅柱中不同材料如ELK、UBM、底填材料、預焊料、 或焊料凸塊上的熱應力’低於習知技藝中 中上述材料上的熱應力。 钔柱 接著進行再流動製程以形成再流動的焊料層。接著 切割半導體基板10，再以焊球絲凸塊將其固定於封裝 基板或另一晶粒上的墊層上，至此完成封裝結構。' 、 上述方法之微影製程中，形成不同光敏性之負光阻 膜的堆疊結構於UBM層上。在較低光賴巾可形成鳥嘴 開口 ’这將使後續形成的銅柱具有基腳形狀。此方法 不需額外化學或電聚製程的情況下，即可輕易定義基腳 形狀的尺寸，這將大幅節省製造成本。^義基腳 第2A-2D圖係本發明一實施例中，採用正光阻形成 體電路中銅柱的製程剖視圖。下述說明將省略與第 1A-1G圖類似或相同的部份。 ” 如第2A圖所不，形成先阻結構40於UBM層18上。 光阻結構40為堆疊紐椹 库且、、、D構，包含至少兩層不同光敏性的光 〇503^A35493TWF/hsuhuche 13 201207967 阻膜。在一實施例中，光阻結構4〇包 與位於第-光阻膜42上的第二光阻膜二 42為正光阻，具有第—光敏性及第-厚度。第二光阻膜 44為正負光阻，具有第^ 、 =第二：大，且第一厚度小於第= =第-先阻膜42之第一厚度約介於3_ ， 而第二ΐ阻膜44之第二厚度約介於卿爪至85_之間。 接者如第2Β圖所示，進行單一曝光製程以圖案化 其曝光光源可為DUV、瞻、或乂光射線。 ^曰、他=_中，光阻結構4Q之曝絲為電子束微影的 Μ化電子。搭配光罩36，光子或電子能#可 :40的曝光部份之组成產生化學變化，例如交聯、斷鏈: 2除支鏈等等。光阻可進行㈣烤或後供烤製程，這 =大化光阻中曝光部份與未曝光部份之間的化學性質 變化差異。由於第-光阻膜42與第二光阻膜44為正光 阻光阻結構40其曝光的部份將被顯影移除。 上述微办製知將形成開口 4〇a於光阻結構中。開 口恤包含藉由移除曝光的第-光阻膜42所形成的第一 開:42a，以及藉由移除曝光的第二光阻膜料所形成的 第一開44a。在第一開口仏中更包含被仙河層 露出的部份所包圍之較低部份你，以及被第一光阻膜 ^保留的部份所包圍的較高部份42a2。總體來說，較高 礼42a2中’第—電阻膜42保留的部份其傾斜的側壁表 面42s與UBJV[層18之夾角θ小於9〇度。如此一來，鳥嘴 開口 42b將形成於第一光阻膜42與ubm層18的界面之 〇503-A35493TWF/hsuhuche 201207967 間。此外，第一開口 42a其較高部份42a2的底部直徑Dib 比第二開π 44a的直徑D2寬。在後續製程中，導電材料 將填入開口中，即完成具有基腳形狀的導電柱。 ^如第2C圖所示，將銅層28填入開口 42a及44a中 後’接著形成蓋層30與焊料層32。在某些實施例中，Ecp 製程之起始沉積速率較慢以達到「填隙」效果，這可幫 助電鑛銅層填人鳥嘴開π 42b，進而使銅層28之基腳形 狀能貼近UBM層18。
接著如第2D圖所示，移除光阻結構40以露出UBM 層18。意1；腿層18突出的銅層28即銅柱。接著钱刻 移除露出的UBM層18，露出其下方的高分子層16。之 f進仃再流動製程以形成再流動的焊料 ”基板1〇’再以焊球或銅凸塊將其固定於封;基= 另m的㈣上’至此完成封裝結構。 上述方法之微影製程中，形成不同光敏性之正光阻 膜的堆疊結構於UBM声f*。y· h , 門口 / M層上。在較低光阻臈中可形成鳥嘴 歼不k將使後續形成的銅柱具有基腳形狀。此方法在 不需額外化學或雷难制& ㈣的㈠ 的情況下，即可輕易定義基腳 祕的尺寸，這將大幅節省製造成本。 非用明已以數個較佳實施例齊露如上，然其並 非用以限定本發明，任何 卫 明之精神和範圍内4;;;=技=在不脫離本發 發明之保護範圍當視;:任：之，更動與调飾，因此本 準。 固田視後附之令請專利範圍所界定者為 0503-A35493T\VF/hsuhuche 201207967 【圖式簡單說明】 第1A至ig圖係本發明一實施例中，採用負光阻形 成積體電路中銅柱的製程剖視圖；以及 第2A-2D圖係本發明一實施例中，採用正光阻形成 積體電路中銅柱的製程剖視圖。 【主要元件符號說明】 Θ〜保留的第一電阻膜侧壁與凸塊下冶金層之間的夾 角，
Dlb〜第一開口其較高部份之底部直徑； D丨广第一開口其較高部份之頂部直徑； D2〜第二開口的直徑； H〗〜銅層高度；
Wi〜銅層之上層部份的寬度； W2〜銅層之中間部份的頂寬，· W3〜銅層之_間部份的底寬； 10〜半導體基板； 12〜導電區，· 14〜保護層； 16〜南分子層； 18〜凸塊下冶金層； ' 18”〜圖案化的凸塊下冶金層； 20、40〜光阻結構； 20a、40a〜開口 ； 22、42〜第一光阻膜； 0503^A35493TWF/hsuhuche 16 201207967 22a、42a〜第一 開口； 22a〗、42a丨〜第一開口之較低部份； 22a2、42a2〜第一開口之較高部份； 22b、42b〜鳥嘴開口； 22s〜保留的第一電阻膜側壁表面； 24、44〜第二光阻膜； 24a、44a〜第二開口； 24s、44s〜第二開口的側壁； 26、36〜光罩； 28〜銅層； 28a〜銅層的上層部份； 28b〜銅層的中間部份； 28c〜銅層的底層部份； 2 8 s〜銅層之中間部份的側壁； 2 8v〜銅層之上層部份的側壁； 30〜蓋層； 32〜焊料層。 0503^A35493TWF/hsuhuche 17

Claims (1)

  1. 201207967 七、申請專利範圍： 1. -種積體電路元件的形成方法，包括. 形成一凸塊下冶金層於一半導體基板上. 形成-光阻結構於該凸塊下冶金層上，盆中 :構包括一第一光阻膜與位於該第-光阻膜：的：第一 之光敏性； 膜之先破性不同於該第二光阻膜 =成=口於該光阻結構中以露出部份的該 中及一第二開口位於二：：位於該第，膜 产如士Λ乐一九阻膜中，且該第一開口之 氐。Ρ直徑大於該第一開口之頂部直徑； 形成一導電層於該光阻結構之該開口巾，且 層電性連接至露出的部份該凸塊下冶金層；以及μ 移除該光阻結構，其中該導電層形成一導電柱。 2·如申4專利$(L圍第丨項所述之㈣電路元件的形 其中該第—光阻膜與該第二光阻膜之組成為負 之：姑料’且該第二光阻臈之光敏性大於該第-光阻膜 之光敏性。 3·如中請專利範圍第丨項所述之龍電路元件的形 ^方法’其中該第—光，與該第二光阻膜之組成為正 、，阻材料’且該第一光阻膜之光敏性大於該第二光阻膜 之光敏性。 、4.如申5月專利範圍第1_項所述之積體電路元件的形 成方法中該第—光阻膜比該第二光阻膜厚，且該第 二開口之直徑小於該第—開口之底部直徑。 0503^A35493TWF/hsuhuche 201207967 、、如申明專利範圍第1項所述之積體電路元件的形 =法’更包括在移除該光阻結構之步驟前，先形成一 該開口中的該導電層上，以及形成一焊料層於該 曰，其中該蓋層包括鎳或鎳合金兩者中至少一者。 6·如巾請專·圍第丨項所述之龍電路元件的形 、方法，其中該導電層包括銅或銅合金兩者中至少一者。 ^一種積體電路元件的形成方法，包括： 形成一凸塊下冶金層於一半導體基板上；
    阻二Γ第一光阻膜於該凸塊下冶金層上，該第-光 阻膜/、有一第一厚度與一第一光敏性； 阻膜二光阻膜於該第—光阻獏上，且該第二光 阻膜具有一第二厚度與一第二光敏性； 产大第二光敏性大於該第—紐性，且該第二厚 度大於該第一厚度； D ; 光製程至該第二光阻膜與該第-光阻膜； 移除未曝光的部份該第二光阻膜以形成一第一開 下冶2未：Γ部份該第一光阻膜以露出部份該凸塊 一第：；“第二開口於該第-開口下，以及形成 第—開口於該第二開口下； 之底ΐ:該！一光阻膜圍繞該第二開口，且該第二開口 之底。卩直徑大於該第二開口之頂部直秤. 開第，、該第二開口、與該第三 移4第！至露出的部份該凸塊下冶金層；以及 第二光阻膜與該第-光阻膜，其中該銅層形 0503^A35493TWF/hsuhuche 201207967 成一銅柱。 · 、8.如申明專利範圍第項所述之積體電路元件的形 成方法’其中該第二開口之側壁與該凸塊下冶金層交會 之夾角小於90度，其中該第二開口之底部直徑比該第二 開口之頂部直徑大2μπ1以上。 一種積體電路元件的形成方法，包括： 形成一凸塊下冶金層於一半導體基板上； 形成一第一光阻膜於該凸塊下冶金層上，該 阻膜具有一第一厚度與一第一光敏性； 第二光阻膜於該第—光阻臈上，且該第二光 阻膜具有—第二厚度與-第二光敏性； 其中該第—祕性大於該第二光敏性，且該第 度大於該第一厚度； 進行一曝光餘至該第二光賴與—光阻膜； 移除曝光的部份該第二光阻膜以形成一第一開口； 冶金:除=的：份該第一光阻膜以露出部份該凸塊下 ;$成-第二開口於該第—開口下，以及形成一 第一開口於該第二開口下； 其中該第一光阻膜圍繞該第二開口， 之底部直徑大於該第：開口之頂部直徑；且料一開口 門口 銅層於該第一開口、該第二開口、與該第三 電性連接至露出的部份該凸塊下冶金層；以及 成：該第二光阻膜與該第-光阻膜，其中該銅層形 1〇.如申請專利範圍第9項所述之積體電路元件的 0503-A35493TWF/hsuhuche 201207967 形成方法，其中該第二開口之側壁與該凸塊下冶金層交 會之夾角小於90度，其中該第二開口之底部直徑比該第 二開口之頂部直徑大2μπι以上。
    0503^A35493TWF/hsuhuche 21
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