TW201125051A - Semiconductor device and method of forming compliant stress relief buffer around large array WLCSP - Google Patents

Semiconductor device and method of forming compliant stress relief buffer around large array WLCSP Download PDF

Info

Publication number
TW201125051A
TW201125051A TW099135402A TW99135402A TW201125051A TW 201125051 A TW201125051 A TW 201125051A TW 099135402 A TW099135402 A TW 099135402A TW 99135402 A TW99135402 A TW 99135402A TW 201125051 A TW201125051 A TW 201125051A
Authority
TW
Taiwan
Prior art keywords
layer
buffer layer
semiconductor die
forming
stress
Prior art date
Application number
TW099135402A
Other languages
English (en)
Other versions
TWI511211B (zh
Inventor
Yao-Jian Lin
Seng Guan Chow
Il-Kwon Shim
Original Assignee
Stats Chippac Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Stats Chippac Ltd filed Critical Stats Chippac Ltd
Publication of TW201125051A publication Critical patent/TW201125051A/zh
Application granted granted Critical
Publication of TWI511211B publication Critical patent/TWI511211B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01073—Tantalum [Ta]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1433—Application-specific integrated circuit [ASIC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30105—Capacitance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Description

201125051 六、發明說明： 【發明所屬之技術領域】 本發明大體上和半導體裝置有關，且更明確地說，和 半導體裝置及形成順從的應力緩和緩衝層於大型陣列晶元 級晶片尺度封裝周圍之方法有關。 【先前技術】 在現代的電子產品中經常會發現半導體裝置。半導體 裝置會有不同數量與密度的電組件。離散式半導體裝置通 常含有一種類型的電組件，舉例來說，發光二極體（Light Emitting Diode，LED)、小訊號電晶體、電阻器、電容器、 電感器、以及功率金屬氧化物半導體場效電晶體（MeUl
Oxide Semiconductor Field Effect Transistor , MOSFET)。積 體式半導體裝置通常含有數百個至&百萬個電組件。積體 式半導體裝置的範例包含微控制器、微處理器、電荷麵合 裝置（Charged-Coupled Device，CCD)、太陽能電池、以及 數位微鏡裝置（Digital Micro-mirror Device，DMD)。 半導體裝置會實施各式各樣的功能，例如，高速計算、 傳送與接收電磁訊號、控制電子裝置、將太陽光轉換成電 能以及產生電視顯示器的視覺投影。在娛樂領域、通訊領 域、電力轉換領域、網路領域、電腦領域以及消費性產品 領域中皆會發現半導體裝置。在軍事應用、航空、自動車、 工業控制器以及辦公室設備中同樣會發現半導體裝置。 半導體裴置會利用半導體材料的電氣特性。半導體材 料的原子結構會使得可藉由施加電場或基礎電流或是經由
S 201125051 換雜處理來操縱其導電性。摻雜會將雜質引入至該半導體 材料之中’以便操縱及彳控制該半導體裝置的傳導性。 半導體裝置會含有主動式電氣結構與被動式電氣結 構主動式結構（其包含雙極電晶體與場效電晶體）會控制電 μ的動。藉由改變摻雜程度以及施加電場或基礎電流， 的流動。被動式結構（其包含 )會創造用以實施各式各樣電 間的關係。該等被動式結構 成讓該半導體裝置實施高速 種複雜的製程來製造，也就 每一者皆可能涉及數百道步 晶圓的表面上形成複數個晶 含有藉由電連接主動式組件 後端製造涉及從已完成的晶 該晶粒，用以提供結構性支 標便係生產較小的半導體裝 少電力’具有較高效能，並 較小的半導體裝置還具有較 端產品所需要的。藉由改善 尺寸，從而導致具有較小以 動式组件的晶粒。後端製程 裝材料而導致具有較小覆蓋 言亥電曰曰曰體便會提高或限制電流 電阻器、電容器、以及電感器 氣功能*所需要的電壓和電流之 與主動式結構會被電連接以形 計算及其它實用功能.的電路。 半導體裝置通常會使用兩 是，前端製造以及後端製造， 驟。則端製造涉及在一半導體 粒母—個晶粒通常相同並且 和被動式組件而形成的電路。 圓中切割個別的晶粒並且封裝 撐及環境隔離。 半導體製造的其中一個目 置。較小的裝置通常會消耗較 且能夠更有效地生產。此外， 小的覆蓋面積，這係較小的末 前端製程可以達成較小的晶粒 及較高密度之主動式組件和被 可以藉由改善電互連材料及封 201125051 面積的半導體裝置封裝》 1 晶圓級晶片尺度封裝（WLCSP)與扇出晶圓級晶 封裝（F〇-WLCSP)通常含有大型陣列半導體晶粒，其會將ς 號路徑從該晶粒的小間距焊塾處重新分佈至周圍扇出 以便達到與外部裝置有更高功能性整合的目的。已:的 係，大型陣列晶圓級晶片尺度封裝會有可靠度問題，明確 地說，在溫度循環測試及落下衝擊測試期間會造成焊料接 合失效。此外，大型陣列晶圓級晶片尺度封裝還有會因為 大粒尺寸的關係而造成翹曲的傾向。 【發明内容】 在大型陣列晶圓級晶片尺度封裝與扇出晶圓級晶片尺 度封裝中都需要降低焊料接合失效。據此，於其中一實施 例中，本發明係一種製造半導體裝置的方法，其包括下面 步驟：形成-應力緩和緩衝層；提供一暫時性基板；固定 -半導體晶粒至該暫時性基板；固定該應力緩和緩衝層至 該暫時性基板於該半導體晶粒周圍；沉積一囊封劑於該半 導體晶粒及應力緩和緩衝層之間；移除該暫時性基板；以 及形成-互連結構在該半導體晶粒、囊封劑、以及應力緩 和緩衝層的上方。該互連結構被電連接至該半導體晶粒。 於另一實施例令，本發明係一種製造帛導體裝置的方 法，其包括下面步驟：提供一暫時性基板；固定一半導體 晶粒或組件至該暫時性H·㈣一應力緩和層於該暫時 性基板的上方’·沉積一囊封劑於該應.力緩和層及半導體晶 粒或組件的上方，·移除該暫時性基板；以及形成一互連結 201125051 構在該半導體晶粒或組件以及應力緩和層的上方。該互連 結構被電連接至該半導體晶粒。 於另一實施例中，本發明係—種製造半導體裝置的方 法，其包括下面步驟：提供一暫時性基板；固定一半導體 晶粒或組件至該暫時性基板；固定一應力緩和緩衝層至該 暫時性基板，以及沉積一囊封劑於該應力緩和缓衝層及半 導體晶粒或組件之間。 於另一實施例中，本發明係—種半導體裝置，其包括 半導體晶粒或組件以及被設置在該半導體晶粒或組件周 圍的應力緩和緩衝層。一囊封劑―，其被設置在該應力緩和… 緩衝層及半導體晶粒或組件之間。一互連結構，其被形成 在該半導體晶粒或組件及應力緩和緩衝層的上方。該互連 結構被電連接至該半導體晶粒或組件。 【實施方式】 下面的說明書中會參考圖式於一或多個實施例中來說 明本發明’於該等圖式中’㈣的符號代表相同或雷同的 元件。雖然本文會以達成本發明目的的最佳模式來說明本 發明，不過，熟習本技術的人士便會明白，本發明希望涵 蓋受到下面揭示内容及圖式支持的隨附申請專利範圍及它 們的等效範圍所定義的本發明的精神與範疇内可能併入的 替代例、修正例以及等效例。 半導體裝置通常會使用兩種複雜的製程來製造：前端 製造和後端製造。前端製造涉及在一半導體晶圓的表面上 形成複數個晶粒。該晶圓上的每一個晶粒皆含有主動式電 201125051 組件和被動式電組件，它們會被電連接而形成功能性電 路。主動式電組件（例如電晶體與二極體）能夠控制電流的流 動:。被動式電組件(例如電容器、電手器' 電阻器、以及變 壓窃)會創造用以實施電路功能所需奏的電壓和電流之間的 關係。 ，被動式組件和主動式組件會藉由一連串的製程步驟被 形成在該半導體晶圓的表面上方，該等製程步驟包含：推 雜、沉積、光微影術、钮刻以及平坦化。播雜會藉由下面 的技術將雜質引入至半導體材料之中，例如：離子植入戍 是熱擴散。摻雜製程會修正主動式裝置中半導體材料的導 電將該半導體材料轉換成絕緣體、導體，或是響應於 電場或基礎電流來動態改變半導體材料傳導性。電晶體含 有不同類型和不同摻雜程度的多個區域，它們會在必要時 被排列成用以在施加__雷揚w i _ 场或基礎電流時讓該電晶體會提 高或限制電流的流動。 主動式組件和被動式組件係由具有不同電氣特性的多 層材料構成。該等層能夠藉 楮由各式各樣的沉積技術來形 成，其部分取決於要姑 /積的材料的類型。舉例來說，薄 膜沉積可能包含：化學氣相沉積⑽emieai ¥ p sition CVD)製程、物理氣相沉積(Physka】Va_
Deportlon，PVD)製程、電解質電錢製程以及無電極電鍍製 程。母一層通常都舍 會被圖樣化’以便形成主動式組件的一 部分、被動式組件的一邱八s Λ ν 的刀或是組件之間的電連接線的一 部分。 201125051 該等層能夠利用亦 Μ外Μ 先微衫術來圖樣化，其涉及在要姑圖 樣化的層的上方沉積名敏材料，舉例來說，=在要被圖 會利用光從-光罩處先严。-圖樣 光作用的部分會利用Α才該光阻圖樣中受到 圖樣化的部分。亨光:中除，從而露出下方層之中要被 -已圖樣化層。：者 剩餘部分會被移除，從而留下 以及電解質電鍍之類的 用…、電極電鍍 技術’藉由將該材料直接籍5 Λ “積及/或蝕刻製程 積至先 圖樣化。 &成的5域或空隙之中而被 在—既有圖樣的上方、、兑 圖樣並且產生一不均勺平材料可能會擴大下方 穿的主動… 表面。生產較小且更密集封 裝的主動式組件和被動古 動式組件需要用到均勻平坦的表面。 千坦化作用可用來從晶 圓的表面處移除材料，並且產生均 勻平坦的表面。平坦化作夺 ΛΑ * ^ . . β及利用一研磨墊來研磨晶圓 的表面。有磨蝕作用的姑 网 麻细Μ 材科以及腐飯性的化學藥劑會在研 磨期間被加到晶圓的表面。 ,,,,m . 化予樂劑的磨蝕性作用及腐蝕 性作用所組成的組合式機 ㈣"，* 械作用會移除任何不規律的拓樸 形狀，從而產生均勻平坦的表面。 後端製造係指將已完成的s 玖的日日圓裁切或切割成個別晶 拉，並且接著封裝該晶粒， 效果。對切割晶粒而言，晶圓：：構，樓及壞境隔離的 4, ®日>α考遠晶圓中被稱為切割 ::street)或切割線（scribe)的非功能性區域形成刻痕並 折斷。該晶圓會利用雷射裁切工具或鑛片來進行切判。 經過切割之後，個別晶粒便會被固定至包含接針或接觸觸 9 201125051 墊的封裝基板，以便和其它系統組件進行互連。被形成在 該半導體晶粒上方的接觸觸塾接著會被連接至該封裝裡面 的接觸觸塾《該等電連接線可利用焊料凸塊、短柱凸塊、 導電膏或是焊線來製成…囊封劑或是其它模造材料會被 =積在該封裝的上方，用以提供物理性支樓和電隔離。接 者，該已完成的封裝便會被插入一電氣系統之中並且讓其 它系統組件可取用該半導體裝置的功能。 圖1圖解電子裝置50，其具有一晶片載體基板或是 印刷電路板（printed Circuit B〇ard，pCB)52，在其表面上固 定著複數個半導體封裝。電子裝置5〇可能具有某一類型的 半導體封裝或是多種類型的半導體封裝，端視應用而定。. 為達解釋目的，圖1中顯示不同類型的半導體封裝。 電子裝置50可能係一單機型系統，其會使用該等半導 體封裝來實施一或多項電氣功能，或者，電子裝置5〇亦可 月b係較大型系統中的一子組件。舉*例來說，電子裝置5 〇 可能係一圖形卡、一網路介面卡或是能夠被插入在一電腦 之中的其它sfl號處理卡。該半導體封裝可能包含：微處理 器、記憶體、特定應用積體電路,（Applicati〇n Specific Integrated Circuits，ASIC)、邏輯電路、類比電路、射頻電 路、離散式裝置、或是其它半導體晶粒或電組件。 在圓1中’印刷電路板52提供一通用基板，用以結構 性支撐及電互連被固定在該印刷電路板之上的半導體封 裝。多條導體訊號線路54會利用下面製程被形成在印刷電 路板52的一表面上方或是多層裡面：蒸發製程、電解質電
S 10 201125051 鍍製程、無電極電鍍製程、網印製程或是其它合宜的金屬 沉積製程。訊號線路54會在該等半導體封裝、被固定的組 件以及其它外部系統組件中的每―者之間提供電通訊。線 路5 4還會提供連接至每—個該等半導體封裝的電力連接線 及接地連接線。 於某些實施例中，-半導體裝置會有兩個封裝層。第 -層封裝係-種用於以機械方式及電氣方式將該半導體晶 粒附接至一中間載板的技術。第二層封裝則涉及以機械方 式及電氣方式將該中間載板附接至該印刷電路板。於其它 實施例中，一半導體裝.置可能僅有該第一層封裝，其中， •亥曰曰粒會以機械方式及電氣方式直接被固定至該印刷電路 板。 為達解釋目的，圖中在印刷電路板52之上顯示數種類 型的第一層封裝，其包含焊線封裝56以及覆晶58。除此之 外，圖中還顯示被固定在印刷電路板52之上的數種類型第 二層封裝，其包含：球柵陣列（Ball Grid Array，bgA)6〇 ; 凸塊日日片載板（Bump Chip Carrier，BCC)62 ;雙直列封裝 (Dual ln_Hne Package，DIp)64;平台格柵陣列（Land G^d
Array ’ LGA)66，多晶片模組（Multi-Chip Module，MCM)68 ; 方形扁平無導線封裝（Quad Fiat N〇n-leaded package，QFN ) 70，以及方形扁平封裝72。端視系統需求而定，被配置成 具有第一層封装樣式和第二層封裝樣式之任何組合以及其 匕電子組件的各種半導體封裝的任何組合皆能夠被連接至 印刷電路板52。於某些實施例中，電子裝置5〇包含單一附 201125051 接半導體封裝；而其它實施例則要求多個互連封裝。藉由 在單一基板上方組合一或多個半導體封裝，製造商便能夠 將事先製成的組件併入電子裝置和系統之中。因為該等半 導體封裝包含精密的功能，所以，電子裝置能夠使用較便 宜的組件及有效率的製程來製造。所產生的 月匕失效而且製造價格較低廉’從而會降低消費者的成本。 圖2a至2c所示的係示範性半導體封裝。圖2a所示& 係被固定在印刷電路板52之上的雙直列封裝64的進一多 細節。半導體曰曰曰粒74包含一含有類比電路或數位電路的立 動區，該等類比電路或數位電路會被施行為被形成在該曰弓 ♦裡面的主動式裝置、被動式裝置、導體層以及介電層， 並且會根據該晶粒的電氣設計來進彳^電互連。舉例來說， 該電路可能包含被形成在半導體晶粒74之主動區裡面的一 或多個電晶體、二極體、雷片盟 電感益、電谷器、電阻器以及其 匕電路兀件。接觸觸墊76係由一或多層的導體材料(例如鋁 :銅二、錫(Μ、_)、金(AU)、或是銀_)製成， 在：破電連接至形成在半導體晶粒74裡面的電路元件。 2直列封裝64的組裝期間，半導體晶敕74會利用一金_ 梦共炼合金層或是膊/ 中門㈣Μ μ 熱環氧樹脂）被黏著至一 中間載板78。封裝主體包含一 ^ a ^ 0 m 6 、、緣封裝材料，例如聚合物 或疋陶是導體導線8〇以及桿㈣ 印刷電路板52之間提供電互連 ^體日日拉74與 封裝的上84會被沉積在該 74 82 …、粒子進入該封裝並污染晶粒 戈知線82而達到環境保護的目的。 12 £ 201125051 ，圖2b所示的係被以在印刷電路板52之上的凸塊晶 片載板62的進—步細_。半導體晶粒μ會利用底層填充 材料或％氧樹月曰膠黏材料92被固定在載板卯的上方。焊 滩94曰在接觸觸墊96與％之間提供第一層封裝互連。模 造化合物或囊封劑100會被沉積在半導體晶粒“和焊線94 方用以為s亥裝置提供物理性支撐以及電隔離效果。 夕個接觸觸墊1 02會利用合宜的金屬沉積製程(例如電解質 電鍍或無電極電鍍)被形成在印刷電路& 52的一表面上方 用以防止氧化。接觸觸$ 1〇2會被電連接至印刷電路板Μ 中的—或多條導體訊號線路_54。多個凸塊.1〇4會被形成在 凸塊晶片載板62的接觸觸墊98和印刷電路板52的接觸觸 墊102之間。 在圖2c中，半導體晶粒58會利用一覆晶樣式的第一層 封裝以面朝下的方式被固定至中間載板1〇6。半導體晶粒 Μ的主動區108含有類比電路或數位電路，該等類比電路 或數位電路會被施行為根據該晶粒的電氣設計所形成的主 動式裝置、被動式裝置·、導體層以及介電層。舉例來說， 5玄電路可能包含被形成在主動區108裡面的一或多個電晶 體一極體、電感益、電谷益、電阻益以及其它電路元件。 半導體晶粒58會經由多個凸塊11〇以電氣方式及機械方式 被連接至載板106。 球栅陣列60會利用多個凸塊112，以球柵陣列樣式的 第二層封裝被電氣性及機械性連接至印刷電路板52。半導 體晶粒58會經由凸塊1; 10、訊號線114以及凸塊丨丨2被電 13 201125051 連接至印刷電路板52中的導體訊號線路54。一模造化合物 或囊封劑1 1 6會被沉積在半導體晶粒58和載板1 〇6的上 方’用以為該裝置提供物理性支撐以及電隔離效果。該覆 晶半導體裝置會提供一條從半導體晶粒58上的主動式裝置 至印刷電路板5 2上的傳導軌的短電傳導路徑，以便縮短訊 號傳播距離、降低電容、並且改善整體電路效能。於另— 實施例中，該半導體晶粒58會利用覆晶樣式的第一層封裝 以機械方式及電氣方式直接被連接至印刷電路板52，而沒 有中間載板106。 圖3a至3f所示的係’配合圖1及2a至2c，用以在_ 半導體晶粒周圍形成順從的應力緩和緩衝層的製程。在圖 3a中’ 一基板或載板120含有暫時性或犧牲性基礎材料， 例如，石夕、聚合物、高分子合成物、金屬、陶究、玻璃、 玻璃環氧樹脂'氧化鈹或是其它合宜的低成本剛性材料或 大型半導體材料’用以達到結構性支撐的目的。一非必要 的w面層122可能會被形成在載板12〇的上方，成為一暫 時性的焊接膜或是蝕刻阻止層。 多個半導體晶粒或組件1 24會被固定至介面層丨22，主 動表面128上的接觸觸墊126會向下朝向載板12〇。主動表 面128含有類比電路或數位電路，該等類比電路或數位電 路會被把行為被形成在該晶粒裡面的主動式裝置、被動式 裝置、導體層以及介電層，並且會根據該晶粒的電氣設計 與功能來進行電互連。舉例來說，該電路可能包含被形成 在主動表面128裡面的一或多個電晶體、二極體以及其它 201125051 電路元件，用以施行類比電路或數位電路， 〇 例如’數位訊 號處理器（Digital Signal Processor，DSP、、姓 a 十 )将疋應用積體電 路、記憶體或是其它訊號處理電路，半導體晶粒124可能 還含有用於射頻訊號處理的整合被動元件（IPD)，例士 電 感器、電容器以及電阻器。 在圖3b中，會利用模造製程將一順從的應力緩和緩衝 層或區塊結構130事先形成為圓形或方形的補片或是矩形 的條狀物。應力緩和緩衝層13〇含有順從材料，例如，聚 合物、環氧樹脂、高分:子材料、具有填充劑的環氧樹脂或 是具有填充劑的環氡丙烯酸酯。或者，應力緩和緩衝層u〇 可能係預先浸透（預浸法（prepreg))酚醛棉紙、環氧樹脂樹 脂、織狀玻璃纖（woven glass)、毛玻璃（matte glass)、聚酯 以及其它強化纖維或織，之組合的聚四氟乙烯；有核心層 的印刷電路板材料；或是其它阻尼材料。應力緩和緩衝層 130會在被指定用於形成凸塊的位置132中（也就是，在已 完成的扇出晶圓級晶片尺度封裝的邊緣或角落處）被固定至 介面層122。 在圖3c中，一囊封劑或模造化合物丨36會利用焊膏印 刷（paste printing)塗敷機：壓縮模造（cornpressive molding) 塗敷機、轉印模造（transfer molding)塗敷機、液體囊封劑模 造塗敷機、真空層疊塗敷機、旋塗塗敷機或是其它合宜的 塗敷機被沉積在應力緩和緩衝層1 3 0與半導體晶粒1 24之 間以及被沉積在該半導體晶粒的上方直到與該應力緩和緩 衝層齊平的水平處。應力緩和緩衝層1 3 〇可能厚過半導體 15 201125051 晶粒124，因此，囊封劑136會覆蓋該晶粒的背表面138。 囊封劑136可能係高分子合成材料，例如，具有填充劑的 環氧樹脂、具有填充劑的環氧丙稀酸g旨或是具有適當填充 劑的聚合物。囊封齊"36係非導體並且會為半導體裝置提 供環境保護，避免受到外部元素與污染物破壞。 圖3d所示的係載板12〇上方的四個半導體晶粒124、 應力緩和緩衝層13〇、以及囊封劑136所組成之群集的俯視 圖。應力緩和緩_ 130會在該扇出晶圓級晶片尺度封裝 的邊緣或角落處被固定至指定用於形成凸塊的位置132。 在圖3e +，暫時性載板12〇與非必要的介面層122會 藉由下面方式被移㊉’化學性钱刻 '機械性剝離、化學機 械研磨（CMP)、機械性研磨、熱烘烤、雷射掃描或是濕式剝 除底邊增進互連結構140會被形成在半導體晶粒丨24、 應力緩和緩衝層13〇以及囊封劑136的上方。該增進互連 結構140包含一絕緣層或鈍化層142，其含有由下面所製成 的一或多層.二氧化矽（si〇2);氮化矽（Si3N4);氮氧化矽 (SiON);五氧化二鈕（Ta2〇5);三氧化二鋁（ai2〇3);低溫 (5250 C )固化尚分子光阻（例如，環苯丁烯（BCB)、聚苯并噁 坐纖、准（PB0)、以環氧樹脂為基礎的光敏高分子介電質）；戋 是具有雷同絕緣特性及結構性特性的其它材料。該絕緣層 142係利用下面方法所形成：物理氣相沉積、化學氣相沉 積、印刷、旋塗 '喷塗 '燒結或是熱氧化。一部分的絕緣 層142會藉由蝕刻製程被移除，用以露出半導體晶粒DA 的接觸觸墊126。 £ 16 201125051 一導電層144會使用圖樣化與金屬沉積製程（例如物理 氣相沉積、化學氣相沉積、機錢、電解質電銀以及無電極 電鐘）被形成在絕緣層142與接觸觸塾126的上方。導體層 ⑷可能係由下面所製成的—或多層：Ai、cu、sn、^
An、Ag或是其它合宜的導電材料。導體層⑷的操作如同 -重新分配層(跳)。導體層144中的一部分會被電連接至 +導體晶粒m的接觸駿126。導體層144中的其它部分 可能為共電或者會被電隔離，端視該半導體裝置的設計及 功能而定。 絕緣層或鈍化層146.會利用下面方法㈣成在 Z14;與導體層144的上方：物理氣相沉積、化學氣相沉 =:刷、旋塗、錢、燒結或是熱氧m緣層146 =由下面所製成的一或多層：si〇2 一 丁烯、聚—〇3亞低'皿⑼〇C)固化高分子光阻（例如，環苯 子介電質二坐纖維或是以環氧樹脂為基礎的光敏高分 料。，3①具有”絕緣特性及結構性特性的其它材 枓。—部分的絕緣層146合 出導體層144。 曰藉由敍刻製程被移除’用以露 益電：：電凸塊材料會利用蒸發製程、電解質電鍵製程、 無電極電鑛製程、丸滴製程 二 連結構的上方並且 儿積在增進互 料可能係A卜Sn、Ni、A、A 導體層144。該凸塊材 們的叙合，1合有' U § ^^'^、焊料以及它 ^ ^ ^ ^ ；n/Pb ^ ^ ^ "J ^ ? •、问釔知枓或是無鉛焊料。該 17 201125051 凸塊材料會利用合宜的附著或焊接製程被焊接至導體層 144。於其中一實施例中，該凸塊材料會藉由將該材料加熱 至其熔點以上而被回焊，用以形成球狀的丸體或凸塊148。 於某些應用中，凸塊U8會被二次回焊，以便改善和導體 層144# t接觸效果。該等凸塊也能夠被壓縮焊接至導體 層144。凸塊148代表能夠被形成在導體層144上方的其中 -種類型的互連結構。該互連結構亦能夠使用焊線、短柱 凸塊、微凸塊或是其它電互連線。 圖3f所示的係四個半導體晶粒124、應力緩和緩衝層 130、.應力緩和緩衝層13〇、以及囊封劑136所組成之群集 的俯視圖，接觸㈣126會經由導體層U4被電連接至凸 塊 148。 -亥最終的半導體封裝（其包含半導體晶⑯124、囊封劑 化合物Π6、應力緩和緩衝| 13〇、以及互連結構14〇)會利 用鋸片或雷射裁切裝置】5〇沿著圖3e與灯中的直線被切割 成個別的半導體裝置4所示的係在經過切割之後的扇 出晶圓級晶片尺度封裝15卜半導體晶粒124會被電連接至 底邊增進互連結構140與凸塊148。事先形成之順從的應力 緩和緩制13G會被設置在扇出晶圓級晶片尺度封裝151 的邊緣、肖洛、以及其它封裝完整性關鍵區域周圍，以便 藉由吸收熱機械應力而在溫度循環測試及可靠度的其它機 械性撞擊或衝擊或是落下測試期間防止凸& 148失效。應 力緩和緩衝層130具有低楊氏模數(也就是，小於囊封劑 13 6 )，良好的彈性與强六姓μ 兴洋力特Μ，而且熱膨脹係數（c〇efficiem
S 18 201125051
Expansion，CTE)等於或略小於該囊封劑。應力 130還會在囊封製程期間用以降低晶粒偏移。 of Thermal 緩和緩衝層 圖5a與5b所示的係部分或完全沿著該扇出晶圓級晶片 尺度封裝的-側邊152延伸的事先形成之順從的應力緩和 緩衝層1 3 0的剖視圖與俯視圖。 圖6所示的係和在圖3a至Η中所述之結構雷同的扇出 晶圓級晶片尺度封t 154的實施例，其具有含有多層的事 先形成之合成應力緩和緩衝層156。於其中一實施例中，合 成應力緩和緩衝層156具有一順從的材料層158、石夕： 16〇、议及順從的材料層158。或者，合成應力緩和緩衝層 156中的各層為金屬/順從材料/金屬或是矽/順從材料/矽。 合成應力緩和緩衝層156會減少扇出晶圓級晶片尺度封裝 154中的翹曲。藉由減巧翹曲及熱膨脹係數誘發的應力，扇 出晶圓級晶片尺度封裝154會的焊料接合失效會降低，尤 其是在該半導體晶粒的周圍附近。 圖7所示的係和在圖3&至3f中所述之結構雷同的扇出 晶圓級晶片尺度封裝162的實施例，在應力緩和緩衝層【Μ 與囊封劑136的上方固定著金屬加固物或層164。一膠黏層 會破沉積在應力緩和緩衝層130的上方，用以固定加固物 164。加固物164會減少扇出晶圓級晶片尺度封裝中的 翹曲。加固物164能夠作為散熱片，其具有一非必要的熱 介面材料（Thermal lnterface Materia卜 TIM)166，用以從 ^ 導體晶粒124處進行散熱。當作散熱片時，加固物164可 能係Ah Cu或是具有高導熱係數的其它材料。熱介面材料 19 201125051 166有助於分佈與消散半導體晶粒124所產生的熱。加固物 164 亦可當作電磁干擾（Electr〇Magnetic Interference，εΜΙ) 遮蔽層或射頻干擾（Radi〇 Frequency Interference，RFI)遮蔽 層°當作電磁干擾或射頻干擾遮蔽層時，加固物164可能 係Cu ’ A1 ’鐵氧體或数基鐵（carbonyl iron);不鏽鋼；銀化 錄，低石反鋼，石夕鐵鋼（silic〇n-ir〇n steel);金屬箔；環氧樹脂； 導體樹脂；以及能夠阻隔或吸收電磁干擾、射頻干擾以及 其它裝置間干擾的其它金屬與合成物。該遮蔽層亦可能係 非金屬材料，例如，碳黑或鋁質薄片，用以降低電磁干擾 效應與射頻干擾效應。加固物164會被接地，用以轉移電 磁干擾訊號與射頻干擾訊號。 圖8所示的係和在圖3a至3f中所述之結構雷同的扇出 晶圓級晶片尺度封冑17〇的實施例，事先形成之應力緩和 緩衝層172含有被埋置在順從的應力緩和材料178裡面的 電路層176。電路層176可能含有類比電路或數位電路，該 等類比電路或數位電路會被施行為被形成在應力緩和材料 178裡面的主動式裝置 '被動式裝置、導體層以及介電層。 圖9a所不的係和在圖3a至3f中所述之結構雷同的扇 出晶圓級晶片尺度封裝刚的實施例.:，應力緩和緩衝層 會被製成比半導體晶粒124還薄。在沉積囊封齊"％之前， 金屬加固物或層182會先被固定在應力緩和緩衝層i 84 的上方° —膠點層會被沉積在應力緩和缓衝層1 84的上方， 以便固定加固物182。加固物182可能會被形成一完全包圍 半導體日日粒124的視窗，如圖外中所示。加固物丄82會减
20 S 201125051 少扇出晶圓級晶片尺度封裝180中的勉曲。
圖10a至l〇c所示的及 A 所不的係，配合圖i以及 在半導體晶粒周圍形成― 至2c，用以 圖3a中所述的妹構，j|g 力緩和層的製程。接續 T 構，一順從的應力 或網印在半導體晶粒124周圍被形成在；;97_塗 方。應力緩和…在固定半導體晶=二的上 積。在應力緩和層19G與半㈣晶 I被"。 隙或者可能沒有任何倘若有間隙的：間::::: 材料（例如，或環氧樹脂或高分曰' --缝沾I七由” ®分 叮θ破塗敷在晶粒邊 移。應力緩和層190可能伟一順從材囊料封期間防止晶粒偏 月b係順從材枓，例如，聚合物； %氧樹月曰’同分子材料；具有填充劑的環氧樹脂；且有填 充劑的環氧㈣料；純光阻；或是具有高伸長性、低 模數、以及平衡熱膨脹係數的其它順從材料。於其中一實 ^中，應力緩和層19G係—絕緣材料，例如，聚亞㈣； I本并°惡°坐纖維；石夕基弹Μ聽·赤Η曰 7丞评性體，或疋具有低熱膨脹係數 (2〇PPm/°C甚至更低）及赞模數（2_pa甚至更低）的其它雷 同材料。應力緩和層190的厚度通常為15至^⑽微米（" m)。 在圖i〇b中，一囊封劑或模造化合物192會利用焊膏 印刷塗敷機、Μ縮模造塗敷機、轉印模造塗敷機、液體囊 封劑模造塗敷機、真空層疊塗敷機、旋塗塗敷機或是其它 合宜的塗敷機被沉積在應力緩和層19〇與半導體晶粒124 的上方。囊封齊"92可能係高分子合成材料，例如，具有 21 201125051 填充劑的環氧樹脂、且有填 有填充剤的環氧丙烯酸酯或是且有 體;==合物。囊封劑192係非導體並且會:二 乂 〃核i兄保心避免受到外部元素與污染物破壞。 在圖1Ge + ’暫時性餘12G與非必要的 會藉由下面方式被蔣呤 曰122 機妯 * .予性蝕刻、機械性剝離、化學 機械研磨、機械性研磨、熱烘烤 一 ^由耵柯描或疋濕式剝除。 底邊^互連結構194會被形成在半導體晶粒η 應力陶190的上方。該增進互連結㈣4包含一絕緣 層或純化層196，其含有由下面所製成的一或多層：二緣 SJN4, Sl0N; τ_;卿3;或是具有雷同絕緣特性及 結構性特性的其它材料。該絕緣I 196係利用下面方法所 形成：物理氣相沉積、化學氣相沉積、印刷、旋塗、喷塗、 燒結或是熱氧化。—部分的、絕緣& 196會藉由#刻製程被 移除用以路出半導體晶粒124的接觸觸墊226。 -導電層198會使用圖樣化與金:屬沉積製程(例如物理 氣相沉積、化學氣相沉積 '濺鍍、電解質電鐘以及無電極 電鍵）被形成在絕緣層i “與接觸㈣126的上方。導體層 198可能係由下面所製成的一或多屬：^、如、犯、
Au、Ag或是其它合宜的導電材料。導體们98的操作如同 重新刀配層導體層198中的一部分會被電連接至半導 體晶粒124的接觸觸墊12“導體層198中的其它部分可能 為共電或者會被電隔離，端視該半導:體裝置的設計及功能 而定。 一絕緣層或鈍化層200會利用下面方法被形成在絕緣
S 22 201125051 層196與導體層198的上方：物理氣相沉積、化學氣相沉 積印刷、旋塗、喷塗、燒結或是熱氧化。該絕緣層2〇〇 可能係由下面所製成的一或多層：Si〇2 ; Si3N4 ; si〇N ;
Ta205 ; A1203 ;或是具有雷同絕緣特性及結構性特性的其 它材料。一部分的絕緣層2〇〇會藉由蝕刻製程被移除，用 以露出導體層198。 導電凸塊材料會利用蒸發製程、電解質電鍍製程、 無電極電鍍製程、丸滴製程或是網印製程被沉積在增進互 連結構194的上方並且會被電連接至導體層198。該凸塊材 料可能係A1、Sli、Ni、Au、Ag、_pb、m、. Cu、焊料以及它 們的組合，其會有一非必要的助熔溶液。舉例來說，該凸 塊材料可能是Sn/Pb共熔合金、高鉛焊料或是無鉛焊料。該 凸塊材料會利用合宜的附著或焊接製程被焊接至導體層 198。於其中一實施例中，該凸塊材料會藉由將該材料加熱 至其熔點以上而被回焊，用以形成球狀的丸體或凸塊2〇2。 於某些應用中，凸％ 202會被二次回焊，以便改善和導體 層198的電接觸效果。該等凸塊‘能，夠被壓縮焊接至導體 層198。凸塊202代表能夠被形成在導體層198上方的其中 -種類型的互連結構。該互連結構亦能夠使用焊線、短柱 凸塊、微凸塊、或是其它電互連線。 半導體晶粒124會，利用鑛片或雷射裁切裝置204被切 割成個別的半導體裝置。圖i la所示的係在切割之後的扇出 晶圓級晶片尺度封裝2〇6的剖視圖。0 m所示的係半導 體晶粒124與應力緩和層19〇的仰視圖，接觸㈣126會 23 201125051 經由導體層198被電連接至凸塊202。該順從的應力緩和層 190會被設置在半導體晶粒124周圍，以便藉由吸收熱機械 應力而在溫度循環測試及可靠度的其它機械性撞擊或衝擊 或疋落下測域期間防止凸塊202失效。應力緩和層19〇具 有低楊氏模數（也就是，小於囊封劑192)，良好的彈性與彈 力特徵，而且熱膨脹係數等於或略小於該囊封劑。應力緩 和層190還會在囊封製程期間用以降低晶粒偏移。 雖然本文已經詳細解釋過本發明的一或多個實施例； 不過，熟練的技術人士便會明白，可以對該些實施例進行 修正與改變，其並不會脫離後面申請專利範圍中所提出的 本發明的範嘴。 【圖式簡單說明】 圖1所示的係一印刷電路板，在其表面上固定著不同 類型的封裝； . 圖2a至2c所示的係被固定至該印刷電路板的代表性半 導體封裝的進一步細節； "圖3a至3f所示的係用以在一半導體晶粒周圍形成一順 從的應力緩和緩衝層的製程； 圖4所不的係於該半導體晶粒周圍具有該應力緩和緩 厂曰的扇出晶圓級晶片尺度封裝； 至5t>所不的係部分或完全沿著該扇出晶圓級晶片 义封裝的一側邊延伸的應力緩和緩衝層； 斤7Γ的係—多層合成應力緩和緩衝層； 圖 7所示的俾—.. '、一被固定在該應力緩和緩衝層與半導體
S 24 201125051 晶粒上方的加固物； 圖8所示的係一被形成在該應力緩和緩衝層之中的電 路層； 圖9a至9b所示的係一被形成在一比該半導體晶粒還薄 的應力緩和緩衝層上方的加固物； 圖1 〇a至10c所示的係在一半導體晶粒周圍形成一順從 的應力緩和層的製程；以及 圖11 a至1 lb所示的係於該半導體晶粒周圍具有該應力 缓和層的扇出晶圓級晶片尺度封裝。 Γ主要元件符號說明】· 50 電子裝置 52 印刷電路板（PCB) 54 線路 56 焊線封裝 58 半導體晶粒 60 球柵陣列（BGA) 62 凸塊晶片載板（BCC) 64 雙直列封裝（DIP) 66 平台格柵陣列（lga) 68 多晶片模組（MCM) 70 方形扁平無導線封裝（qfn) 72 方形扁平封裝 74 半導體晶粒 76 接觸觸塾 25 201125051 78 中間載板 80 導體導線 82 焊線 84 囊封劑 88 半導體晶粒 90 載板 92 膠黏材料 94 焊線 96 接觸觸墊 98 接觸觸墊 100 模造化合物或囊封劑 102 接觸觸墊 104 凸塊 106 中間載板 108 主動區 1 10 凸塊 112 凸塊 114 訊號線 116 模造化合物或囊封劑 120 基板或載板 122 介面層 124 半導體晶粒或組件’ 126 接觸觸墊 128 主動表面
S 26 201125051 130 合成應力緩和緩衝層或區塊結構 132 位置 136 囊封劑或模造化合物 13 8 背表面 140 增進互連結構 142 絕緣層或鈍化層 144 導電層 146 絕緣層或鈍化層 148 球狀的丸體或凸塊 149 直線 150 鋸片或雷射裁切裝置 151 扇出晶圓級晶片尺度封裝 152 扇出晶圓級晶片尺度封裝的側邊 154 扇出馬圓級晶片尺度封裝 156 合成應力緩和緩衝層 158 順從材料 160 矽層 162 扇出晶圓級晶片尺度封裝 1 64 金屬加固物或層 166 熱介面材料（TIM) 170 扇出畢圓級晶片尺度封裝 •j 172 應力緩和緩衝層 176 電路層 178 順從的應力緩和材料 27 201125051 180 扇 出 晶 圓 級 晶片 尺 度 封 裝 182 金 屬 加 固 物 或層 184 應 力 緩 和 緩 衝層 190 應 力 缓 和 緩 衝層 192 囊 封 劑 或模 造化 合物 194 增 進 互 連 結 構 196 絕 緣 層 或 鈍 化層 198 導 電 層 200 絕 緣 層 或鈍化層 202 球狀 的 丸 體 或凸 塊 204 鋸 片 或 雷 射 裁切 裝 置 206 扇 出 晶 圓 級 晶片 尺 度 封 裝 s 28

Claims (1)

  1. 201125051 七、申請專利範圍： 1.一種製造半導體裝置的方法，其包括： 形成一應力緩和緩·衝層； 提供一暫時性基板； 固疋一半導體晶粒至該暫時性基板； 固定該應力緩和緩衝層至該暫時性基板於該半導體晶 粒周圍； 沉積一囊封劑於該半導體晶粒及應力緩和緩衝層之 間； 移除該暫時性基板、；以及 . 形成一互連結構於該半導體晶粒、囊封劑以及應力缓 矛緩衝層的上方’ $互連結構被電連接至該半導體晶粒。 2. 如申請專利範圍第1項的方法，其進-步包含形成該 應力緩和緩衝層在被指定用於形成凸塊的位置中。 3. 如申請專利範圍第1項的方法，其中，該應力緩和缓 衝層包含一具有阻尼特性的吝 刃夕層合成材料與結構。 4. 如申請專利範圍第1 ’ 貝的方法’其中，形成該應力級 和緩衝層包含： ^ PX, 形成-矽層於該第一順從層上方；以及 形成一第二順從層於該矽層上方。 5 ·如申5月專利範圍第1項的古土 ,m a λ 貝的方法，其進一步包含形成 加固層於該應为@ @ 力緩和綾衝層與囊封劑的上方。 6.如申請專利範圍第i $的方法’其中，該應力緩和 29 201125051 衝層比半導體晶粒還薄。 7_如申請專利範圍第【項的方法，其進一步包含形成— 電路於該應力緩和緩衝層裡面。 8·—種製造一種半導體裝置的方法，其包括： 提供一暫時性基板； 固疋一半導體晶粒或組件至該暫時性基板； 形成一應力緩和層於該暫時性基板的上方； 沉積-囊封劑於該應力緩和層及半導體晶粒或組件的 上方； 移除該暫時性基板；以及 - 形成一互連結構於該半導體晶粒或組件以及應力緩和 層的上方，該互連結構被電連接至該半導體晶粒。 9. 如申請專利範圍第8項的方法，其進一步包含形成— 加固層在該應力緩和緩衝層與囊封劑:的上方。 10. 如申請專利範圍"項的方法，其中，該應力緩和 緩衝層比半導體晶粒或組件還薄。 11. 如申請專利範圍第8項的方法，其進一步包含形成 一電路層在該應力緩和緩衝層裡面。 12. —種製造半導體裝置的方法，其包括： 提供一暫時性基板； 固疋一半導體晶粒或組件至該暫.時性基板； 固定一應力緩和緩衝層至該暫時性基板；以及 沉積一囊封劑於該應力緩和緩衝層及半導體晶粒或組 件之間。 201125051 13·如申請專利範圍第12項的方&，其進—步包含： 移除該暫時性基板；以及 形成互連，纟°構於该半導體晶粒與應力緩和緩衝層的 上方’該互連結構會被電連接至該半導體晶粒或組件。 14. 如申請專利範圍第12項的方法，其進—步包含形成 該應力緩和緩衝層在被指定用於形成凸塊的位置中。 15, 如申請專利範圍第12項的方法，其中，該應力緩和 緩衝層包含一多層合成材料。 …16·如中π專利範圍第12項的方法，其中，形成該應力 和编^齡層包含： 形成一第一順從層； 形成一加固層於該第一順從層上方；以及 形成一第二順從層於該加固層的上方。 7.如申。月專利範圍第12項的方法，其進一步包含形成 一加固層在該應力緩和緩衝層與囊封劑的上方。 18. 如申請專利範圍第12項的方法其中，該應力緩和 緩衝層比半導體晶粒或組件還薄。 19. 如申請專利範圍第12項的方法，其進一步包含形成 電路層在该應力緩和緩衝層裡面。 20. —種半導體裝置，其包括： 半導體晶粒或組件； 被设置在該半導體晶粒或組件周圍的應力緩和緩衝 層； 囊封劑，其會被設置在該應力緩和緩衝層及半導體 31 201125051 晶粒或組件之間；以及 一互連結構’其會被形成在該半導體晶粒或組件及應 力緩和緩衝層的上方’該互連結構會被電連接至該半導體 晶粒或組件。 2 1 ·如申請專利範圍第2〇項的半導體裝置，其中，該應 力缓和緩衝層會被設置在被指定用於形成凸塊的位置中。 22.如申請專利範圍第2〇項的半導體裝置，其中，該應 力緩和缓衝層包含一多層合成材料。 23. 如申請專利範圍第2〇項的半導體裝置，其進一步包 含一被形成在該應力緩和緩衝層與囊封劑上方的加固層。 24. 如申請專利範圍第2G項的半導體裝置，其中，該應 力緩和緩衝層比半導體晶粒或組件還薄。 25.如申請專利範圍第2〇項的半導體裝置，其進一步包 含一位於該應力緩和緩衝層裡面的電路層。 八、圖式： (如次頁） S 32
TW099135402A 2009-11-25 2010-10-18 半導體裝置及形成順從的應力緩和緩衝層於大型陣列晶圓級晶片尺度封裝周圍之方法 TWI511211B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US12/625,975 US8034661B2 (en) 2009-11-25 2009-11-25 Semiconductor device and method of forming compliant stress relief buffer around large array WLCSP

Publications (2)

Publication Number Publication Date
TW201125051A true TW201125051A (en) 2011-07-16
TWI511211B TWI511211B (zh) 2015-12-01

Family

ID=44061491

Family Applications (1)

Application Number Title Priority Date Filing Date
TW099135402A TWI511211B (zh) 2009-11-25 2010-10-18 半導體裝置及形成順從的應力緩和緩衝層於大型陣列晶圓級晶片尺度封裝周圍之方法

Country Status (4)

Country Link
US (3) US8034661B2 (zh)
CN (1) CN102082102B (zh)
SG (2) SG171522A1 (zh)
TW (1) TWI511211B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10056349B2 (en) 2014-08-20 2018-08-21 Amkor Technology, Inc. Manufacturing method of semiconductor device and semiconductor device thereof

Families Citing this family (63)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9875911B2 (en) * 2009-09-23 2018-01-23 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming interposer with opening to contain semiconductor die
US9202769B2 (en) 2009-11-25 2015-12-01 Stats Chippac, Ltd. Semiconductor device and method of forming thermal lid for balancing warpage and thermal management
US8034661B2 (en) * 2009-11-25 2011-10-11 Stats Chippac, Ltd. Semiconductor device and method of forming compliant stress relief buffer around large array WLCSP
US8258633B2 (en) * 2010-03-31 2012-09-04 Infineon Technologies Ag Semiconductor package and multichip arrangement having a polymer layer and an encapsulant
US8535989B2 (en) * 2010-04-02 2013-09-17 Intel Corporation Embedded semiconductive chips in reconstituted wafers, and systems containing same
US8518746B2 (en) 2010-09-02 2013-08-27 Stats Chippac, Ltd. Semiconductor device and method of forming TSV semiconductor wafer with embedded semiconductor die
US8946890B2 (en) * 2010-10-20 2015-02-03 Marvell World Trade Ltd. Power/ground layout for chips
US9030019B2 (en) * 2010-12-14 2015-05-12 Infineon Technologies Ag Semiconductor device and method of manufacture thereof
US8937382B2 (en) 2011-06-27 2015-01-20 Intel Corporation Secondary device integration into coreless microelectronic device packages
US8848380B2 (en) 2011-06-30 2014-09-30 Intel Corporation Bumpless build-up layer package warpage reduction
US20150124415A1 (en) * 2011-07-12 2015-05-07 Aliphcom Protective covering for wearable devices
US8828846B2 (en) * 2011-07-26 2014-09-09 Atmel Corporation Method of computing a width of a scribe region based on a bonding structure that extends into the scribe reigon in a wafer-level chip scale (WLCSP) packaging
US9064883B2 (en) 2011-08-25 2015-06-23 Intel Mobile Communications GmbH Chip with encapsulated sides and exposed surface
US20130049214A1 (en) * 2011-08-29 2013-02-28 Infineon Technologies Ag Method of processing at least one die and die arrangement
US8664756B2 (en) 2012-07-24 2014-03-04 Medtronic, Inc. Reconstituted wafer package with high voltage discrete active dice and integrated field plate for high temperature leakage current stability
WO2013048620A1 (en) * 2011-09-30 2013-04-04 Medtronic, Inc. Reconstituted wafer package with high voltage discrete active dice and integrated field plate for high temperature leakage current stability
US20130249073A1 (en) * 2012-03-22 2013-09-26 Hsin Hung Chen Integrated circuit packaging system with support structure and method of manufacture thereof
JP2013214568A (ja) * 2012-03-30 2013-10-17 Fujitsu Ltd 配線基板及び配線基板の製造方法
US8703542B2 (en) * 2012-05-18 2014-04-22 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer-level packaging mechanisms
CN104321864B (zh) 2012-06-08 2017-06-20 英特尔公司 具有非共面的、包封的微电子器件和无焊内建层的微电子封装
TWI473217B (zh) * 2012-07-19 2015-02-11 矽品精密工業股份有限公司 半導體封裝件及其製法
US9385102B2 (en) 2012-09-28 2016-07-05 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming supporting layer over semiconductor die in thin fan-out wafer level chip scale package
TWI545702B (zh) * 2012-10-25 2016-08-11 矽品精密工業股份有限公司 半導體封裝件及其製法
US9202782B2 (en) * 2013-01-07 2015-12-01 Intel Corporation Embedded package in PCB build up
US20140284040A1 (en) * 2013-03-22 2014-09-25 International Business Machines Corporation Heat spreading layer with high thermal conductivity
US8878350B1 (en) * 2013-04-12 2014-11-04 Maxim Integrated Products, Inc. Semiconductor device having a buffer material and stiffener
TWI509749B (zh) * 2013-05-20 2015-11-21 矽品精密工業股份有限公司 半導體封裝件之製法
KR102123039B1 (ko) * 2013-07-19 2020-06-15 니치아 카가쿠 고교 가부시키가이샤 발광 장치 및 그 제조 방법
US9673364B2 (en) * 2013-07-19 2017-06-06 Nichia Corporation Light emitting device and method of manufacturing the same
US9530762B2 (en) * 2014-01-10 2016-12-27 Taiwan Semiconductor Manufacturing Company Limited Semiconductor package, semiconductor device and method of forming the same
JP6318844B2 (ja) * 2014-05-20 2018-05-09 日亜化学工業株式会社 発光装置
US9355968B2 (en) * 2014-06-13 2016-05-31 Maxim Integrated Products, Inc. Silicon shield for package stress sensitive devices
US9978700B2 (en) 2014-06-16 2018-05-22 STATS ChipPAC Pte. Ltd. Method for building up a fan-out RDL structure with fine pitch line-width and line-spacing
DE102015100771B4 (de) * 2015-01-20 2022-05-05 Infineon Technologies Ag Chipträgerlaminat mit Hochfrequenzdielektrikum und thermomechanischem Dämpfer
US10043769B2 (en) 2015-06-03 2018-08-07 Micron Technology, Inc. Semiconductor devices including dummy chips
US9761540B2 (en) * 2015-06-24 2017-09-12 Micron Technology, Inc. Wafer level package and fabrication method thereof
US9741620B2 (en) 2015-06-24 2017-08-22 Invensas Corporation Structures and methods for reliable packages
TW201701429A (zh) * 2015-06-24 2017-01-01 華亞科技股份有限公司 晶圓級封裝及其製作方法
US9449935B1 (en) * 2015-07-27 2016-09-20 Inotera Memories, Inc. Wafer level package and fabrication method thereof
US9691637B2 (en) * 2015-10-07 2017-06-27 Nxp Usa, Inc. Method for packaging an integrated circuit device with stress buffer
US20170170087A1 (en) * 2015-12-14 2017-06-15 Intel Corporation Electronic package that includes multiple supports
US9842828B1 (en) 2016-06-13 2017-12-12 Stmicroelectronics, Inc. Stacked semiconductor package with compliant corners on folded substrate
US20180182682A1 (en) * 2016-12-25 2018-06-28 Powertech Technology Inc. Semiconductor device package with stress relief layer
US10249573B2 (en) 2017-03-16 2019-04-02 Powertech Technology Inc. Semiconductor device package with a stress relax pattern
US10461060B2 (en) * 2017-05-31 2019-10-29 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and formation method of chip package with redistribution layers
US9947634B1 (en) * 2017-06-13 2018-04-17 Northrop Grumman Systems Corporation Robust mezzanine BGA connector
CN107241853A (zh) * 2017-06-29 2017-10-10 广州兴森快捷电路科技有限公司 一种屏蔽型刚挠结合板及其制造方法
US10276551B2 (en) * 2017-07-03 2019-04-30 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device package and method of forming semiconductor device package
TWI645523B (zh) * 2017-07-14 2018-12-21 矽品精密工業股份有限公司 封裝結構及其製法
US11152274B2 (en) * 2017-09-11 2021-10-19 Advanced Semiconductor Engineering, Inc. Multi-moldings fan-out package and process
US11562935B2 (en) * 2017-11-07 2023-01-24 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure
US10431534B2 (en) 2017-12-11 2019-10-01 Nxp Usa, Inc. Package with support structure
US11127604B2 (en) * 2018-01-05 2021-09-21 Innolux Corporation Manufacturing method of semiconductor device
US10854527B2 (en) 2018-05-25 2020-12-01 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method of manufacturing the same
WO2020142989A1 (en) * 2019-01-10 2020-07-16 Yangtze Memory Technologies Co., Ltd. Structures and methods for reducing stress in three-dimensional memory device
CN109803523B (zh) * 2019-02-23 2021-01-29 华为技术有限公司 一种封装屏蔽结构及电子设备
US10999919B2 (en) 2019-07-11 2021-05-04 Toyota Motor Engineering & Manufacturing North America, Inc. Flexible electronic assembly for placement on a vehicle motor assembly
CN110494012B (zh) * 2019-07-29 2023-08-04 常州澳弘电子股份有限公司 一种埋嵌电阻pcb板
KR102543996B1 (ko) * 2019-09-20 2023-06-16 주식회사 네패스 반도체 패키지 및 이의 제조방법
US11217498B2 (en) 2019-11-01 2022-01-04 Advanced Semiconductor Engineering, Inc. Semiconductor package and manufacturing method of the same
TWI756000B (zh) * 2020-12-28 2022-02-21 欣興電子股份有限公司 晶片封裝結構及其製作方法
CN113035831A (zh) * 2021-05-25 2021-06-25 甬矽电子(宁波)股份有限公司 晶圆级芯片封装结构及其制作方法和电子设备
CN114512464B (zh) * 2022-04-19 2022-08-02 甬矽半导体(宁波)有限公司 扇出型封装结构和扇出型封装结构的制备方法

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5250843A (en) * 1991-03-27 1993-10-05 Integrated System Assemblies Corp. Multichip integrated circuit modules
US5353498A (en) * 1993-02-08 1994-10-11 General Electric Company Method for fabricating an integrated circuit module
JPH0846098A (ja) 1994-07-22 1996-02-16 Internatl Business Mach Corp <Ibm> 直接的熱伝導路を形成する装置および方法
US5866952A (en) * 1995-11-30 1999-02-02 Lockheed Martin Corporation High density interconnected circuit module with a compliant layer as part of a stress-reducing molded substrate
US5841193A (en) * 1996-05-20 1998-11-24 Epic Technologies, Inc. Single chip modules, repairable multichip modules, and methods of fabrication thereof
US6011304A (en) 1997-05-05 2000-01-04 Lsi Logic Corporation Stiffener ring attachment with holes and removable snap-in heat sink or heat spreader/lid
US5835355A (en) * 1997-09-22 1998-11-10 Lsi Logic Corporation Tape ball grid array package with perforated metal stiffener
TWI256095B (en) * 2004-03-11 2006-06-01 Siliconware Precision Industries Co Ltd Wafer level semiconductor package with build-up layer and process for fabricating the same
US7015577B2 (en) 2004-07-21 2006-03-21 Advanced Semiconductor Engineering, Inc. Flip chip package capable of measuring bond line thickness of thermal interface material
CN100585839C (zh) * 2005-12-31 2010-01-27 财团法人工业技术研究院 芯片封装结构与芯片封装工艺
US20070278671A1 (en) * 2006-06-02 2007-12-06 Powertech Technology Inc. Ball grind array package structure
US7397127B2 (en) * 2006-10-06 2008-07-08 Taiwan Semiconductor Manufacturing Co., Ltd. Bonding and probing pad structures
US7432601B2 (en) * 2006-10-10 2008-10-07 Powertech Technology Inc. Semiconductor package and fabrication process thereof
US20080237855A1 (en) * 2007-03-28 2008-10-02 Powertech Technology Inc. Ball grid array package and its substrate
US7619901B2 (en) * 2007-06-25 2009-11-17 Epic Technologies, Inc. Integrated structures and fabrication methods thereof implementing a cell phone or other electronic system
US7868446B2 (en) * 2007-09-06 2011-01-11 Infineon Technologies Ag Semiconductor device and methods of manufacturing semiconductor devices
US20090096093A1 (en) * 2007-10-15 2009-04-16 Advanced Chip Engineering Technology Inc. Inter-connecting structure for semiconductor package and method of the same
US7906860B2 (en) * 2007-10-26 2011-03-15 Infineon Technologies Ag Semiconductor device
US7745260B2 (en) * 2008-09-22 2010-06-29 Freescale Semiconductor, Inc. Method of forming semiconductor package
US8013438B2 (en) 2009-07-21 2011-09-06 Stmicroelectronics Asia Pacific Pte. Ltd. Semiconductor package with a stiffening member supporting a thermal heat spreader
US8021930B2 (en) 2009-08-12 2011-09-20 Stats Chippac, Ltd. Semiconductor device and method of forming dam material around periphery of die to reduce warpage
US8034661B2 (en) * 2009-11-25 2011-10-11 Stats Chippac, Ltd. Semiconductor device and method of forming compliant stress relief buffer around large array WLCSP

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10056349B2 (en) 2014-08-20 2018-08-21 Amkor Technology, Inc. Manufacturing method of semiconductor device and semiconductor device thereof
TWI659477B (zh) * 2014-08-20 2019-05-11 美商艾馬克科技公司 半導體裝置及其製造方法
US11031370B2 (en) 2014-08-20 2021-06-08 Amkor Technology Singapore Holding Pte. Ltd. Semiconductor device and manufacturing method thereof
US11901332B2 (en) 2014-08-20 2024-02-13 Amkor Technology Singapore Holding Pte. Ltd. Semiconductor device and manufacturing method thereof

Also Published As

Publication number Publication date
US9508621B2 (en) 2016-11-29
US8912648B2 (en) 2014-12-16
US8034661B2 (en) 2011-10-11
SG183777A1 (en) 2012-09-27
CN102082102B (zh) 2015-09-09
US20150145126A1 (en) 2015-05-28
SG171522A1 (en) 2011-06-29
CN102082102A (zh) 2011-06-01
US20110121449A1 (en) 2011-05-26
US20120001325A1 (en) 2012-01-05
TWI511211B (zh) 2015-12-01

Similar Documents

Publication Publication Date Title
TW201125051A (en) Semiconductor device and method of forming compliant stress relief buffer around large array WLCSP
TWI479577B (zh) 形成屏障材料於晶粒之周圍以減少翹曲之半導體裝置和方法
TWI508202B (zh) 雙重模造晶粒形成於增進互連結構之對邊上之半導體裝置和方法
TWI581345B (zh) 半導體裝置以及形成引線上接合互連用於鑲嵌半導體晶粒在扇出晶圓級晶片規模封裝中之方法
TWI502682B (zh) 半導體封裝及鑲嵌半導體晶粒至直通矽晶穿孔基板的對邊之方法
US9847324B2 (en) Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP
TWI499000B (zh) 形成雙主動邊之半導體晶粒於扇出晶圓程度晶粒級封裝之半導體裝置和方法
TWI557872B (zh) 半導體裝置及用於形成具有垂直互連之薄剖面wlcsp於封裝覆蓋區的方法
TWI508226B (zh) 在基板的孔穴中鑲嵌具有直通矽晶穿孔的晶粒用以扇入封裝疊加的電互連之半導體裝置和方法
TWI553794B (zh) 半導體裝置及在膠封期間形成黏著材料於半導體晶粒和載體上以減少晶粒位移之方法
TWI528465B (zh) 半導體元件和形成具有嵌入半導體晶粒的預先製備散熱框之方法
US9263332B2 (en) Semiconductor device and method of forming open cavity in TSV interposer to contain semiconductor die in WLCSMP
CN102543772B (zh) 结合晶片级不同尺寸半导体管芯的方法和半导体器件
TWI538131B (zh) 形成在半導體晶粒的接觸墊上的晶種層上方的互連結構而在互連結構下方無底切的晶種層之方法和半導體裝置
TWI552265B (zh) 形成孔穴於增進互連結構中以縮短晶粒之間訊號路徑之半導體裝置和方法
US8999760B2 (en) Semiconductor device and method of forming thermally conductive layer between semiconductor die and build-up interconnect structure
TWI531011B (zh) 使用相同的載體在ｗｌｃｓｐ中形成ｔｍｖ和ｔｓｖ的半導體裝置及方法
TWI538070B (zh) 半導體裝置及形成具有由聚合物層隔開的導電層和導電通路之扇出式晶圓級晶片尺寸封裝的方法
TWI553811B (zh) 在具有不同熱膨脹係數的絕緣層之半導體晶粒上方形成具有組合互連結構的半導體封裝之半導體裝置及方法
TWI602262B (zh) 形成穿過互連結構和ｗｌｃｓｐ的封膠的導電通孔之半導體裝置及方法
TWI570820B (zh) 半導體元件和在晶粒及互連結構之間形成應力減輕層之方法
TWI518811B (zh) 半導體裝置及以多層凸塊底層金屬形成凸塊結構於凸塊形成區周圍之方法
TWI520287B (zh) 半導體裝置以及形成沿著第一軸較寬於接觸墊並且沿著第二軸較窄於接觸墊之重新分配層的方法
TW201327744A (zh) 半導體裝置和形成具有扇出互連結構以減少基板複雜性之擴大的半導體裝置之方法