TW201115697A - Semiconductor device - Google Patents

Semiconductor device Download PDF

Info

Publication number
TW201115697A
TW201115697A TW099115842A TW99115842A TW201115697A TW 201115697 A TW201115697 A TW 201115697A TW 099115842 A TW099115842 A TW 099115842A TW 99115842 A TW99115842 A TW 99115842A TW 201115697 A TW201115697 A TW 201115697A
Authority
TW
Taiwan
Prior art keywords
conductor
film
wiring layer
layer
barrier
Prior art date
Application number
TW099115842A
Other languages
English (en)
Chinese (zh)
Inventor
Takeshi Furusawa
Takao Kamoshima
Hiroki Takewaka
Original Assignee
Renesas Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Electronics Corp filed Critical Renesas Electronics Corp
Publication of TW201115697A publication Critical patent/TW201115697A/zh

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/27—Structural arrangements therefor
    • H10P74/273—Interconnections for measuring or testing, e.g. probe pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/425—Barrier, adhesion or liner layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5525—Materials of bond wires comprising metals or metalloids, e.g. silver comprising copper [Cu]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/59—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/923—Bond pads having multiple stacked layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/923—Bond pads having multiple stacked layers
    • H10W72/9232—Bond pads having multiple stacked layers with additional elements interposed between layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/951—Materials of bond pads
    • H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/981—Auxiliary members, e.g. spacers
    • H10W72/983—Reinforcing structures, e.g. collars

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)
TW099115842A 2009-06-16 2010-05-18 Semiconductor device TW201115697A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2009143133A JP2011003578A (ja) 2009-06-16 2009-06-16 半導体装置

Publications (1)

Publication Number Publication Date
TW201115697A true TW201115697A (en) 2011-05-01

Family

ID=43305653

Family Applications (1)

Application Number Title Priority Date Filing Date
TW099115842A TW201115697A (en) 2009-06-16 2010-05-18 Semiconductor device

Country Status (4)

Country Link
US (1) US20100314620A1 (https=)
JP (1) JP2011003578A (https=)
CN (1) CN101924089A (https=)
TW (1) TW201115697A (https=)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8603909B2 (en) * 2009-11-05 2013-12-10 Globalfoundries Singapore Pte. Ltd. Integrated circuit packaging system with core region and bond pad and method of manufacture thereof
JP5772926B2 (ja) * 2013-01-07 2015-09-02 株式会社デンソー 半導体装置
JP2016004877A (ja) * 2014-06-16 2016-01-12 ルネサスエレクトロニクス株式会社 半導体装置および電子装置
US9620460B2 (en) 2014-07-02 2017-04-11 Samsung Electronics Co., Ltd. Semiconductor chip, semiconductor package and fabricating method thereof
JP2016139711A (ja) * 2015-01-28 2016-08-04 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JP6524730B2 (ja) * 2015-03-17 2019-06-05 セイコーエプソン株式会社 半導体装置
CN108140577B (zh) * 2016-02-23 2022-09-09 瑞萨电子株式会社 半导体器件及其制造方法
JP6649189B2 (ja) * 2016-06-27 2020-02-19 ルネサスエレクトロニクス株式会社 半導体装置
JP2018137344A (ja) * 2017-02-22 2018-08-30 ルネサスエレクトロニクス株式会社 半導体装置及びその製造方法
KR102576062B1 (ko) * 2018-11-07 2023-09-07 삼성전자주식회사 관통 실리콘 비아를 포함하는 반도체 소자 및 그 제조 방법
KR102807501B1 (ko) * 2019-10-02 2025-05-16 삼성전자주식회사 두꺼운 금속층을 갖는 반도체 소자들
JP2020061580A (ja) * 2020-01-16 2020-04-16 ルネサスエレクトロニクス株式会社 半導体装置
WO2024042698A1 (ja) * 2022-08-26 2024-02-29 株式会社ソシオネクスト 半導体集積回路装置

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6727593B2 (en) * 2001-03-01 2004-04-27 Kabushiki Kaisha Toshiba Semiconductor device with improved bonding
JP2003031575A (ja) * 2001-07-17 2003-01-31 Nec Corp 半導体装置及びその製造方法
JP2003218114A (ja) * 2002-01-22 2003-07-31 Toshiba Corp 半導体装置及びその製造方法
US7319277B2 (en) * 2003-05-08 2008-01-15 Megica Corporation Chip structure with redistribution traces
JP4998262B2 (ja) * 2005-07-05 2012-08-15 富士通セミコンダクター株式会社 半導体装置及びその製造方法
JP4639138B2 (ja) * 2005-10-28 2011-02-23 パナソニック株式会社 半導体装置
JP2009021528A (ja) * 2007-07-13 2009-01-29 Toshiba Corp 半導体装置
JP5027605B2 (ja) * 2007-09-25 2012-09-19 パナソニック株式会社 半導体装置
JP5205066B2 (ja) * 2008-01-18 2013-06-05 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JP5443827B2 (ja) * 2009-05-20 2014-03-19 ルネサスエレクトロニクス株式会社 半導体装置

Also Published As

Publication number Publication date
US20100314620A1 (en) 2010-12-16
JP2011003578A (ja) 2011-01-06
CN101924089A (zh) 2010-12-22

Similar Documents

Publication Publication Date Title
TW201115697A (en) Semiconductor device
JP5205066B2 (ja) 半導体装置およびその製造方法
JP4170103B2 (ja) 半導体装置、および半導体装置の製造方法
US9754912B2 (en) Electronic device and method for production
JP5559775B2 (ja) 半導体装置およびその製造方法
TWI336920B (en) Pad structure and forming method of the same
CN100517668C (zh) 接合垫结构
JP2008258258A (ja) 半導体装置
TW201246487A (en) Semiconductor device and manufacturing method thereof
US9053973B2 (en) Semiconductor device
TW200924094A (en) Semiconductor device having bonding pad above low-k dielectric film and manufacturing method therefor
KR20050001337A (ko) 반도체장치
JP2018206938A (ja) 半導体装置およびその製造方法
US20090176124A1 (en) Bonding pad structure and semiconductor device including the bonding pad structure
CN100587947C (zh) 半导体元件及其制造方法
JP2005142351A (ja) 半導体装置およびその製造方法
US7026547B1 (en) Semiconductor device and a method for fabricating a semiconductor device
JP2012227379A (ja) 半導体装置および半導体装置の製造方法
JP5564557B2 (ja) 半導体装置
TWI316741B (en) Method for forming an integrated cricuit, method for forming a bonding pad in an integrated circuit and an integrated circuit structure
TW200402861A (en) Semiconductor integrated device
TWI225288B (en) Chip structure
JP4663510B2 (ja) 半導体装置
JP4701264B2 (ja) 半導体装置、および半導体装置の製造方法
JP2005327763A (ja) 半導体装置