TW201113998A - Semiconductor package with sectioned bonding wire scheme - Google Patents

Semiconductor package with sectioned bonding wire scheme Download PDF

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Publication number
TW201113998A
TW201113998A TW098139349A TW98139349A TW201113998A TW 201113998 A TW201113998 A TW 201113998A TW 098139349 A TW098139349 A TW 098139349A TW 98139349 A TW98139349 A TW 98139349A TW 201113998 A TW201113998 A TW 201113998A
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TW
Taiwan
Prior art keywords
semiconductor
pad
dummy
wire
bonding
Prior art date
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TW098139349A
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English (en)
Inventor
Jen-Chung Chen
Original Assignee
Nanya Technology Corp
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Application filed by Nanya Technology Corp filed Critical Nanya Technology Corp
Publication of TW201113998A publication Critical patent/TW201113998A/zh

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Description

201113998 六、發明說明： 【發明所屬之技術領域】 本發明係有關於半導體封裝技術領域，特別是有關於一種改良之 半導體積體電路封裝構件，採用分段金線架構，如此使金線有較強 的強度支撐，避免模流沖擊造成金線脫落的問題。 【先前技術】 動鑛機躲記紐(DRAM)主要是朝献冑容量絲效能兩 個方向發展。單H DRAM的封裝肋魏，在追求冑魏的方向發 展上，以最短的内部路徑配合二維系統單晶片（2 dimensi〇nai
SyStem，〇n-Chip或2D_S0C)解決方案為主。但是s〇c架構下的 =RAM ’其在雜高容量的需求部分，卻麟不足^為了達成高容 量的需求’鮮於是發展出各仙議堆疊封裝技術，例如，打線 接合(Stack by wire bond)、層疊封裝(Package_〇n Package)、線路重佈 技術(膨WifebGnd)、垂封連接製簡術inte_ecti〇n Pr_s) '金線金線内連接技術(G〇w t〇 a〗伽⑽_細GGI) 與 PiP (Package in Package)製程技術。 如熟習該徹藝者所知，封裝的魏在於保路及晶片避免受 到外界的外力、灰塵、化學性的侵鱗因素的干擾，及規則化、尺 201113998 寸匹配等功能，並維持電路能正常運作。封裝佔整個電子封果梦造 成本很大的比例’因此設計封裳不健只是挑選一種樣式精組 裝’而要考慮到更多系統整合之後的因素。此外，由於電子封裝產 口口尺寸的縮小，造成晶片線路密集化及線路直徑細小化細小化的 結果產生了許多問題如電磁干擾、高溫、熱應力等問題。因此在設 计其型式、結構尺寸及材料選用時，都必須審慎選擇設計，以避免 電子封裝產品在封裝的製造過程中產生損壞或在使用階段的可靠度 問題等。 目前主流的DRAM規格已由DDIU、DDR2快速的被DDR3取 代，在高速、倍頻的要求下，汇封裝體的j/〇數也勢必增加。採用 打線接δ製程的3D堆疊封裝，由於互連路徑長度較長，在封裝模 封製程中，受模封材料(m〇ldingc〇mp〇und)的模流路徑限制，常遇到 沖線(bondingwiresweep)問題，這是因為當模流的路徑與金線方向 不一致，金線受到模封材料的衝擊，導致金線脫落，金線脫離產生 訊號線短路或斷路的結果，使產品電性失效。隨著DRAM容量需求 增加’ I/O數勢必持續上升；此需求除了使金線數目增加，同時金 線互連路徑長度也較長；當金線密度與長度增加，模封製程中 (molding process)，模封材料(molding compound)的沖線問題也愈來 愈嚴苛，亦愈來愈重要。 過去為解決沖線的問題’有人利用CAD輔助模流分析’藉此改 善流道(runner)及模穴(moldchase)設計’藉CAD達到模穴最佳化設 201113998 计，改善並避餅線問題的發生。也詞用—膠固定金線的方式， 解決沖線的醜，此方法是在打線前，使賴膠機將^^膠塗佈在 晶片適當驗置， uv光騎膠，使膠反應成為B_stage狀態， 具適當的黏性’此時再進行打線製程，因金線被⑽膠固所以， 在模封lUit，β卩使模封材料(MGldingQ)mpGun_模流路獲與金 線方向完全不-致’也不會使金線脫落。然而，上述模穴設計與模 μ刀析的時間與成本高，轉^^膠固定金線的方式職額外製程 φ或设備，及加工的時間，且UV膠的材料費用也不便宜。 【發明内容】 本發明之主要目的在提供一種採用分段金線架構及晶片上假接 塾之新穎半導體封裝構件，使金線有較強的強度支樓，有效的避免 模流沖擊造成金線脫落的問題。 ❿ 根據本發明一較佳實施例，本發明提供一種半導體封裝構件，包 含有-基板，其上設有至少一打線手指；一半導體晶片，設於該基 板的上表面；至少一主動接合塾，設於該半導體晶片上；至少一假 接塾，a又於該半導體晶片上；一第一接合導線 ，電連接該至少一主 動接合塾與該至少-假接墊；一第二接合導線，電連接該至少一假 接塾與該至少-打線手指；以及一膜封材料，包覆住至少該半 晶片。 201113998 根據本發明之另-較佳實施例，本發明提供一種半導體封裝構 件，包含有-基板，其上設有至少一打線手指；一晶片堆疊結構， 包含有-第-半導體晶片設於該基板的上表面，以及一第二半導體 :片’堆®在該第-半導體晶片上；至少—主動接合墊設於該第 二半導體晶壯；至少-假接墊，設於該第二半導體晶片上，· -接合導線’電連接該至少―主動接合塾與該至少—假接塾·一第 二接合導線，電連接該至少―假接墊與該至少—打線手指，·以及一 膜封材料，包覆住至少該晶片堆疊結構。 為讓本發明之上述目的、特徵及優點能更明顯易懂，下文特舉較 佳實施方式，並配合所_式，作詳細說明如下。然而如下之較佳 實施方式與圖式僅供參考與說明用，並非用來對本發明加以限制者。 【實施方式】 口月參閱第1圖，其為依據本發明一較佳實施例所繪示的半導體封 裝構件的上視示意圖。如第丨圖所示，半導體封裝構件&包括一基 板1〇 ’例如封裝基板，在基板10的上表面設有一半導體晶片2〇， 以及-膜封材料3G，其至少包覆住半導體晶片2〇。 根據本發明之較佳實施例，在基板1〇的上表面提供有至少兩排 姻手指12a_12d及14a_14d。根據本發明之較佳實施例，打線手 日12a-12d係在半導體“ 2G的—側邊沿著參考y軸排成一直線， 201113998 而打線手指14a-14d在半導體晶片20的相對於打線手指仏损的 另一側邊沿著參考y軸排成一直線。 根據本發明之較佳實施例，在半導體晶片2〇的主動面的中央位 置設有複數個排成單排的主動接合塾22a_22h。根據本發明之較佳實 ^十單排的主動接合塾22a_22h在半導體晶片2〇的中央位置同樣 是沿著參考y軸排列成一直線，也就是說，單排的主動接合墊 鲁22a-22h與半|^體晶片20兩側邊的兩排打線手指以⑶及 是平行排列的。 本發明的概在於在半導體⑼2G牡動面上另包含有兩排的 假接墊(drnnrnybondp—m-md及ma-114d，同樣的，這兩排 假接塾ma-md及1Ma··均沿著參考y軸各排列成一直線其 中’從上視圖來看’單排的假接塾112a_112d係位於單排的主動接 合墊Da-22h以及打線手指12a_12d之間，單排的假接墊li4a_md _位於單排的主動接合墊22a_22h以及打線手指之間。這兩排 假接塾112a-112d及114a-114d係在電性上為浮置的(electrically floating)接塾’且在製程上，係與主動接合塾22心2迚同時製作。其 中’「電性上為浮置的」指的是假接墊112a U2d及114a ll4d並未 與半導體晶片20的内部主動電路有所連結。 根據本發明之較佳實施例，各個假接墊112a ll2d及114a ll4d 的尺寸大小需大於各個主動接合墊22a 22h的尺寸大小。較佳者， 201113998 各個假接墊112a-112d及114a-114d需提供同時足夠容納兩條金線的 打線接合面積。舉例來說，各個假接墊112a-112d及114a-114d的面 積約為100μιη><60μιη，各個主動接合墊22a-22h的面積約為 50μηιχ60/«η 左右。 根據本發明之較佳實施例，複數條接合導線32a_32d係分別用來 電連結主動接合墊22b、22d、22f、22h及相對應的假接墊1丨2a_丨丨2d， 複數條接合導線42a-42d則分別用來電連結假接塾iDa-lUd及相對 應的打線手指12a-12d。同樣的，根據本發明之較佳實施例，複數條 接合導線34a-34d係分別用來電連結主動接合墊22a、22c、22e、22g 及相對應的假接墊114a-114d，複數條接合導線44a_44d則分別用來 電連結假接墊114a-114d及相對應的打線手指14a_14d。其中，接合 導線32a-32d、3%-34<1、42a-42d及44a-44d可以是金線或銅線。 請參閱第2A圖及第2B圖，其中第2A圖為依據本發明另一較 佳實施例所繪示的王維⑽半導體封裝構件的上視示意圖，第 圖為沿著第2A圖切線：[-：[，所視的剖面示意圖。如第2A圖及第2b 圖所示，半導體封裝構件包括基板10，例如封裝基板，在基板 的上表面1〇1設有-晶片堆疊結構·，包括一上晶片施以及 一下晶片2_，以及-膜封材料30,包覆住至少晶片堆疊結構勝 在基板K)的上表面101提供有至少兩排的打線手指12及14。 根據本發明之較佳實施例，㈣手指12勉晶片堆疊結構的一 201113998 :邊沿者參考y軸排成-直線，而打線手指M在晶片堆疊結構· 、相對於打線手指丨2的另一侧邊沿著參考以排成一直線。在基板 10的中央位置設有-長條型開孔1〇ae在基板1〇的下表面⑴2沿著 長條型· IGa姆兩長邊另提财兩制打線手指232及说。 其中’打線手指232及234靠近長條型開孔1〇a。在基板1〇的下表 面1〇2另提供有陣列錫球μ。第M圖及第沈圖所示的半導體封 裝構件又被稱為窗型BGA封裝或者wBGA封裝。 根據本發狀雛f施例，下晶# 2_具有—面向絲ι〇上表 面101的主動接合面’而在下晶片200b的主動接合面上的中央位置 提供有兩排的接合塾222a及222b。魏條接合導線232及234則 用來分別電連結在下晶片200b上的接合塾222a及222b以及相對應 的打線手指212及214。其中，接合墊222a及222b、接合導線232 及234、打線手指212及214係被包覆在膜封材料3〇内，且膜封材 料填滿長條型開孔l〇a。 根據本發明之較佳實_，在上晶片綱a另提供制成兩排的 接合塾122a]22b。根據本發明之較佳實施例，_成單排的接合墊 122a係彼此對準成-直線，且排職單漏接合塾咖係與兩排 打線手指12及14平行排列。此外’上晶片聽尚包含有排列成兩 排的假接墊124a及124b。 假接墊l24a係彼此對準排成一直線，且從上視圖來看使排成 201113998 單排的假接墊124a設於單排的接合墊122a與單排的打線手指14之 間。同樣的’假接塾124b係彼此對準排成一直線，且從上視圖來看， 使排成單排的假接墊124b設於單排的接合墊i22b與單排的打線手 指12之間。 根據本發明之較佳實施例，各個假接墊124a及124b的尺寸均大 於各個接合墊122a-122b的尺寸大小。較佳者，各個假接墊12如及 124b需具有同時足夠容納兩條金線的打線接合面積。舉例來說，各 個假接墊124a及124b的面積約為ΐΟΟμηρ^Ομιη，各個接合墊 儀 122a-122b 的面積約為 5〇μηΐχ60/>«η 左右。 根據本發明之較佳實施例’複數條接合導線132係分別用來電連 結接合塾122b及相對應的假接墊124b ’而複數條接合導線142則 分別用來電連結假接墊124b及相對應的打線手指12。根據本發明 之較佳實施例，同樣的，複數條接合導線134係分別用來電連結接 合墊122a及相對應的假接墊124a，複數條接合導線144則分別用 φ 來電連結假接墊124a及相對應的打線手指14。 本發明利用假接塾(dummy pad)的設計將金線由一長線路分成兩 段，使金線有較強的強度支撑，避免模流沖擊造成金線脫落的問題。 同樣地’此方法在模封製程中，即使模封材料的模流路徑與金線方 向完全不-致，也不會使金魏落。本發明的優點是在晶片設計時， 可設計於與接合墊同-層面，並於晶片金屬化製程中同時製造完 12 201113998 成，當在後段封料’節省敎設計賴流分析 比⑽膠製程省製程加工的時間及省uv材料的費用、成本；也 以上所述僅為本發明之較佳實施例，凡依本發 做之均等變化與_，皆應屬本發明之涵蓋範圍。她圍所 【圖式簡單說明】 第1圖為依據本發明-較佳實施例所繪示的半導體封裝構 示意圖。 第2A圖為依據本發明另-較佳實施例所緣示的三維半導體封震構 件的上視示意圖。 ~ 第2B圖為沿著第2A圖切線1-1’所視的剖面示意圖。 【主要元件符號說明】 la半導體封裝構件 lb半導體封裝構件 1〇基板 l〇a長條型開孔 12打線手指 14打線手指 16陣列錫球 13 201113998 12a-12d打線手指 14a-14d打線手指 20半導體晶片 22a-22h主動接合墊 30膜封材料 32a-32d接合導線 34a-34d接合導線 42a-42d接合導線 44a-44d接合導線 101上表面 102下表面 112a-112d假接墊 114a-114d假接墊 122a接合墊 122b接合墊 124a假接墊 124b假接墊 132接合導線 134接合導線 142接合導線 144接合導線 200晶片堆疊結構 200a上晶片 201113998 200b下晶片 212打線手指 214打線手指 222a接合墊 222b接合墊 232打線手指 234打線手指

Claims (1)

  1. 201113998 七、申請專利範圍： 1. 一種半導體封裝構件，包含有： 一基板，其上設有至少一打線手指； 一半導體晶片’設於該基板的上表面； 至少一主動接合墊，設於該半導體晶片上； 至少一假接墊’設於該半導體晶片上； 一第一接合導線，電連接該至少一主動接合墊與該至少一假接 墊； 第一接合導線，電連接該至少一假接墊與該至少一打線手 以及 9 ’ 一膜封材料，包覆住至少該半導體晶片。 一假 2·如申請專利範圍第i項所述之半導體封轉件，其中該至+ 接墊的尺寸係大於縫少-絲接合_尺寸。 夕 ’其中該至少一假 3.如申請專利範圍第1項所述之半導體封裂構件 接塾的尺寸為100μηιχ60μιη。 件’其中該至少一主 4.如申請專利範圍第3項所述之半導體 動接合墊的尺寸為50μιηχ60μιη。 、 5. 如申請專利範圍第1項所述之轉體封農構件， 其中該至少一假 201113998 接墊具有樹賊第-、第二接合導㈣打線接合面積。 假 6.如申請專利範圍第i項所述之半導_ 接墊係在電性上為浮置。 、牛八中該至少一 7. —種半導體封裝構件，包含有： 一基板，其上設有至少一打線手指； 一晶片堆疊结構，包含有一第一半導 ^ 也此 卞等體日日片設於該基板的上袅 面，以及一第二半導體晶片，堆疊在該第一半導體晶片上表 至少一主動接合墊，設於該第二半導體晶片上；日日， 至少一假接墊，設於該第二半導體晶片上；’ 以及 塾；一第-接合轉，電連接該至少—主動接合塾與該至少一假接 第二接合轉，電連接該至少—假接塾與該至少一打線手指； 膜封材料，包覆住至少該晶片堆疊結構 8. 如申請專利範圍第7項所述之半導體封輯件，其中該至少一假 接墊的尺寸係大於該至少一主動接合墊的尺寸。 9.如申請專利範圍第7項所述之半導體封鶴件其中該至少一假 接塾的尺寸為1〇〇μπιχ6〇μιη。 201113998 10.如申請專利範園第9項所述之半導體封裝構件，其中該至少一主 動接合塾的尺寸為50μΐηχ60μιη。 11. 如申請專利範圍第7項所述之半導體封裝構件，其愧至少一假 接塾具有足夠容納該第一、第二接合導線的打線接合面積。又 12. 如申請專利範圍第7項所述之半導體封⑽件，其中該至少一假 接墊係在電性上為浮置。 又 連接 13.如申請專利範圍第7項所述之半導體封裝構件，其中該第 體晶片係經由縣板的1孔，以打線與縣板的—下表面構成電
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI458026B (zh) * 2012-01-13 2014-10-21 Dawning Leading Technology Inc 內嵌封裝體之封裝模組及其製造方法
TWI825828B (zh) * 2022-05-09 2023-12-11 南亞科技股份有限公司 窗型球柵陣列(wbga)封裝的製備方法

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104160550B (zh) * 2012-09-23 2019-01-11 Dsp集团有限公司 用于rf功率放大器的线性行阵列集成功率合成器
KR102247916B1 (ko) 2014-01-16 2021-05-04 삼성전자주식회사 계단식 적층 구조를 갖는 반도체 패키지
CN105609480B (zh) * 2015-12-24 2018-11-30 合肥矽迈微电子科技有限公司 叠层芯片封装结构
WO2018125163A1 (en) * 2016-12-29 2018-07-05 Intel Corporation Multi-point stacked die wirebonding for improved power delivery
US11069646B2 (en) * 2019-09-26 2021-07-20 Nanya Technology Corporation Printed circuit board structure having pads and conductive wire
US11362071B2 (en) * 2020-08-24 2022-06-14 Micron Technology, Inc. Stacked semiconductor dies for semiconductor device assemblies
CN112864121A (zh) * 2021-01-14 2021-05-28 长鑫存储技术有限公司 芯片结构、封装结构及其制作方法

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6329711B1 (en) * 1995-11-08 2001-12-11 Fujitsu Limited Semiconductor device and mounting structure
US5777345A (en) * 1996-01-03 1998-07-07 Intel Corporation Multi-chip integrated circuit package
JP3481444B2 (ja) * 1998-01-14 2003-12-22 シャープ株式会社 半導体装置及びその製造方法
JP3437477B2 (ja) * 1999-02-10 2003-08-18 シャープ株式会社 配線基板および半導体装置
JP3765952B2 (ja) * 1999-10-19 2006-04-12 富士通株式会社 半導体装置
JP2001127246A (ja) * 1999-10-29 2001-05-11 Fujitsu Ltd 半導体装置
JP2001196529A (ja) * 2000-01-17 2001-07-19 Mitsubishi Electric Corp 半導体装置及びその配線方法
JP2002043503A (ja) * 2000-07-25 2002-02-08 Nec Kyushu Ltd 半導体装置
JP3631120B2 (ja) * 2000-09-28 2005-03-23 沖電気工業株式会社 半導体装置
JP4780844B2 (ja) * 2001-03-05 2011-09-28 Ｏｋｉセミコンダクタ株式会社 半導体装置
JP3850325B2 (ja) * 2002-03-27 2006-11-29 株式会社東芝 マイクロ波集積回路
JP4146290B2 (ja) * 2003-06-06 2008-09-10 株式会社ルネサステクノロジ 半導体装置
JP2009038142A (ja) * 2007-07-31 2009-02-19 Elpida Memory Inc 半導体積層パッケージ
JP5628470B2 (ja) * 2007-12-04 2014-11-19 ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． 半導体装置
JP2010087403A (ja) * 2008-10-02 2010-04-15 Elpida Memory Inc 半導体装置
JP4776675B2 (ja) * 2008-10-31 2011-09-21 株式会社東芝 半導体メモリカード

Cited By (2)

* Cited by examiner, † Cited by third party
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TWI458026B (zh) * 2012-01-13 2014-10-21 Dawning Leading Technology Inc 內嵌封裝體之封裝模組及其製造方法
TWI825828B (zh) * 2022-05-09 2023-12-11 南亞科技股份有限公司 窗型球柵陣列(wbga)封裝的製備方法

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