TW201108394A - Field effect transistor with integrated tjbs diode - Google Patents

Field effect transistor with integrated tjbs diode Download PDF

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Publication number
TW201108394A
TW201108394A TW099125667A TW99125667A TW201108394A TW 201108394 A TW201108394 A TW 201108394A TW 099125667 A TW099125667 A TW 099125667A TW 99125667 A TW99125667 A TW 99125667A TW 201108394 A TW201108394 A TW 201108394A
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TW
Taiwan
Prior art keywords
semiconductor component
tjbs
trench
voltage
doped
Prior art date
Application number
TW099125667A
Other languages
English (en)
Inventor
Ning Qu
Alfred Goerlach
Original Assignee
Bosch Gmbh Robert
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Filing date
Publication date
Application filed by Bosch Gmbh Robert filed Critical Bosch Gmbh Robert
Publication of TW201108394A publication Critical patent/TW201108394A/zh

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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
    • H01L29/7806—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a Schottky barrier diode
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/872—Schottky diodes
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/861—Diodes
    • H01L29/872—Schottky diodes
    • H01L29/8725—Schottky diodes of the trench MOS barrier type [TMBS]
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/223—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a gaseous phase
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    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Description

201108394 六、發明說明： 【發明所屬之技術領域】 本發明關於一種半導體構件，特別是一種功率半導體 構件，尤其是一種具有整合之渠溝接合屏障肖特基（TJBS) 一極體的功率MOS場效電晶體。舉例而言，這種功率用導 體-構件可用於汽車發電機的同步整流器的場合。 【先前技術】 功率MOS場效電晶體在幾千年以來用於功率電子電路 中當作快速開關使用。除了平面式雙重擴散的構造（dm〇s ) 外’還使用具有渠溝（Grab’央.trench)構造的功率MOSFET (渠溝MOS )»然而在具很快切換過程的應用的場合〔其 中電流也很短時地流經MOSFET的「體二極體」 (Bodydiode )〕，例如在同步整流器DC-DC轉換器等的場 合’該pn體二極體的「通過損失」及「切換損失」有不利 的影響。故有人主張一種可能的輔助手段，將MOSFET並 聯，例如用其整合的pn體二極體與肖特基二極體並聯。 因此在美專利公報US-5 1 1 1253發表了一種DMOS與整 合之肖特基屏障二極體（SBD )的組合，雖然其優點為流通 電壓（Fluflspannung )較小及切換損失較小，然而在肖特基 二極體的缺點為阻斷電流（逆向電流）（Sperrstr〇m，英： reverse current)較大。除了主要由於金屬-半導體過渡區的 屏障（Barrier )引起的阻斷電流外，還會發生與阻斷電壓（反 向電壓）（Sperrspannimg ’ 英：reverse voltage)有關的成 201108394 分’它係由於所謂的「屏障降低作用」（Barrie卜Lowering W M US_2(K)5/()199918 中，主張將渠溝 MOS 與整合的渠溝聰屏障肖特基二極體（MBS)組合。如 此，該不利的BL效應可抑制。 ^顯示具有整合的刪屏障肖特基二極體（tmbs) =trs的裝置的簡化橫截面圖。在-高n+摻雜㈣ — η摻雜的石夕層（2)(蟲晶層），有多數渠溝 做到該碎層（2)中，在渠溝的側壁與底上有—薄介電層⑷， 一種導電材料(5)(例 有-。_(6) ( = =旁，在渠溝之間 圍⑺在广用:=“+摻雜的範圍（源極)與高。+摻雜的範 、連接Ρ電位肼）做到該ρ摻雜的 Π::;適當的導電層"Η例如用—= 層⑺與 _ 溝間的範圍〔它們不 '接點的作用。在渠 的作用係為「肖層(6)中〕該導電層(9) 觸。在該導電層(9)上二；了方的， 數個金導電金屬層或一個由 ，呈源極接點作用的金屬層⑽ =通::::;:切成分的銘合金(它係為”術中 ^ 弋）或其他金屬系統。在後側上施有一般01 軟録的金屬系統⑴)例如由以下層序構成:cr、二=了 此金屬系統(⑴為作排極接點，該多晶㈣(5)互相作電連： 4 201108394 以及與一閘極接點（圖未示）作電連接。 因此在電學上，該肖特基二極體〔亦即指某些範圍， 在這些範圍中金屬層⑼與n摻離的矽⑺接觸〕係與 MOSFET的體二極體〔亦即p推雜層（6)與n推雜層⑺〕並 聯。如果施加「阻斷電壓」，則在與肖特基接點相鄰的渠 溝構造之間形成空間電荷區域，且將電場從本來的肖特基 接點〔亦即過渡區（9_2)〕遮蔽。由於在肖特基上電場較小， 故BL效應減少’亦即阻斷電流隨阻斷電壓增加而上升的情 事可防止》由於肖特基二極體的流通電流較小，故ρη體二 極體不沿流通方向操作。因此該肖特基二極體(9·2)的作用 為 MOSFET 的反向二極體（Inversdi〇de)。 由於在肖特基二極體的場合，少數電荷載體 (Min〇ritatstrager)之儲存的電荷不必清除’因此在理想情 形，只要將空間電荷區域的電容部分充電。由於此排空所 發生的Pn二極體的高的逆電流尖峰不會出現。將一肖特基 二極體整合，可使M0SFET的切換性質改善，切換時間及 切換損失較少。 對於一些應用，宜使M0SFET也能在崩潰（Avalanche ) 貫穿時也能操作’電壓尖峰可利用體二極體限制，由於在 mosfet中經常有寄生性NPN電晶體存在，故會造成NpN 構造之不想要的破壞性的貫穿。因此，這種操作不被容許。 在整〇之TMBS —極體的情形，這種操作&原理上是可能 的，但由於如此會發生電荷載體注人TMBS的M0S構造中 的情事’基於品質理由’這種作法不宜採用。 201108394 在US 2006/0202204中主張另外將所謂的「接合屏障肖 特基二極體」整合到一渠溝M〇S中。接合屏障肖特基二極 體為扁平的肖特基二極體，其中將具有與基材的摻雜物相 反的導電類型的扁平範圍擴散進去，例如p摻雜範圍在η 摻雜的基材中，當施加阻斷電壓時，在ρ摻雜範圍之間的 空間電荷區域生長在一齊，且將電場大略和肖特基接點作 遮蔽隔開。因此BL效應略減少，然而此作用遠小於在TMBs 構造的場合《利用這種裝置，該M〇SFET在崩潰貫穿時可 操作，而不會有控制的危險以及寄生性npn電晶體破壞之 層0 【發明内容】 利用本發明的功率半導體構件可用有利的方式將在傳 統構造發生的「屏障降低效應」（BL效應）有效抑制，為 此，茲主張另外將TJBS二極體（渠溝M〇s屏障肖特基） 整合到一功率MOSFET中。在此，TJBS構造的貫穿電壓可 選設成比該另外存在的PN體二極體的貫穿電壓更大或更 小。當JTBS構造的崩潰貫穿電壓（z電壓）比該NpN電晶 體或pn體二極體的貫穿電壓更小的情形，該構件甚至可在 貫穿時在更高的電流操作。 本發明在圖式中作圖式並在以下說明敘述。 【實施方式】 圖2以不意方式顯示本發明一第一實施例的橫截面 6 201108394 U此匕係一種單晶積體電路構造，該構造含有-MOS =效=晶體及—TiBS二極體。在—高n+摻雜㈣基材上有 :雜碎層’例如—蟲晶層（2)，有多數渠溝⑺做入該為 :大多渠溝的側壁及底上設有一薄介電層，大多 由氧化石夕構層。這些渠溝内部再用-導電材料（例如摻 雜的多晶妙）+# 0¾ jf 3 -rH a 異滿’多明矽層（5)互相呈電連接，且與一閘 極接點（圖未示）作電連接。 圖3中顯示一本發明裝置的另一實施例，具有一單晶 積體電路構& ’它包含—M0S場效電晶體與-TJBS二極 體。其構造、功能及圖號與目2之本發明相似，只有在内 部範圍為例外。與圖2不同巾，該内部渠溝——TJBS的渠 溝並非用p摻雜的矽或多晶矽充填，而係完全或部分地用 金屬充填。有一平坦高p+摻雜的領域（13)接在這些渠溝的側 壁上與底上，其侵入深度小於丨〇〇奈米。這些領域與金屬 層（9)用電阻方式接觸。 該領域（13)可藉著施覆一種二硼烷氣相，接著作擴散或 加熱步驟（例如快速熱退火，RTp，Rapid Thermal Annealing) 而產生。其摻雜量及擴散或加熱速度選設成能達到相關的 貫穿電壓UZ_TiBS。本發明的裝置的所有其他的變更例可選 擇性地做成將渠溝用p摻雜的矽或多晶矽充填。 圖4中顯示一本發明裝置的另一變更例，在此該渠溝 與具閘構造的TJBS渠溝對立。如果此MOSFET要在貫穿時 操作，則貫穿電壓再調成使該TJBS具有所有構造的電壓之 甲的最小電壓值。 201108394 在圖2〜圖4的實施例中，TJBS的最外渠溝構造係與 體領域（Bodygebiet) (6)接觸（如圖2及圖3所示）或設成 和M0S渠溝構造對立（如圖4所示）。但TJBS的渠溝也 可位於P-摻雜的體領域之間相隔某種距離，如圖5所示。 在此，該TJBS構造可位在M〇SFET晶片内部或設在晶片邊 緣。 在本發明解決方法的說明中所選的半導體材料與摻雜 方式只是舉例，也可不用η·摻雜而用p_摻雜，以及不用ρ· 摻雜而用η-摻雜。 【圖式簡單說明】 圖1係依先前技術之具有整合的TMBS二極體的一功 率渠溝M0S場效電晶體的一示意橫截面圖； 圖2係第一種本發明裝置的示意橫載面圖； 圖3係第二種本發明裝置的示意橫截面圖； 圖4係另一種本發明裝置的示意橫截面圖； 圖5係具有整合的TJBS構造的另一本發明裝置的示意 橫截面圖。 【主要元件符號說明】 (1) $夕基材 (2) 石夕層（遙晶層） (3) 渠溝 (4) 介電層 201108394 (5) 導電材料 (6) P摻雜層（P電位肼） ⑺ p +摻雜的層 (8) n+摻雜的層 (9) 導電層 (9-2) 過渡區 (10) 金屬層 (Π) 金屬系統 9

Claims (1)

  1. 201108394 七、申請專利範圍： 1. 一種半導體元件，具有至少一 MOS場效電晶體及一 二極體’其特徵在：該二極體為一種渠溝接合屏障肖特基 二極體（TJBS)。 2 ·如申請專利範圍第1項之半導體構件，其中： 該MOS場效電晶體與該渠溝屏障肖特基二極體（TJBS) 計成單晶或積體電路構造。 3. 如申請專利範圍第1或第2項之半導體構件，其中： 該MOS場效電晶體與該渠溝接合屏障肖特基二極體 (TJBS )的貫穿電壓選設成使該M〇s場效電晶體可在貫穿 的情形中操作。 4. 如申請專利範圍第3項之半導體構件，其中： 該渠溝接合屏障肖特基二極體（TJBS )的貫穿電壓 (UZ.TjBS)選設成最小的貫穿電壓且因此小於該TJBs二極 體的貫穿電壓UZ-M基及小於一 pn體二極體的貫穿電壓 υζ·ρη以及小於該半導體構件的寄生性npn電晶體的貫穿電 壓。 5 ·如申請專利範圍第1或第2項之半導體構件，其中： 有一 η摻雜的矽〔例如一磊晶層（2)〕施到一高n+摻雜 的矽基材（1)上，有多數渠溝（3)做到該磊晶層中，且其中有 一些渠溝（3)的側壁及//或底上設以一薄介電層（4)，其中内 部用一由導電材料構旳層（5)充填，且這些層（5)互呈電相連 接及與一閘接點呈電連接。 6.如申請專利範圍第5項之半導體構件，其中： 201108394 該介電層（4)由二氧化矽構成。 7.如申請專利範圍第5項之半導體構件，其中： 該導電材料為摻的多晶矽。 8_如申請專利範圍第5項之半導體構件，其中： 在渠溝之間有一 p摻雜層（6) ( p電位肼），高n +摻雜 的範圍（8)在表面上設到該p摻雜層（6)中當作源極，且高p+ 摻雜的範圍（7)在表面設到該p摻雜層（6)中用於連接該口電 位肼。 9. 如申請專利範圍第8項之半導體構件，其中： 在渠溝之間有一些區域沒有p摻雜層（6) ( p電位肼）， 只有η摻雜的磊晶層（2)，其中在這些渠溝中，二氧化石夕層 (4)被ρ摻雜的矽或多晶矽（12)取代，該矽或多晶矽填滿該渠 溝。 10. 如申請專利範圍第1或第2項之半導體構件，其中： 在用Ρ-摻雜的矽充填的渠溝的位置，該磊晶層（2)與一 種肖特基金屬（9)(特別是與矽化鈦）接觸構成肖特基接點， 其中該過渡區（9-2)形成一肖特基二極體，如此，當施加阻 斷電壓時，該與肖特基接點相鄰之用ρ摻雜石夕充填的渠溝 構造之間形成空間電荷區域，該空間電荷區域將電場與過 渡區（9-2)上原來的肖特基接點遮蔽隔離，因此由於在肖特 基接點處的電場較小使BL效應減少，且防止阻斷電流隨阻 斷電壓增加而上升。 11. 如申請專利範圍第1或第2項之半導體構件，其中： 該範圍（1)造成一種渠溝接合屏障肖特基二極體（Tjbs 201108394
    體 極 ο 該p-層（12)的滲雜量選設成使p-層（12)與η-摻雜的遙晶 層（TJBS) (2)之間的貫穿電壓（UZ.TjBS)小於該肖特基二 極體（9-2)的貫穿電壓UZ_SBD。 13. 如申請專利範圍第1或第2項之半導體構件，其中： 該貫穿電壓也小於該pn-反向二極體（6-2)的貫穿電壓 及該由範圍（8)(7)(6)及（2)組合成的寄生性電晶體的貫穿電 壓。 14. 如申請專利範圍第1或第2項之半導體構件其中： 在該導電層（9)上方有一較厚的導電金屬層或一個由數 個金屬層構成的層系統且它形成源極接點，且在後側有一 金屬系統，該金屬系統當作排極’其中該多晶矽層⑺互相 成電連接以及與—閘極接點成電連接以將電壓作可靠的限 制。 15卞申請專利範圍第！或第2項之半導體構件，其中： 側壁構造㈣溝用金屬充填，且渠溝的 與底包含平坦的P-摻雜領域。 當二V’專利範圍第15項之半導體構件，其中： 上側用P+石夕ΓΓ上的去渠溝|完全用卜領域充滿時，將p-領域的 17·如申請專利二溝壁的摻雜作業可， 該内部渠濟一 或第2項之半導體構件，其中： 石夕充填，而；入—即TJBS渠溝——不用P-摻的矽或多晶 /几丹而係全部八 一刀也用金屬充填，且在這此渠溝的 12 201108394 側壁與底上接一個平坦的高p+摻雜的領域（13)，其侵入深 度小於100奈米，該領域（13)與金屬層（9)呈電阻方式接觸。 1 8.如申請專利範圍第！ 7項之半導體構件，其中： 該領域（13)係藉著施覆一種二硼烷氣相，然後作擴散或 加熱步驟（例如快速熱退火rTP )產生，其中的摻雜量及 擴散或加熱步驟選設成可達到相關的貫穿電壓（uZ TjBs)。 19. 如申請專利範圍第1或第2項之半導體構件，其中： 該渠溝（12)選擇性地用p摻雜的矽或多晶矽充填。 20. 如申請專利範圍第1或第2項之半導體構件，其中： 具有閘構造的渠溝與TJBS的渠溝對立，其中，當該 MOSFET要在貫穿情形中操作時，則將貫穿電壓再調整成 使該TJBS具有所有構造的電壓的最低電壓。 21. 如申請專利範圍第1或第2項之半導體構件，其中： 該TJBS的渠溝以某種間隔位在那些p_摻雜的體領域（6) 中，其中該TJBS構造位在MOSFET晶片内部或設在晶片邊 緣。 22. 如申請專利範圍第1或第2項之半導體構件，其中： 所有摻雜都做成相反的導通類型，且n_摻雜者利用p- 摻雜者取代。 八、圖式： (如次頁） 13
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