TW201001623A - Wafer level integration module with interconnects - Google Patents

Wafer level integration module with interconnects Download PDF

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Publication number
TW201001623A
TW201001623A TW098114948A TW98114948A TW201001623A TW 201001623 A TW201001623 A TW 201001623A TW 098114948 A TW098114948 A TW 098114948A TW 98114948 A TW98114948 A TW 98114948A TW 201001623 A TW201001623 A TW 201001623A
Authority
TW
Taiwan
Prior art keywords
wafer
component
layer
conductive layer
conductive
Prior art date
Application number
TW098114948A
Other languages
English (en)
Chinese (zh)
Inventor
Gautham Viswanadam
Original Assignee
Gautham Viswanadam
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Gautham Viswanadam filed Critical Gautham Viswanadam
Publication of TW201001623A publication Critical patent/TW201001623A/zh

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D10/00—Bipolar junction transistors [BJT]
    • H10D10/60—Lateral BJTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/23—Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by multiple measurements, corrections, marking or sorting processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/27—Structural arrangements therefor
    • H10P74/273—Interconnections for measuring or testing, e.g. probe pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/019—Manufacture or treatment of bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/20—Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by the properties tested or measured, e.g. structural or electrical properties
    • H10P74/207—Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H10W72/252—Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/29—Bond pads specially adapted therefor

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
TW098114948A 2008-05-06 2009-05-06 Wafer level integration module with interconnects TW201001623A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
SG200803479-5A SG156550A1 (en) 2008-05-06 2008-05-06 Wafer level integration module with interconnects

Publications (1)

Publication Number Publication Date
TW201001623A true TW201001623A (en) 2010-01-01

Family

ID=41265195

Family Applications (1)

Application Number Title Priority Date Filing Date
TW098114948A TW201001623A (en) 2008-05-06 2009-05-06 Wafer level integration module with interconnects

Country Status (6)

Country Link
US (2) US7998854B2 (https=)
JP (1) JP2011523203A (https=)
CN (1) CN102084479A (https=)
SG (1) SG156550A1 (https=)
TW (1) TW201001623A (https=)
WO (1) WO2009136873A2 (https=)

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CN102339816A (zh) * 2011-09-30 2012-02-01 上海宏力半导体制造有限公司 晶圆测试键结构及晶圆测试方法
US20140209926A1 (en) * 2013-01-28 2014-07-31 Win Semiconductors Corp. Semiconductor integrated circuit
US10163773B1 (en) 2017-08-11 2018-12-25 General Electric Company Electronics package having a self-aligning interconnect assembly and method of making same
US10811390B2 (en) * 2019-01-21 2020-10-20 Taiwan Semiconductor Manufacturing Company, Ltd. Die stack structure and method of fabricating the same and package
CN113767716B (zh) 2019-05-06 2024-07-30 3M创新有限公司 图案化导电制品
US12573766B2 (en) 2020-06-16 2026-03-10 3M Innovative Properties Company Patterned article including metallic bodies
CN112800715B (zh) * 2021-01-14 2021-09-24 国家数字交换系统工程技术研究中心 软件定义晶上系统及数据交互方法和系统体系架构
CN114975333A (zh) * 2022-07-29 2022-08-30 广东大普通信技术股份有限公司 芯片结构

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JPS62219954A (ja) * 1986-03-20 1987-09-28 Fujitsu Ltd 三次元ｉｃの製造方法
KR900008647B1 (ko) * 1986-03-20 1990-11-26 후지쓰 가부시끼가이샤 3차원 집적회로와 그의 제조방법
JPS62272556A (ja) * 1986-05-20 1987-11-26 Fujitsu Ltd 三次元半導体集積回路装置及びその製造方法
JPH01189141A (ja) * 1988-01-25 1989-07-28 Nec Corp 半導体装置
US6882030B2 (en) * 1996-10-29 2005-04-19 Tru-Si Technologies, Inc. Integrated circuit structures with a conductor formed in a through hole in a semiconductor substrate and protruding from a surface of the substrate
JP4234244B2 (ja) * 1998-12-28 2009-03-04 富士通マイクロエレクトロニクス株式会社 ウエハーレベルパッケージ及びウエハーレベルパッケージを用いた半導体装置の製造方法
US6693358B2 (en) * 2000-10-23 2004-02-17 Matsushita Electric Industrial Co., Ltd. Semiconductor chip, wiring board and manufacturing process thereof as well as semiconductor device
JP3967108B2 (ja) * 2001-10-26 2007-08-29 富士通株式会社 半導体装置およびその製造方法
US6706629B1 (en) * 2003-01-07 2004-03-16 Taiwan Semiconductor Manufacturing Company Barrier-free copper interconnect
TWI242274B (en) * 2003-02-27 2005-10-21 Siliconware Precision Industries Co Ltd Ball grid array semiconductor package and method for fabricating the same
TWI228295B (en) * 2003-11-10 2005-02-21 Shih-Hsien Tseng IC structure and a manufacturing method
JPWO2005086216A1 (ja) * 2004-03-09 2008-01-24 独立行政法人科学技術振興機構 半導体素子及び半導体素子の製造方法
JP5354765B2 (ja) * 2004-08-20 2013-11-27 カミヤチョウ アイピー ホールディングス 三次元積層構造を持つ半導体装置の製造方法
KR100688857B1 (ko) * 2004-12-17 2007-03-02 삼성전기주식회사 윈도우를 구비한 볼 그리드 어레이 기판 및 그 제조방법
US7629225B2 (en) * 2005-06-13 2009-12-08 Infineon Technologies Ag Methods of manufacturing semiconductor devices and structures thereof
US20090081862A1 (en) * 2007-09-24 2009-03-26 Taiwan Semiconductor Manufacturing Co., Ltd. Air gap structure design for advanced integrated circuit technology
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JP2010287831A (ja) * 2009-06-15 2010-12-24 Renesas Electronics Corp 半導体装置およびその製造方法

Also Published As

Publication number Publication date
WO2009136873A2 (en) 2009-11-12
SG156550A1 (en) 2009-11-26
CN102084479A (zh) 2011-06-01
US20110278569A1 (en) 2011-11-17
US20110065215A1 (en) 2011-03-17
WO2009136873A3 (en) 2010-08-12
US7998854B2 (en) 2011-08-16
JP2011523203A (ja) 2011-08-04

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