TW200942117A - Production method of multilayer printed wiring board and multilayer printed wiring board - Google Patents

Production method of multilayer printed wiring board and multilayer printed wiring board Download PDF

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Publication number
TW200942117A
TW200942117A TW097145199A TW97145199A TW200942117A TW 200942117 A TW200942117 A TW 200942117A TW 097145199 A TW097145199 A TW 097145199A TW 97145199 A TW97145199 A TW 97145199A TW 200942117 A TW200942117 A TW 200942117A
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TW
Taiwan
Prior art keywords
insulating layer
hole
glass cloth
printed wiring
wiring board
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Application number
TW097145199A
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Chinese (zh)
Other versions
TWI450666B (en
Inventor
Seiichiro Ohashi
Eiichi Hayashi
Shigeo Nakamura
Takaaki Yazawa
Junichi Nakamura
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Ajinomoto Kk
Shinko Electric Ind Co
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Publication of TW200942117A publication Critical patent/TW200942117A/en
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Publication of TWI450666B publication Critical patent/TWI450666B/en

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    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/02Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038Through-connections; Vertical interconnect access [VIA] connections
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0296Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
    • H05K1/0298Multilayer circuits
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/0011Working of insulating substrates or insulating layers
    • H05K3/0017Etching of the substrate by chemical or physical means
    • H05K3/0026Etching of the substrate by chemical or physical means by laser ablation
    • H05K3/0032Etching of the substrate by chemical or physical means by laser ablation of organic insulating material
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/0011Working of insulating substrates or insulating layers
    • H05K3/0055After-treatment, e.g. cleaning or desmearing of holes
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42Plated through-holes or plated via connections
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4611Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4626Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/03Use of materials for the substrate
    • H05K1/0313Organic insulating material
    • H05K1/0353Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement
    • H05K1/0366Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement reinforced, e.g. by fibres, fabrics
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/07Treatments involving liquids, e.g. plating, rinsing
    • H05K2203/0779Treatments involving liquids, e.g. plating, rinsing characterised by the specific liquids involved
    • H05K2203/0786Using an aqueous solution, e.g. for cleaning or during drilling of holes
    • H05K2203/0796Oxidant in aqueous solution, e.g. permanganate
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/0011Working of insulating substrates or insulating layers
    • H05K3/0017Etching of the substrate by chemical or physical means
    • H05K3/0026Etching of the substrate by chemical or physical means by laser ablation
    • H05K3/0032Etching of the substrate by chemical or physical means by laser ablation of organic insulating material
    • H05K3/0035Etching of the substrate by chemical or physical means by laser ablation of organic insulating material of blind holes, i.e. having a metal layer at the bottom
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155Manufacturing circuit on or in base
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155Manufacturing circuit on or in base
    • Y10T29/49165Manufacturing circuit on or in base by forming conductive walled aperture in base

Abstract

The production method of the multilayer printed wiring board of the present invention includes forming a via hole by laser irradiation in insulating layer formed by a prepreg comprised of a glass cloth impregnated with a thermosetting resin composition, and subjecting the via hole to a glass etching treatment with a glass etching solution and then to a desmear treatment with an oxidizing agent solution. Due to such constitution, etch back phenomenon and excessive protrusion of glass cloth from the wall surface of a via hole can be sufficiently suppressed, and a highly reliable via can be formed. Particularly, a highly reliable via can be formed in a small via hole having a top diameter of 75 μ m or below.

Description

,200942117 九、發明說明 【發明所屬之技術領域】 本發明係關於多層印刷配線板的製造方法、及藉由該 方法所製造的多層印刷配線板。 【先前技術】 關於製造多層印刷配線板的技術,習知上已知使用在 核心基板上將絕緣層及導電層交錯地疊層之堆疊製程。爲 了形成絕緣層,獨特地使用藉由在塑膠膜上形成熱固性樹 脂層而形成的黏著膜,其中,藉由將黏著膜疊層於內層電 路基板上、將塑膠膜分離、及將熱固性樹脂熱固化,以形 成絕緣層。另一方面,慮及近來電子裝置及電子構件尺寸 縮小的需求,舉例而言,由於需要更薄的核心基板及省略 基板等等,所以,多層印刷配線板趨向於製成更薄。在嘗 試藉由製造更薄的核心基板以提供更薄的多層印刷配線板 時,使用預浸體(prepreg)作爲形成層間絕緣膜的材料,可 以有效維持多層印刷配線板的機械強度。 圖4 ( a) -(e)及圖5 ( a)和(b)是顯示多層印刷配線 板的製造步驟之剖面視圖,多層印刷配線板包含使用預浸 體所形成的層間絕緣層’預浸體包括浸漬有熱固性樹脂的 片狀玻璃布纖維基板。 首先,製備電路基板10及包含浸漬有熱固性樹脂成 分2的玻璃布1之預浸體3(圖4(a)及4(b)),預浸體3係 疊層於電路基板1〇上以遮蓋電路基板1〇的表面上的導電 -5- 200942117 體圖案(墊)11,以及,使熱固性樹脂成分2固化以形成絕 緣層4(圖4(c))。然後,如圖4(d)所示,在絕緣層4上藉 由雷射照射而形成通孔(盲孔)5。由於玻璃布1與絕緣 層4 (熱固性樹脂成分2的固化產品)間之加工性的差 異,玻璃布1會從通孔5的壁面凸出(圖4(d))。在雷射 處理之後,當施加去塗抹處理以去除因雷射處理所產生的 殘留物時,玻璃布1又從通孔5的壁面凸出(圖4(e))。 但是,當從通孔的壁面凸出的玻璃布1原狀地保留時,玻 璃布會使下一個電鍍處理中電鍍溶液的流動(流動性)變 差,因而在通孔中產生不均勻的電鍍。結果,變得難以形 成具有高導通可靠度的通孔。爲了防止此情形,從通孔的 側壁表面凸出的玻璃布需要被處理,舉例而言,JP-A-2002- 1 00866(此後稱爲「先前技術文獻1」)建議使用氟化 物等的蝕刻處理。此外,JP-A-2005-86 1 64(此後稱爲「先 前技術文獻2」)指出當上述先前技術文獻1中述的方法 應用至真實的多層電路基板時,會有雷射照射所熔化的基 質樹脂附著至玻璃布及阻止氟化物與玻璃布相接觸等問 題,因而無法有效地藉由蝕刻來去除玻璃布。爲了解決此 問題,使用過锰酸鹼金屬鉀鹽溶液以去除樹脂殘留物,以 及,接著使玻璃布受到鈾刻處理。在玻璃布的蝕刻處理之 後,玻璃布1並未從通孔5的壁面凸出(圖5(a))。在此 狀態中,一般而言,藉由電鍍等,以使塞孔20形成於通 孔5中(圖5b),藉以取得層間導通。 200942117 【發明內容】 近年來,通孔直徑也趨向於尺寸縮小以用於多層印刷 配線板的超細微配線。當從具有小直徑的通孔的側壁表面 凸出的玻璃布被充分地蝕刻時,如圖5(a)所示’因爲玻璃 布1的進一步表面溶解,所以在絕緣層4中形成在通孔5 的壁面上具有開口的空隙S。結果’在用以形成塞孔的電 鍍處理期間,電鍍溶液滲透入空隙S中,因而在空隙S中 形成導電膜(電鍍膜)21 (請參見圖5(b)),此稱爲玻璃 布的回蝕現象。此爲形成於絕緣層上的塞孔所共有的現 象,這會造成例如降低塞孔20與相鄰塞孔之間的絕緣可 靠度等等缺點。 先前技術文獻2指出穿孔中的毛細現象(回蝕現象) 問題。但是,其完全未提及塞孔的回蝕現象。這是因爲, 假定先前技術文獻 2係有關於將具有相當大的直徑 1 00 μπι(頂部直徑)的通孔做爲目標,其中,電鍍溶液之 劣化的流動之問題(電鍍溶液難以流動的問題)本身並未 顯露,以及將玻璃布的蝕刻至造成回蝕現象的程度是不需 要的。但是,根據本發明人的硏究,發現電鍍溶液劣化的 流動問題對於例如具有未大於7 5 μπι之小的頂部直徑的通 孔等具有較小直徑的通孔會成爲嚴重問題,以及,從通孔 壁面凸出的玻璃布需要被充分地蝕刻,因而在這些通孔中 造成回蝕現象。換言之,他們發現玻璃布的充分蝕刻會造 成通孔壁內之玻璃布充分蝕刻,以及,在通孔的壁內留下 未受損傷的玻璃布之這些條件下的蝕刻並無法充分地蝕刻 200942117 從壁面凸出的玻璃布,因而,造成電鍍溶液之劣化的流動 (低流動性)。 有鑑於此情形而做成本發明,本發明之目的在於提供 多層印刷配線板之製造方法,其能夠充分地抑制回鈾現象 及玻璃布從導通孔的壁面凸出,以及,能夠形成高度可靠 的塞孔。此外,本發明提供具有高度可靠的塞孔之多層印 刷配線板。 本發明人經過深入的硏究以解決上述問題,並且發現 藉由雷射照射以在藉由熱固化浸漬體所形成的絕緣層中形 成通孔、蝕刻從通孔的側壁表面凸出的玻璃布、及以氧化 劑溶液對通孔施加去塗抹處理,可以消除因爲蝕刻期間玻 璃布的進一步表面溶解而形成之通孔的側壁表面上具有開 口的空隙,而完成本發明,浸漬體包括以熱固性樹脂成分 浸漬的玻璃布。因此本發明涵蓋下述。 [1] 多層印刷配線板之製造方法,包括:藉由雷射照射 以在由預浸體所形成的絕緣層中形成通孔,以及,使通孔 受到以玻璃蝕刻溶液之玻璃蝕刻處理,而後受到以去氧化 劑溶液的去塗抹處理,該預浸體包括以熱固性樹脂成分所 浸漬的玻璃布。 [2] 根據上述[1]的方法,其中,通孔具有不大於 7 5 μιη 的頂部直徑。 [3] 根據上述[1]或[2]的方法,其中,將預浸體疊層於 電路基板的至少一表面上、在降壓下加熱及壓製該疊層、 以及熱固化該預浸體’以形成絕緣層。 -8 - 200942117 [4] 根據上述[1]-[3]中任一方法,其中,氧化劑溶液 是過鍤酸驗金屬鹽溶液。 [5] 根據上述[1]-[4]中任一方法,其中,使用氧化劑 溶液的通孔去塗抹處理與使用氧化劑溶液的絕緣層表面粗 糙化處理被同時實施。 [6] 根據上述[5]的方法,又包括電鏟程序,藉由電鍍 以在絕緣層的粗糙化表面上形成導電層。 [7] 根據上述[6]的方法,又包括退火處理步驟,用以 在形成導電層之後,將絕緣層及導電層退火。 [8] 根據上述[7]的方法,又包括電路形成步驟,用以 在導電層上形成電路。 [9 ] 一種多層印刷配線板,包括: 絕緣層’係由包括以熱固性樹脂成分浸漬的玻璃布之 預浸體所形成, 通孔,係形成於絕緣層上, 電路,含有在導通孔中由導電層所形成的塞孔,及 玻璃布,從上述通孔的側壁突出不大於6μιη的長 度, 其中,玻璃布的凸出部份係嵌入於形成塞孔的導電層 中。 [10]根據上述[9]之多層印刷配線板,其中,絕緣層係 由積層法所形成。 [1 1]上述[9]或[10]之多層印刷配線板,其中,使絕緣 層的表面粗糙化至具有〇.1-1·5μηι範圍內的算術平均粗糙 200942117 度(Ra)。 根據本發明的多層印刷配線板之製造方法,由於使用 氧化劑溶液的去塗抹處理係施加至形成於絕緣層上的通 孔,所以,在從通孔的側壁表面凸出的玻璃布的蝕刻處理 之後,由於在去塗抹處理期間氧化劑溶液蝕刻構成絕緣層 的樹脂固化產物,所以,可以消除在玻璃布蝕刻處理期間 可能形成在導通孔側表面上具有開口的空隙。因此,可以 同時地達成充分地降低從通孔的側壁表面凸出的玻璃布之 長度以及抑制回蝕現象之蝕刻,以及,可以形成高度可靠 的塞孔,而不會有導因於電鍍液的劣化流動(降低的流動 性)或回蝕現象之缺點。因此,舉例而言,本發明可以提 供高度可靠的具有小直徑塞孔之多層印刷配線板,小直徑 塞孔的頂部直徑不大於7 5 μηι。 【實施方式】 在圖中,1代表玻璃布,2表示熱固性樹脂成分,3 表示預浸體,4代表絕緣層,5代表通孔,9代表塞孔 (經塡充之孔),10代表電路基板。 在下述說明中,將舉例說明較佳實施例以解說本發 明。 在本發明中的預浸體包括例如片狀纖維基板之玻璃 布’其以熱固性樹脂成分來予以浸漬。做爲玻璃布,可以 使用用於預浸體的已知玻璃布而沒有限定,其可爲織布或 不織布。由於具有高強度的織布在商業上可以取得且很容 -10- 200942117 易取得,所以,較佳的是織布。此外,雖然玻璃布的厚度 並未特別限定,但是,較佳的是不大於5〇μηι,特別較佳 地爲10-3 0 μπι。織布形式的玻璃布之具體實例包含由 Asahi-Schwebel公司所製造的「STYLE 1027MS」(經紗密 度75絲/25mm,緯紗密度75絲/25mm ’布重20g/m2,厚 度 19μιη),由 Asahi-Schwebel 公司所製造的「STYLE 1 03 7MS」(經紗密度 70絲/25mm,緯紗密度 73 絲 /25mm,布重 24g/m2,厚度 28μιη),由 Arisawa Mfg·公司 所製造的「1 03 7NS」(經紗密度72絲/25mm ’緯紗密度 69 絲/25mm,布重 23 g/m2,厚度 21μιη),由 Arisawa Mfg 公司所製造的「1 027NS」(經紗密度75絲/25mm,緯紗密 度 75 絲/25mm,布重 19.5g/m2,厚度 16μιη),由 Arisawa Mfg.公司所製造的「1 01 5NS」(經紗密度95絲/25 mm,緯 紗密度95絲/25 mm,布重1 7.5 g/m2,厚度1 5μιη) '等 等。此外,不織布形式的玻璃布的具體實例包含由Japan Vilene 公司所製造的 「Cumulass EPM4025」(直徑約 13μιη,纖維長度約 ΙΟμιη)、「Cumulass EPM4100B」(直 徑約13μιη,纖維長度約ΙΟμιη)、等等。 做爲熱固性樹脂成分,只要適用於多層印刷配線板的 絕緣層即可,並無特別限制。舉例而言,可以使用至少含 有熱固性樹脂及其固化劑之成分,舉例而言,熱固性樹脂 可爲環氧樹脂、氰酸酯樹脂、酚樹脂、二順丁烯二醯亞胺 一三嗪樹脂、聚醯亞胺樹脂、丙烯酸樹脂、乙烯苯甲基樹 脂、等等。在這些之中,較佳的是含有環氧樹脂作爲熱固 -11 - 200942117 性樹脂的成分,舉例而言,含有環氧樹脂、熱塑樹脂及固 化劑的成分。 環氧樹脂的例子包含雙酚A型環氧樹脂、聯苯型環 氧樹脂、萘酚型環氧樹脂、萘型環氧樹脂、雙酚F型環氧 樹脂、含磷環氧樹脂、雙酚S型環氧樹脂、脂環環氧樹 脂、脂肪鏈環氧樹脂、酚醛清漆型環氧樹脂、甲酚醛清漆 型環氧樹脂、雙酚A醛清漆型環氧樹脂、具有丁二烯結 構的環氧樹脂、雙酚的二氧化丙烯醚產物、萘二酚的二氧 化丙烯醚產物、酚的二氧化丙烯醚產物、及醇的二氧化丙 烯醚產物以及這些環氧樹脂的的烷替代產物、鹵化物及氫 化產物等等。可以單獨使用這些環氧樹脂中的任一種或二 或更多種可以相混合。 做爲環氧樹脂,從抗熱性、絕緣可靠度、及與金屬膜 的緊密黏合的觀點而言,雙酚A型環氧樹脂、萘酚型環 氧樹脂、萘型環氧樹脂、聯苯型環氧樹脂及具有丁二烯結 構的環氧樹脂是較佳的。明確地說,舉例而言,可爲液態 雙酣A型環氧樹脂(由Japan Epoxy Resins公司所製造的 「Epikote 828EL」)、萘型二官能環氧樹脂(由 Dainippon Ink and Chemicals 公司所製造的「HP4032」、 「HP403 2D」)、萘型四官能環氧樹脂(由Dainippon Ink and Chemicals公司所製造的「HP4700」)、萘酚型環氧樹 脂(由Tohto Kasei公司所製造的「ESN-475V」)' 具有丁 二烯結構的環氧樹脂(由 DAICEL CHEMICAL INDUSTRIES公司所製造的「PB-3 600」)、具有聯苯結構 200942117 的環氧樹脂(由 Nippon Kayaku 公司所製造的 「NC3000H」、「NC3000L」,由 Japan Epoxy Resins 公 司所製造的「YX4000」)、等等。 舉例而言,爲了在固化之後等等,賦予成分適當的可 撓性,預浸體可以含有熱塑性樹脂。此種熱塑性樹脂的實 例包含苯氧樹脂、聚乙烯縮醛樹脂、聚醯亞胺、聚醯胺醯 亞胺、聚醚楓、聚碾、等等。可以單獨地使用這些環氧樹 II 脂中的任一種或是其二或更多種可以混合。相對於100質 量%之熱固性樹脂成分中的非揮發性成分,較佳地以0.5-. 60質量%的比例,更佳地以3-50質量%的比例,添加熱塑 . 性樹脂。 苯氧樹脂的具體實例包含由Tohto Kasei公司所製造 的 FX280、FX293,由 Japan Epoxy Resin 公司所製造的 YX8100、YL6954、YL6974、等等。[Technical Field] The present invention relates to a method of manufacturing a multilayer printed wiring board and a multilayer printed wiring board manufactured by the method. [Prior Art] Regarding a technique for manufacturing a multilayer printed wiring board, a stacking process in which an insulating layer and a conductive layer are alternately laminated on a core substrate is known. In order to form an insulating layer, an adhesive film formed by forming a thermosetting resin layer on a plastic film by laminating an adhesive film on an inner layer circuit substrate, separating the plastic film, and heating the thermosetting resin is uniquely used. Curing to form an insulating layer. On the other hand, in consideration of the recent demand for downsizing of electronic devices and electronic components, for example, since a thinner core substrate and a substrate are omitted, the multilayer printed wiring board tends to be made thinner. When attempting to manufacture a thinner core substrate to provide a thinner multilayer printed wiring board, a prepreg is used as a material for forming an interlayer insulating film, and the mechanical strength of the multilayer printed wiring board can be effectively maintained. 4(a)-(e) and Figs. 5(a) and (b) are cross-sectional views showing a manufacturing step of a multilayer printed wiring board including an interlayer insulating layer formed by using a prepreg The body includes a sheet-like glass cloth fiber substrate impregnated with a thermosetting resin. First, a circuit board 10 and a prepreg 3 (Figs. 4(a) and 4(b)) including the glass cloth 1 impregnated with the thermosetting resin component 2 are prepared, and the prepreg 3 is laminated on the circuit board 1 The conductive-5-200942117 body pattern (pad) 11 on the surface of the circuit substrate 1 is covered, and the thermosetting resin component 2 is cured to form the insulating layer 4 (Fig. 4(c)). Then, as shown in Fig. 4 (d), a via hole (blind hole) 5 is formed on the insulating layer 4 by laser irradiation. The glass cloth 1 protrudes from the wall surface of the through hole 5 due to the difference in workability between the glass cloth 1 and the insulating layer 4 (cured product of the thermosetting resin component 2) (Fig. 4(d)). After the laser treatment, when the smear treatment is applied to remove the residue due to the laser treatment, the glass cloth 1 is again protruded from the wall surface of the through hole 5 (Fig. 4(e)). However, when the glass cloth 1 protruding from the wall surface of the through hole is left as it is, the glass cloth deteriorates the flow (fluidity) of the plating solution in the next plating process, thereby causing uneven plating in the through holes. As a result, it becomes difficult to form a through hole having high conduction reliability. In order to prevent this, the glass cloth protruding from the side wall surface of the through hole needs to be treated. For example, JP-A-2002-100866 (hereinafter referred to as "Prior Art Document 1") suggests etching using fluoride or the like. deal with. Further, JP-A-2005-86 1 64 (hereinafter referred to as "Prior Art Document 2") indicates that when the method described in the above-mentioned prior art document 1 is applied to a real multilayer circuit substrate, there is laser irradiation to be melted. The matrix resin adheres to the glass cloth and prevents the fluoride from coming into contact with the glass cloth, and thus the glass cloth cannot be effectively removed by etching. In order to solve this problem, an alkali metal permanganate solution was used to remove the resin residue, and then the glass cloth was subjected to uranium engraving. After the etching treatment of the glass cloth, the glass cloth 1 does not protrude from the wall surface of the through hole 5 (Fig. 5 (a)). In this state, in general, the plug holes 20 are formed in the through holes 5 by plating or the like (Fig. 5b), thereby achieving interlayer conduction. 200942117 SUMMARY OF THE INVENTION In recent years, the via diameter has also tended to be downsized for use in ultrafine wiring of multilayer printed wiring boards. When the glass cloth protruding from the side wall surface of the through hole having the small diameter is sufficiently etched, as shown in FIG. 5(a), 'because the further surface of the glass cloth 1 is dissolved, the through hole is formed in the insulating layer 4. The wall of 5 has an open space S. As a result, during the plating process for forming the plug holes, the plating solution penetrates into the voids S, thereby forming a conductive film (plating film) 21 in the gap S (see FIG. 5(b)), which is called glass cloth. Eclipse phenomenon. This is a phenomenon common to the plug holes formed on the insulating layer, which causes disadvantages such as lowering the insulation reliability between the plug holes 20 and the adjacent plug holes. The prior art document 2 points out the problem of capillary phenomenon (etchback phenomenon) in perforation. However, it does not mention the etchback phenomenon of the plug hole at all. This is because it is assumed that the prior art document 2 is directed to a through hole having a relatively large diameter of 100 μm (top diameter) in which the problem of the flow of deterioration of the plating solution (the problem that the plating solution is difficult to flow) It is not revealed by itself, and the extent to which the glass cloth is etched to cause etchback is not required. However, according to the study of the present inventors, it has been found that the flow problem of deterioration of the plating solution becomes a serious problem for a through hole having a smaller diameter such as a through hole having a top diameter of not more than 75 μm, and The glass cloth protruding from the wall surface of the hole needs to be sufficiently etched, thereby causing etch back in these through holes. In other words, they found that sufficient etching of the glass cloth caused the glass cloth in the wall of the through hole to be sufficiently etched, and etching under these conditions that left the undamaged glass cloth in the wall of the through hole was not sufficiently etched. The glass cloth protruding from the wall surface thus causes a degraded flow of the plating solution (low fluidity). In view of the circumstances, it is an object of the present invention to provide a method of manufacturing a multilayer printed wiring board capable of sufficiently suppressing the phenomenon of uranium retreat and the glass cloth protruding from the wall surface of the via hole, and capable of forming a highly reliable plug. hole. Further, the present invention provides a multilayer printed wiring board having a highly reliable plug hole. The present inventors have intensively studied to solve the above problems, and have found that a glass cloth protruding from the side wall surface of the through hole is formed by forming a through hole in the insulating layer formed by thermally curing the impregnated body by laser irradiation. And applying a de-smearing treatment to the via hole with the oxidizing agent solution, the void having an opening on the side wall surface of the through hole formed by further surface dissolution of the glass cloth during etching can be eliminated, and the present invention is completed, and the impregnated body includes a thermosetting resin component. Impregnated glass cloth. The invention therefore covers the following. [1] A method of manufacturing a multilayer printed wiring board comprising: forming a through hole in an insulating layer formed of a prepreg by laser irradiation, and subjecting the through hole to a glass etching treatment using a glass etching solution, and then It is subjected to a desmearing treatment with a deoxidizing solution comprising a glass cloth impregnated with a thermosetting resin component. [2] The method according to the above [1], wherein the through hole has a top diameter of not more than 75 μm. [3] The method according to the above [1] or [2] wherein the prepreg is laminated on at least one surface of the circuit substrate, the laminate is heated and pressed under reduced pressure, and the prepreg is thermally cured. 'To form an insulating layer. -8 - 200942117 [4] The method according to any one of the above [1] to [3] wherein the oxidizing agent solution is a peroxyic acid metal salt solution. [5] The method according to any one of the above [1] to [4] wherein the through-hole smear treatment using the oxidizing agent solution and the surface roughening treatment using the oxidizing agent solution are simultaneously performed. [6] The method according to the above [5], further comprising a shovel program for forming a conductive layer on the roughened surface of the insulating layer by electroplating. [7] The method according to [6] above, which further includes an annealing treatment step of annealing the insulating layer and the conductive layer after forming the conductive layer. [8] The method according to [7] above, further comprising a circuit forming step of forming a circuit on the conductive layer. [9] A multilayer printed wiring board comprising: an insulating layer formed of a prepreg comprising a glass cloth impregnated with a thermosetting resin component, a through hole formed on the insulating layer, and an electric circuit included in the via hole The plug hole formed by the conductive layer and the glass cloth protrude from the side wall of the through hole by a length of not more than 6 μm, wherein the convex portion of the glass cloth is embedded in the conductive layer forming the plug hole. [10] The multilayer printed wiring board according to the above [9], wherein the insulating layer is formed by a lamination method. [1] The multilayer printed wiring board according to the above [9] or [10] wherein the surface of the insulating layer is roughened to have an arithmetic mean roughness of 200942117 degrees (Ra) in the range of 1-1.1-1·5μη. According to the method of manufacturing a multilayer printed wiring board of the present invention, since the de-coating treatment using the oxidizing agent solution is applied to the through holes formed on the insulating layer, after the etching treatment of the glass cloth protruding from the side wall surface of the through hole Since the oxidizing agent solution etches the resin cured product constituting the insulating layer during the smear process, it is possible to eliminate voids which may have openings on the side surface of the via hole during the glass cloth etching process. Therefore, it is possible to simultaneously achieve an etching which sufficiently reduces the length of the glass cloth which protrudes from the side wall surface of the through hole and suppresses the etch back phenomenon, and can form a highly reliable plug hole without being caused by the plating solution. Defective flow (decreased fluidity) or etchback. Thus, for example, the present invention can provide a highly reliable multilayer printed wiring board having a small diameter plug hole having a top diameter of not more than 75 μm. [Embodiment] In the figure, 1 represents a glass cloth, 2 represents a thermosetting resin component, 3 represents a prepreg, 4 represents an insulating layer, 5 represents a through hole, 9 represents a plug hole (via a filled hole), and 10 represents a circuit. Substrate. In the following description, the preferred embodiments are illustrated to illustrate the invention. The prepreg in the present invention includes, for example, a glass cloth of a sheet-like fibrous substrate, which is impregnated with a thermosetting resin component. As the glass cloth, a known glass cloth for the prepreg can be used without limitation, and it can be woven or non-woven. Since the woven fabric having high strength is commercially available and is very accommodating -10-200942117, it is preferable to obtain a woven fabric. Further, although the thickness of the glass cloth is not particularly limited, it is preferably not more than 5 〇 μη, particularly preferably 10 - 3 0 μm. Specific examples of the glass cloth in the form of a woven fabric include "STYLE 1027MS" manufactured by Asahi-Schwebel Co., Ltd. (warp density 75 yarn / 25 mm, weft density 75 filament / 25 mm 'cloth weight 20 g/m2, thickness 19 μιη), by Asahi- "STYLE 1 03 7MS" manufactured by Schwebel (warp density 70 silk/25mm, weft density 73 silk/25mm, cloth weight 24g/m2, thickness 28μιη), "1 03 7NS" manufactured by Arisawa Mfg. Warp density 72 wire / 25mm 'Weft density 69 wire / 25mm, cloth weight 23 g / m2, thickness 21μιη), "1 027NS" manufactured by Arisawa Mfg company (warp density 75 wire / 25mm, weft density 75 wire / 25mm , cloth weight 19.5g / m2, thickness 16μιη), "1 01 5NS" manufactured by Arisawa Mfg. (warp density 95 wire / 25 mm, weft density 95 wire / 25 mm, cloth weight 1 7.5 g / m2, Thickness 1 5μιη) 'and so on. Further, specific examples of the glass cloth in the non-woven form include "Cumulass EPM4025" (diameter about 13 μm, fiber length about ΙΟμιη), "Cumulass EPM4100B" (diameter about 13 μm, fiber length about ΙΟμιη) manufactured by Japan Vilene Co., Ltd., etc. . The thermosetting resin component is not particularly limited as long as it is suitable for the insulating layer of the multilayer printed wiring board. For example, a component containing at least a thermosetting resin and a curing agent thereof may be used. For example, the thermosetting resin may be an epoxy resin, a cyanate resin, a phenol resin, a dimethyleneimine-triazine resin, Polyimine resin, acrylic resin, vinyl benzyl resin, and the like. Among these, it is preferred to contain an epoxy resin as a component of the thermosetting -11 - 200942117 resin, for example, a component containing an epoxy resin, a thermoplastic resin, and a curing agent. Examples of the epoxy resin include bisphenol A type epoxy resin, biphenyl type epoxy resin, naphthol type epoxy resin, naphthalene type epoxy resin, bisphenol F type epoxy resin, phosphorus containing epoxy resin, bisphenol S type epoxy resin, alicyclic epoxy resin, aliphatic chain epoxy resin, novolak type epoxy resin, cresol novolak type epoxy resin, bisphenol A aldehyde varnish type epoxy resin, ring having butadiene structure An oxyresin, a propylene oxide ether product of bisphenol, a propylene oxide ether product of naphthalenediol, a propylene oxide ether product of phenol, and a propylene oxide ether product of an alcohol, and an alkyl replacement product of these epoxy resins, halogenated And hydrogenated products and the like. Any one or two or more of these epoxy resins may be used alone to be mixed. As an epoxy resin, bisphenol A type epoxy resin, naphthol type epoxy resin, naphthalene type epoxy resin, biphenyl type from the viewpoints of heat resistance, insulation reliability, and close adhesion to a metal film An epoxy resin and an epoxy resin having a butadiene structure are preferred. Specifically, for example, it may be a liquid biguanide type A epoxy resin ("Epikote 828EL" manufactured by Japan Epoxy Resins Co., Ltd.) or a naphthalene type difunctional epoxy resin (manufactured by Dainippon Ink and Chemicals Co., Ltd.). "HP4032", "HP403 2D"), naphthalene type tetrafunctional epoxy resin ("HP4700" manufactured by Dainippon Ink and Chemicals Co., Ltd.), naphthol type epoxy resin ("ESN-475V" manufactured by Tohto Kasei Co., Ltd. ") "Epoxy resin having a butadiene structure ("PB-3 600" manufactured by DAICEL CHEMICAL INDUSTRIES), epoxy resin having biphenyl structure 200942117 ("NC3000H" manufactured by Nippon Kayaku Co., Ltd.," "NC3000L", "YX4000" manufactured by Japan Epoxy Resins Co., Ltd., and so on. For example, the prepreg may contain a thermoplastic resin in order to impart appropriate flexibility to the component after curing or the like. Examples of such a thermoplastic resin include phenoxy resin, polyvinyl acetal resin, polyimide, polyamidamine, polyether maple, polymill, and the like. Any of these epoxy resines may be used singly or two or more thereof may be mixed. The thermoplastic resin is preferably added in a proportion of 0.5 to 60% by mass, more preferably 3 to 50% by mass, based on 100% by mass of the nonvolatile component in the thermosetting resin component. Specific examples of the phenoxy resin include FX280, FX293 manufactured by Tohto Kasei Co., Ltd., YX8100, YL6954, YL6974, and the like manufactured by Japan Epoxy Resin Co., Ltd.

聚乙烯縮醛樹脂較佳地爲聚乙烯縮丁醛樹脂。聚乙烯 φ 縮醛樹脂的實例包含由 DENKI KAGAKU KOGYO KABUSHIKI KAISHA 公司所製造的 Denka Butyral 4000-2 ' 5000-A、6000-C、6000-EP,由 SEKISUI CHEMICAL 公司所製造的S-LEC BH系列、BX系列、KS系列、BL 系列、B M系列、等等。 聚醯亞胺的具體實例包含由New Japan Chemical公 司所製造的聚醯亞胺 「RIKACOAT SN20」和 「RIKACOAT PN20」。此外,藉由使例如二官能羥基― 端接聚丁二烯等變質的聚醯亞胺、二異氰酸酯化合物及四 -13- 200942117 元酸酐反應而取得的線性聚醯亞胺(在JP-A-2006-37083 中所述者)、具有聚矽氧烷骨架的聚醯亞胺(在JTP-A-2002-1 2667、JP-A-2000-3 1 9386 等等中所述者)、等等。 聚醯胺醯亞胺的具體實例包含由Toyobo公司所製造 的聚醯胺醯亞胺「VYLOMAXHR11NN」、「VYLOMAX HR16NN」、等等。此外,在本發明中的聚醯胺醯亞胺是 包含例如含有聚矽氧烷骨架的聚醯胺醯亞胺等變質聚醯胺 醯亞胺。含有聚矽氧烷骨架的聚醯胺醯亞胺之具體實例包 含由 Hitachi Chemical公司所製造的 「KS9100」、 「KS93 00」、等等。 聚酸碾的具體實例包含由Sumitomo Chemical公司所 製造的聚醚颯「PES 5 003P」、等等。 聚颯的具體實例包含由 Solvay Advanced Polymers K.K公司所製造的聚颯「P1700」、「P3 500」、等等。 固化劑的實例包含胺系固化劑、胍系固化劑、咪唑系 固化劑、酚系固化劑、萘酚系固化劑、酸酐系固化劑、其 環氧加成物、其微膠囊產物、氰酸酯樹脂、等等。在這些 固化劑中,酚系固化劑,萘酚系固化劑及氰酸酯樹脂是較 佳的。在本發明中,可使用單一固化劑或是二或更多種的 組合。 酚系固化劑及萘酚系固化劑的具體實例包含由Meiwa Plastic Industries 公司所製造的 MEH-7700、MEH-7810、 MEH-7 8 5 1、由 Nippon Kayaku 公司所製造的 NHN、 CBN、GPH、由 Tohto Kasei 公司所製造的 SN170、 200942117 SN180 、 SN190 、 SN475 、 SN485 、 SN495 、 SN375 、 SN395、以及由 Dainippon Ink and Chemicals 公司所製造 的 LA7052、LA7054、LA3 0 1 8、LA 1 3 56、等等。 除此之外,氰酸酯樹脂的具體實例包含例如雙酚A 二氰酸酯、多酚氰酸酯(寡聚(3-亞甲基-1,5-伸苯基氰酸 酯))、4,4’-亞甲基雙(2,6-二甲基苯基氰酸酯)、4,4’-亞乙 基二苯基二氰酸酯、六氟雙酚A二氰酸酯、2,2-雙(4-氰 酸酯)苯基丙烷、1,1-雙(4-氰酸酯苯基甲烷)、雙(4-氰酸 酯-3,5-二甲基苯基)甲烷、1,3-雙(4-氰酸酯苯基-1-(甲基 亞乙基))苯、雙(4-氰酸酯苯基)硫醚、雙(4-氰酸酯苯基)醚 等二官能氰酸酯樹脂、酚醛清漆、甲酚醛清漆等衍生的多 官能氰酸酯樹脂、這些氰酸酯樹脂被部份地轉換成三嗪之 預聚物、等等。商業上可取得的氰酸酯樹脂包含酚醛清漆 型多官能氰酸酯樹脂(由 Lonza Japan公司所製造的 「PT30」,氰酸酯當量124)、雙酚A二氰酸酯被部份地 或全部地三氮六環化成爲三聚物之預聚物(由Lonza Japan 公司所製造的「BA2 30」,氰酸酯當量232)、等等。 根據熱固性樹脂與固化劑的種類等,適當地決定熱固 性樹脂與固化劑的混合比例。當熱固性樹脂爲環氧樹脂 時,舉例而言,在酚系固化劑或萘系固化劑的情形中,環 氧樹脂與固化劑的混合比例爲相對於環氧樹脂的1環氧當 量,固化劑的酚系羥當量的比例較佳地在〇.4-2.0的範圍 內,更佳地在0.5-1.0範圍內。在氰酸酯樹脂的情形中, 相對於1環氧當量,氰酸酯當量的比例較佳地在〇.3-3.3 -15- 200942117 的範圍內,更佳地在0.5-2的範圍內。 根據熱固性樹脂與固化劑的種類等,適當地決定熱固 性樹脂與固化劑的混合比例。當熱固性樹脂爲環氧樹脂 時,舉例而言,在酚系固化劑或萘系固化劑的情形中’環 氧樹脂與固化劑的混合比例爲相對於環氧樹脂的1環氧當 量,固化劑的酚系羥當量的比例較佳地在0·4·2·0的範圍 內,更佳地在0.5-1.0範圍內。在氰酸酯樹脂的情形中’ 相對於1環氧當量,氰酸酯當量的比例較佳地在〇.3-3.3 的範圍內,更佳地在0.5-2的範圍內。 熱固性樹脂成份除了固化劑之外,又含有固化加速 劑。此固化加速劑的實例包含咪唑系化合物、有機膦系化 合物、等等,具體實例包含 2-甲基咪唑、三苯膦、等 等。當使用固化加速劑時,較佳地使用相對於環氧樹指爲 0.1-3.0質量%的比例。當使用氰酸酯樹脂作爲環氧樹脂固 化劑時,可添加有機金屬化合物,以縮短固化時間,此有 機金屬化合物習知上作爲使用環氧樹脂成份及氰酸酯化合 物結合的系統中的固化催化劑。此有機金屬化合物的實例 包含例如乙醯丙酮銅(II)等有機銅化合物、乙醯丙酮鋅(II) 等有機鋅化化合物、乙醯丙酮鈷(II)、乙醯丙酮鈷(III)等 有機鈷化合物、等等,它們可以被單獨使用或二或三種相 結合使用。相對於氣酸酯樹脂,以金屬爲基礎,要添加的 有機金屬化合物的數量一般在1 0-500 ppm的範圍內,較 佳地在25-200 ppm的範圍內。 熱固性樹脂成份可以含有無機塡充物,以供固化後成 -16- 200942117 份的低熱膨脹用。此無機塡充物的實例包含二氧化矽、氧 化鋁、魚膠、雲母、矽酸鹽、硫酸鋇、氫氧化鎂、氧化鈦 等等。在這些實例中,氧化矽和氧化鋁是較佳的,氧化矽 是特別較佳的。從絕緣可靠度的觀點而言,無機塡充物較 佳地具有不大於3 μιη的平均粒度,更佳地不大於1.5 μιη。 當熱固性樹脂成份的非發揮性成份爲1 〇〇質量%時,在熱 固性樹脂中的無機塡充物的含量較佳地爲20-60質量%, @ 更佳地爲2 0 - 5 0質量%。 此外,當需要時,熱固性樹脂成份可以含有其它成 份。其它成份的實例包含例如有機磷系耐燃劑、有機含氮 磷化合物、氮化合物、矽系耐燃劑、金屬氫氧化物等耐燃 劑;例如矽樹脂粉末、尼龍粉末、氟粉末等有機塡充物; 例如歐本(ORBEN )、本頓(BENTON )等厚化劑;例如 矽系、氟系等聚合消泡劑或調平劑;例如咪唑系、噻唑 系、三唑系、矽烷系耦合劑等緊密黏著施加劑;例如酞青 φ 藍、酞青綠、碘綠、雙偶氮黃、碳黑等著色劑、等等。 要被使用於本發明的預浸體可以由已知的熱熔法、溶 劑法等來予以製造。根據熱熔法,不將熱固性樹脂成份溶 於有機溶劑中,將熱固性樹脂成份一次塗著於釋放紙上以 及將其層疊於片狀纖維基板上、或以模塗著器將其直接塗 著等等’以製造本發明中所使用的預浸體,所述釋放紙顯 示從成份釋放的良好釋放特性。根據溶劑法,將片狀纖維 基板浸漬於樹脂清漆中以允許片狀纖維由樹脂成份清漆浸 漬’接著’將其乾燥,樹脂成份清漆係藉由將熱固性樹脂 -17- 200942117 成份溶解於有機溶劑中而取得的。也可以在從片狀纖維基 板的二表面加熱及施壓的條件下,將疊層於塑膠膜上包含 熱固性樹脂成份的複數個黏著膜連續地層疊,以製備預浸 體。用於製備清漆的有機溶劑的實例包含例如丙酮、甲基 乙基酮、環已酮等酮類、例如乙酸乙酯、乙酸丁酯、乙二 醇醚乙酸酯、丙二醇單甲基醚乙酸酯、卡必醇乙酸酯等乙 酸酯、例如乙二醇醚、丁基卡必醇等卡必醇、例如甲苯、 二甲苯等芳族烴、二甲基甲醯胺、二甲基乙醯胺、N-甲基 吡咯啶酮、等等。這些有機溶劑可以被單獨使用或二或更 多種結合使用。 雖然乾燥條件並無特別限定,但是,重要的是,當預 浸體要被層疊於電路基板等之上時,在乾燥期間,抑制熱 固性樹脂成份的固化進展,以保持預浸體的黏著力。由於 當有機溶劑大量地維持於預浸體中時,在固化後會發生膨 脹,所以,將預浸體乾燥至熱固性樹脂成份中的有機溶劑 的含量大致上爲5重量%或更低,較佳地2重量%或更 低。雖然具體的乾燥件會視熱固性樹脂成份的固化特性及 清漆中的有機溶劑的數量而定,但是,舉例而言,含有 30-60重量%的有機溶劑之清漆大致上在80- 1 80°C下乾燥 約3-13分鐘。藉由簡單的實驗,習於此技藝者可以適當 地決定乾燥條件。 預浸體的厚度(當由溶劑法形成時乾燥後的厚度)較 佳地爲20-100μιη。在此範圍內的厚度有利於製造平坦及 薄的絕緣層。更精確而言,當預浸體具有小於20μιη的厚 200942117 度時,預浸體無法以足夠高的平坦特徵容易地層疊於電路 基板上,以及,當其超過100 μιη時,無法將多層印刷配 線板有利地製成薄的。 圖1(a)—圖1(f)是使用預浸體之本發明的多層印刷配 線板的製造方法的一實施例的步驟的剖面視圖。在圖式 中,與圖4中相同的代號顯示相同或對應的構件。 首先,製備包含玻璃布1的預浸體3及電路基板 10(圖1(a)、( b)),玻璃布1以熱固性樹脂成份2來予 以浸漬,預浸體3層疊於電路基板1 0的至少一表面上以 遮蓋電路基板10的表面上的導電電路層(墊)11,以及, 將熱固性樹脂成份2固化以造成絕緣層4(圖1(c))。如圖 1 ( c)所示,雖然基本上將一片預浸體(一層)層疊於預 浸體3的電路基板10上,但是,可以以不小於2片(2 層)來層疊。因此,絕緣層 4的厚度較佳地爲 20-ΙΟΟμιη,更佳地爲 30-70μπι。 在絕緣層4中的玻璃布及樹脂成份的構成比例由預浸 體3的玻璃布與樹脂成份的構成比例決定。其也會隨著玻 璃布的密度、布重量等等而變。但是’爲了將導電電路層 (墊)11嵌入於電路基板10的表面上(亦即’嵌入整體 導電電路層11(墊)),預浸體應含有足夠數量的樹脂。 如此,玻璃布及樹脂成份的構成比例以質量比而言大致上 較佳地爲1:0.65-9,更佳地爲1:4-5(玻璃布:樹脂成 份)。預浸體中的樹脂成份的質量可以從預浸體的質量與 玻璃布的質量的差値取得。 -19- 200942117 爲了藉由熱固化預浸體3(熱固樹脂成份2)來形成絕 緣層4,可以使用以預浸體來形成電路基板的絕緣層之習 知方法。舉例而言,預浸體係層疊於電路基板的一或二表 面上,以及,在降壓下經由釋放片,使用例如SUS面板 等金屬板,對疊層加熱及施壓。壓力較佳地爲 5-40 kgf/cm2(49xl 04-392 xl04 N/m2),溫度較佳地爲 120-200 °C,施壓時間較佳地爲15-100分鐘。The polyvinyl acetal resin is preferably a polyvinyl butyral resin. Examples of the polyethylene φ acetal resin include Denka Butyral 4000-2 '5000-A, 6000-C, 6000-EP manufactured by DENKI KAGAKU KOGYO KABUSHIKI KAISHA Co., Ltd., S-LEC BH series manufactured by SEKISUI CHEMICAL Co., Ltd. BX series, KS series, BL series, BM series, and so on. Specific examples of the polyimine include polyethylenimine "RIKACOAT SN20" and "RIKACOAT PN20" manufactured by New Japan Chemical Co., Ltd. Further, a linear polyimine obtained by reacting a polyimine, a diisocyanate compound such as a difunctional hydroxyl group-terminated polybutadiene, and a tetra--13-200942117-acid anhydride (in JP-A- Polyamines having a polyoxyalkylene skeleton (described in JTP-A-2002-1 2667, JP-A-2000-3 1 9386, etc.), etc., as described in 2006-37083 . Specific examples of the polyamidoximine include polyamidoquinone imine "VYLOMAXHR11NN" manufactured by Toyobo Co., "VYLOMAX HR16NN", and the like. Further, the polyamidoximine in the present invention is a modified polyamidoximine containing, for example, a polyamidoximine containing a polyoxyalkylene skeleton. Specific examples of the polyamidoximine containing a polyoxyalkylene skeleton include "KS9100", "KS93 00", and the like manufactured by Hitachi Chemical Co., Ltd. Specific examples of the polyacid mill include polyether oxime "PES 5 003P" manufactured by Sumitomo Chemical Co., Ltd., and the like. Specific examples of the polypeptone include polypene "P1700", "P3 500" manufactured by Solvay Advanced Polymers K.K, and the like. Examples of the curing agent include an amine curing agent, an oxime curing agent, an imidazole curing agent, a phenol curing agent, a naphthol curing agent, an acid anhydride curing agent, an epoxy addition product thereof, a microcapsule product thereof, and cyanic acid. Ester resin, and the like. Among these curing agents, a phenol curing agent, a naphthol curing agent and a cyanate resin are preferred. In the present invention, a single curing agent or a combination of two or more may be used. Specific examples of the phenolic curing agent and the naphthol-based curing agent include MEH-7700, MEH-7810, MEH-7 8 5 1 manufactured by Meiwa Plastic Industries, and NHN, CBN, GPH manufactured by Nippon Kayaku Co., Ltd. SN170, 200942117 SN180, SN190, SN475, SN485, SN495, SN375, SN395, manufactured by Tohto Kasei, and LA7052, LA7054, LA3 0 18, LA 1 3 56, etc. manufactured by Dainippon Ink and Chemicals . Besides, specific examples of the cyanate resin include, for example, bisphenol A dicyanate, polyphenol cyanate (oligo(3-methylene-1,5-phenylene)), 4,4'-methylenebis(2,6-dimethylphenyl cyanate), 4,4'-ethylenediphenyl dicyanate, hexafluorobisphenol A dicyanate, 2,2-bis(4-cyanate)phenylpropane, 1,1-bis(4-cyanate phenylmethane), bis(4-cyanate-3,5-dimethylphenyl) Methane, 1,3-bis(4-cyanate phenyl-1-(methylethylidene))benzene, bis(4-cyanate phenyl) sulfide, bis(4-cyanate phenyl) a polyfunctional cyanate resin derived from a difunctional cyanate resin such as an ether, a novolac, a cresol or the like, a cyanate resin partially converted into a prepolymer of a triazine, and the like. The commercially available cyanate resin contains a novolac type polyfunctional cyanate resin ("PT30" manufactured by Lonza Japan Co., Ltd., cyanate equivalent 124), and bisphenol A dicyanate is partially or All of the triazine was cyclized to a prepolymer of a terpolymer ("BA2 30" manufactured by Lonza Japan Co., Ltd., cyanate equivalent 232), and the like. The mixing ratio of the thermosetting resin to the curing agent is appropriately determined depending on the type of the thermosetting resin and the curing agent. When the thermosetting resin is an epoxy resin, for example, in the case of a phenolic curing agent or a naphthalene curing agent, the mixing ratio of the epoxy resin to the curing agent is 1 epoxy equivalent with respect to the epoxy resin, and the curing agent The proportion of the phenolic hydroxyl equivalent is preferably in the range of from 4-.4 to 2.0, more preferably in the range of from 0.5 to 1.0. In the case of the cyanate resin, the ratio of the cyanate equivalents with respect to 1 epoxy equivalent is preferably in the range of 〇.3-3.3 -15 to 200942117, more preferably in the range of 0.5-2. The mixing ratio of the thermosetting resin to the curing agent is appropriately determined depending on the type of the thermosetting resin and the curing agent. When the thermosetting resin is an epoxy resin, for example, in the case of a phenolic curing agent or a naphthalene curing agent, the mixing ratio of the epoxy resin to the curing agent is 1 epoxy equivalent with respect to the epoxy resin, and the curing agent The ratio of the phenolic hydroxyl equivalent is preferably in the range of 0·4·2·0, more preferably in the range of 0.5 to 1.0. In the case of the cyanate resin, the ratio of the cyanate equivalent to 1 equivalent of the epoxy equivalent is preferably in the range of 〇.3-3.3, more preferably in the range of 0.5-2. The thermosetting resin component contains a curing accelerator in addition to the curing agent. Examples of the curing accelerator include an imidazole compound, an organic phosphine compound, and the like, and specific examples include 2-methylimidazole, triphenylphosphine, and the like. When a curing accelerator is used, a ratio of 0.1 to 3.0% by mass based on the epoxy resin is preferably used. When a cyanate resin is used as the epoxy resin curing agent, an organometallic compound may be added to shorten the curing time, and the organometallic compound is conventionally used as a curing catalyst in a system using an epoxy resin component and a cyanate compound. . Examples of the organometallic compound include, for example, an organic copper compound such as copper (II) acetate, an organic zinc compound such as zinc(II) acetate, cobalt (II) acetate, and cobalt (III). Cobalt compounds, and the like, they may be used singly or in combination of two or three. The amount of the organometallic compound to be added is generally in the range of from 10 to 500 ppm, preferably from 25 to 200 ppm, based on the metal ester resin. The thermosetting resin component may contain an inorganic chelating agent for curing to a low thermal expansion of -16 to 200942117 parts. Examples of the inorganic chelating agent include cerium oxide, aluminum oxide, fish gelatin, mica, silicate, barium sulfate, magnesium hydroxide, titanium oxide, and the like. Among these examples, cerium oxide and aluminum oxide are preferred, and cerium oxide is particularly preferred. The inorganic ruthenium preferably has an average particle size of not more than 3 μm, more preferably not more than 1.5 μm from the viewpoint of insulation reliability. When the non-functional component of the thermosetting resin component is 1% by mass, the content of the inorganic filler in the thermosetting resin is preferably 20 to 60% by mass, @ more preferably 2 to 50% by mass. . Further, the thermosetting resin component may contain other components as needed. Examples of the other components include, for example, an organic phosphorus-based flame retardant, an organic nitrogen-containing phosphorus compound, a nitrogen compound, a lanthanide-based flame retardant, a metal hydroxide, and the like; and an organic filler such as a ruthenium resin powder, a nylon powder, or a fluorine powder; For example, thickeners such as ORBEN and BENTON; for example, polymeric antifoaming agents or leveling agents such as lanthanides and fluorines; for example, imidazoles, thiazoles, triazoles, decane-based coupling agents, etc. Adhesive application agent; for example, indigo blue, indocyanine green, iodine green, disazo yellow, carbon black and the like, and the like. The prepreg to be used in the present invention can be produced by a known hot melt method, solvent method or the like. According to the hot melt method, the thermosetting resin component is not dissolved in the organic solvent, the thermosetting resin component is once coated on the release paper and laminated on the sheet fiber substrate, or directly coated by a die coater, etc. 'To make the prepreg used in the present invention, the release paper showed good release characteristics released from the components. According to the solvent method, the sheet-like fiber substrate is immersed in the resin varnish to allow the sheet-like fiber to be impregnated by the resin component varnish, which is then dried, and the resin component varnish is dissolved in the organic solvent by the thermosetting resin -17-200942117 component. And achieved. It is also possible to continuously laminate a plurality of adhesive films comprising a thermosetting resin component laminated on a plastic film under conditions of heating and pressing from the both surfaces of the sheet-like fibrous substrate to prepare a prepreg. Examples of the organic solvent used for the preparation of the varnish include ketones such as acetone, methyl ethyl ketone, cyclohexanone, etc., such as ethyl acetate, butyl acetate, glycol ether acetate, propylene glycol monomethyl ether acetate Acetate such as ester or carbitol acetate, carbitol such as glycol ether or butyl carbitol, aromatic hydrocarbon such as toluene or xylene, dimethylformamide, dimethyl Indoleamine, N-methylpyrrolidone, and the like. These organic solvents may be used singly or in combination of two or more. Although the drying conditions are not particularly limited, it is important that when the prepreg is to be laminated on a circuit board or the like, the progress of curing of the thermosetting resin component is suppressed during drying to maintain the adhesion of the prepreg. Since the swelling occurs after curing when the organic solvent is largely maintained in the prepreg, the content of the organic solvent in which the prepreg is dried to the thermosetting resin component is substantially 5% by weight or less, preferably. Ground 2% by weight or less. Although the specific drying member depends on the curing characteristics of the thermosetting resin component and the amount of the organic solvent in the varnish, for example, the varnish containing 30 to 60% by weight of the organic solvent is substantially 80 to 180 ° C. Dry down for about 3-13 minutes. By simple experimentation, those skilled in the art can appropriately determine the drying conditions. The thickness of the prepreg (thickness after drying when formed by a solvent method) is preferably from 20 to 100 μm. The thickness within this range facilitates the fabrication of a flat and thin insulating layer. More precisely, when the prepreg has a thickness of 200942117 degrees of less than 20 μm, the prepreg cannot be easily laminated on the circuit substrate with sufficiently high flat characteristics, and when it exceeds 100 μm, the multilayer printed wiring cannot be printed. The plate is advantageously made thin. Fig. 1 (a) - Fig. 1 (f) is a cross-sectional view showing the steps of an embodiment of a method of manufacturing a multilayer printed wiring board of the present invention using a prepreg. In the drawings, the same reference numerals as in Fig. 4 show the same or corresponding components. First, a prepreg 3 including a glass cloth 1 and a circuit board 10 (Fig. 1 (a), (b)) are prepared, and the glass cloth 1 is immersed in a thermosetting resin component 2, and the prepreg 3 is laminated on the circuit substrate 10 At least one surface covers the conductive circuit layer (pad) 11 on the surface of the circuit substrate 10, and the thermosetting resin component 2 is cured to form the insulating layer 4 (Fig. 1(c)). As shown in Fig. 1 (c), although a single prepreg (one layer) is laminated on the circuit board 10 of the prepreg 3, it may be laminated in not less than two sheets (two layers). Therefore, the thickness of the insulating layer 4 is preferably 20-Å μm, more preferably 30-70 μm. The composition ratio of the glass cloth and the resin component in the insulating layer 4 is determined by the ratio of the composition of the glass cloth and the resin component of the prepreg 3. It also varies with the density of the glass cloth, the weight of the cloth, and the like. However, in order to embed the conductive circuit layer (pad) 11 on the surface of the circuit substrate 10 (i.e., 'embedded in the integral conductive circuit layer 11 (pad)), the prepreg should contain a sufficient amount of resin. Thus, the composition ratio of the glass cloth and the resin component is substantially preferably 1:0.65-9, more preferably 1:4-5 (glass cloth: resin component) in terms of mass ratio. The quality of the resin component in the prepreg can be obtained from the difference between the quality of the prepreg and the quality of the glass cloth. -19- 200942117 In order to form the insulating layer 4 by thermally curing the prepreg 3 (thermosetting resin component 2), a conventional method of forming an insulating layer of a circuit substrate with a prepreg can be used. For example, the prepreg system is laminated on one or both surfaces of the circuit board, and the laminate is heated and pressed via a release sheet using a metal plate such as an SUS panel under reduced pressure. The pressure is preferably 5-40 kgf/cm2 (49xl 04-392 x 104 N/m2), the temperature is preferably 120-200 ° C, and the pressing time is preferably 15-100 minutes.

雖然熱固化條件會隨熱固性樹脂成份的種類等而變, 但是,固化溫度通常約1 20-200 °C,適當的固化時間約 1 5-100 分鐘。 如圖1(d)所示,在藉由熱固化預浸體3(熱固化樹 脂成份2)而取得的絕緣層4中,藉由雷射照射以形成通 孔(肓孔)5。在此情況中,由於玻璃布1與絕緣層4 (熱固 性樹脂成份2的固化產物)的處理力的差異而從通孔 5(圖1(d))的側壁表面凸出。Although the heat curing conditions vary depending on the type of the thermosetting resin component, etc., the curing temperature is usually about 1 20 to 200 ° C, and the appropriate curing time is about 1 to 100 minutes. As shown in Fig. 1(d), in the insulating layer 4 obtained by thermally curing the prepreg 3 (thermosetting resin component 2), a through hole (pupil) 5 is formed by laser irradiation. In this case, the surface of the through hole 5 (Fig. 1 (d)) protrudes due to the difference in the processing force of the glass cloth 1 and the insulating layer 4 (cured product of the thermosetting resin component 2).

做爲上述雷射,可以使用二氧化碳氣體雷射、YAG 雷射、準分子雷射、等等,從處理速率及成本的觀點而As the above laser, carbon dioxide gas laser, YAG laser, excimer laser, etc. can be used, from the viewpoint of processing rate and cost.

爲了多層印刷配線板的高密度佈線,通孔5的頂部直 徑較佳不大於75μιη,更佳地不大於70μιη,又更佳地不大 於67μιη。對於具有不大於75μιη的頂部直徑之小直徑通 孔’玻璃布從通孔的側壁表面突出成爲更加値得注意的問 題’而本發明的製造方法證明特別有利。 在形成通孔5之後,以玻璃蝕刻溶液蝕刻從通孔5的 -20- 200942117 壁表面凸出的玻璃布1,以消除從通孔5的壁面凸出的玻 璃布1 (圖1(e))。關於玻璃蝕刻溶液,可以使用例如氫氟 酸溶液、氟硼酸溶液 '氟化銨溶液等習知溶液。商業上可 取得的玻璃蝕刻溶液的實例包含由Meltex公司所製造的 「Enplate MLB GLASS ETCH ADDITIVE」等等。商業上 可取得的玻璃蝕刻溶液一般在使用前會先稀釋。舉例而 言,當玻璃蝕刻溶液爲氟硼酸溶液時,氟硼酸的濃度一般 約爲50 g/L,在使用前,以離子交換水、蒸餾水等將此溶 液稀釋至 5 mL/L-200 mL/L的範圍,較佳地,10 mL/L-100 mL/L。做爲蝕刻方法,包含將具有通孔的疊層浸漬於 溶液中之方法、以及包含噴灑溶液於通孔中之方法,噴灑 法在溶液於通孔中的穿透性上是較優的。爲了抑制下述的 去塗抹處理之後玻璃布1的凸出長度,考慮去塗抹造成之 通孔側壁的碎屑,較佳地使用這些溶液以實施玻璃布的蝕 刻,以蝕刻從通孔側壁表面至樹脂(絕緣層4)的內部之 玻璃布,一般可達到始於通孔側壁表面、以及在樹脂內部 (絕緣層4)約2μπι。因此,藉由使用玻璃蝕刻溶液的鈾 刻處理,可以在通孔5的側壁表面上形成具有開口的空隙 S (請參見圖1(e))。 在使用上述玻璃蝕刻溶液的玻璃布1的蝕刻處理之 後,通孔5受到去塗抹處理(圖1(f))。關於此去塗抹處 理,可使用包含將具有通孔5的疊層浸漬於氧化劑溶液中 之方法,以及包含噴灑氧化劑溶液至通孔中的方法。氧化 劑溶液的實例包含濃縮的硫酸、鉻酸、或其混合酸、或過 -21 - 200942117 錳酸鹼金屬鹽水溶液(過錳酸鈉水溶液、過錳酸鉀水溶液) 等等,較佳的是過錳酸鹼金屬鹽水溶液。這些氧化劑溶液 是商業上可取得的用於印刷配線板的化學品,以及,可以 原樣地使用這些商業上可取得的產品。做爲過錳酸鹼金屬 鹽水溶液,可爲由 Meltex公司所製造的「Enplate MLB-4 97」等等。藉由去塗抹處理,通孔5的側壁上的熱固性 樹脂成份的固化產物(樹脂固化產物)會藉由氧化劑來使 其碎裂,以及,可以消除因玻璃布蝕刻處理而形成之在通 空 5側壁表面上具有開口的上述空隙 S (請參見圖 1(e))。爲了確定地消除空隙S,需要充分地實施熱塗抹處 理。雖然玻璃布的尖端有點凸出,但是,其突出量可以 小,而且,比用以形成通孔5 (圖1 (f))的雷射處理(圖 1 (d))期間所形成的突出顯著地小。爲了增進通孔中電鍍 液的流動,在去塗抹處理之後從通孔的側壁凸出的玻璃布 1的長度較佳地不大於6μπι,更佳地不大於5μιη,仍然更 佳地不大於4μιη、以及,又進一步較佳地不大於3μιη。 在使用過錳酸鹼金屬鹽水溶液的去塗抹處理中,在使 用過錳酸鹼金屬鹽水溶液處理之前,較佳地使用膨脹劑溶 液以實施膨脹處理,以及,在使用過錳酸鹼金屬鹽水溶液 的處理之後,較佳地使用還原劑以實施後置處理(中和處 理)。膨脹劑溶液及還原劑溶液是商業上可取得的用於印 刷配線板的化學品,以及,可以原樣地使用這些商業上可 取得的產品。膨脹劑溶液的實例包含由Meltex公司所製 造的「Melplate MLB-6001」、「Melplate MLB-495」、 200942117 「Melplate MLB-496」、等等,還原劑溶液的實例包含由 Meltex公司所製造的「Enplate MLB-790M」、等等。 使用氧化劑溶液的通孔的去塗抹處理也爲絕緣層的表 面的粗糙化處理。在此情況中,考慮超精密佈線形成以及 佈線的緊密黏著強度,在粗糙化處理之後的絕緣層4的表 面粗糙度希望不小於Ο.ίμιη且不大於1·5μιη之表面粗糙 度Ra値。表面粗糙度Ra値是顯示表面粗糙度的一種數 値,稱爲算術平均粗糙度。明確而言,藉由測量測量區域 內變化之距離作爲平均線的表面之高度的絕對値,以及計 算算術平均値,取得表面粗糙度Ra値。舉例而言,使用 由 Veeco Instruments 公司所製造的 WYKO NT3 3 00,以 121μηιχ92μιη的5 0x透鏡的測量範圍之VSI接觸模式,取 得數値,從所取得的數値取得表面粗糙度Ra値。 在先前技術文獻2中,指出由於雷射照射至玻璃布而 熔化的基質(matrix)樹脂之附著,氟化物無法接觸玻璃布 以及抵抗蝕刻的有效去除等問題。根據本發明人的硏究, 這些問題不會突顯。這被視爲導因於先前技術文獻2與本 發明之間的不同處理之基質樹脂的不同固化狀態之間的差 異,由於先前技術文獻2中所述的方法包含同時熱固化, 在一批次中同時熱壓預浸體及銅以形成絕緣層及導電層, 但是,本發明的實施例使用之製程實質上包含二步驟熱固 化處理以藉由電鍍來形成導電層,其中,疊層於電路基板 上的預浸體在導電層形成之後受到熱固化及退火處理。 在本發明中具有絕緣層的電路基板可以在需要時形成 -23- 200942117 穿透孔(貫通孔)。穿透孔可以藉由傳統上習知的方法來 予以形成,一般使用機械鑽孔。此外,也可以使用包含化 學處理銅箔表面及施加雷射照射之方法。在多層印刷配線 板中,穿透孔通常形成於核心基板中。在本發明中,在累 積例如絕緣層4等絕緣層時,通常藉由通孔以取得導通。 本發明的多層印刷配線板的製造方法,在上述絕緣層 中形成通孔之後,又包含:玻璃蝕刻處理及去塗抹處理, 藉由電漿以在絕緣層表面中形成導電層的電鍍程序,以 及,在導電層形成之後,藉由加熱之電路基板的退火處 理,以及,在導電層中形成電路。可以根據習於此技藝者 所熟知的不同方法及用於多層印刷配線板的不同方法,來 實施這些步驟。 在藉由電鍍以形成導電層的電鍍程序中,當絕緣層的 表面粗糙化時,藉由固著效果,可以增進導電層對絕緣層 的緊密黏著。如上所述,因此,在玻璃布的蝕刻處理之後 的去塗抹處理中,絕緣層較佳地受到同時表面粗糙化處 理。在電鍍程序中,也在通孔中形成電鍍。 使用結合無電電鍍及電解電鍍之方法,以電鍍來形成 導電層。或者,形成圖案與導電層的圖案相反的抗電鍍油 墨,單獨以無電電鍍來形成導電層。導電層一般由銅、黃 金、銀、鎳、錫、等所形成,銅是較佳的。無電電鏟層較 佳地具有〇.1-3μιη的厚度,更佳地〇.3-2μιη’以及,電解 電鍍層具有的厚度較佳地與無電電銨層的厚度之總厚度爲 3-35μιη,更佳地爲5-20μιη。此外,通孔可以由接續於電 200942117 層形成之後的電鍍所塡充的塞孔。 在例如導電層形成之後,以約15〇-200°C的溫度,將 電路基板(絕緣層及導電層)加熱約20-90分鐘’以實施 退火處理。藉由退火處理,可以進一步增進及穩定導電層 的剝離強度。 關於電路形成步驟,舉例而言,可以使用削減製程、 半添加製程等等。爲了形成精密線,半添加製程是較佳 的,其中,圖案抗電鍍油墨塗敷至無電電鍍層上,形成具 〇 有所需厚度的電解電鑛層(圖案電鍍層),將圖案抗電鍍 油墨分離,以及,藉由快速蝕刻來去除無電電鍍層而產生 電路。 圖2(a)-圖2(c)顯示從導電層至電路形成的一系列步 驟之一實施例。藉由電解電鍍(圖2(a)),在絕緣層4的 表面上以及通孔5的內部,形成種子層(導電層)6,將圖 案抗電鎪油墨7塗敷至種子層6,以形成完全地塡充導通 0 孔的電解電鍍層(圖案電鎪層)8,之後,將圖案抗電鍍 油墨7分離及藉由快速餓刻以去除無電電鑛層8,因而形 成具有塡充塞孔9的電路(圖2(c))。 如上所述’根據本發明的方法,玻璃布1從形成於含 有玻璃布1之絕緣層4中的通孔5的壁面凸突出的長度足 夠小’以及,可以抑制回蝕現象。因此,可以確定地形成 高度可靠的塞孔9。亦即,可以取得具有含有塞孔9的電 路之多層印刷配線板’其中,以積層法形成含有玻璃布1 的絕緣層4’玻璃布1從形成於絕緣層4中的通孔5的側 -25- 200942117 壁凸出6μιη或更少的長度,以及,玻璃布1的凸出部份 嵌入於形成塞孔9的導電層(種子層6和電解電鍍層8) 中。 用於本發明的多層印刷配線板的製造之電路基板主要 意指玻璃環氧基板、金屬基板、聚酯基板、聚醯亞胺基 板、ΒΤ樹脂基板、熱固聚苯醚基板等等,其中,其一或 二表面具有圖案處理過的導電層(電路)。在本發明中的 電路基板也涵蓋中間產物的內部層電路基板,在內部層電 路基板上,將形成用於多層印刷配線板的製造之絕緣層及 /或導電層。由於可以取得絕緣層與電路基板的緊密黏 著,所以,以塗黑處理等,將導電電路層的表面較佳地預 先粗糙化。 在下述中,將參考實施例及比較實施例來詳述本發 明。在下述中,「份」意指「質量份」。 <預浸體的製造> 將液體雙酚Α型環氧樹脂(環氧當量180,由Japan Epoxy Resins 公司所製造的「Epikote 828EL」,28 份) 及萘型四官能環氧樹脂(環氧當量163’由Dainippon Ink and Chemicals公司所製造的「 HP4700」,28份)溶解 於甲基乙基酮(此後簡寫爲「MEK」,15份)與環己酮 (15份)的混合溶液中,並攪拌及同時加熱。在此混合 溶液中,加入具有50%的固體含量之萘酚系固化劑(由 Tohto Kasei公司所製造的「SN-485」,酚系羥基當量 200942117 215)、固化觸媒(由SHIKOKU CHEMICALS公司所製造的 「2E4MZ」,0.1份)、球形氧化矽(平均粒度〇.5μιη, 由Admatechs公司所製造的「SO-C2」,70份)、以及聚 乙烯縮丁醛樹脂溶液(由SEKISUI CHEMICAL公司所製造 的「KS-1」溶液,乙醇與甲苯以1:1(質量比)混合的溶 液,具有15% (質量%)的固體含量,30份),以及,以高 速旋轉混合器,將混合物均勻地分散,以產生樹脂清漆。 以所述樹脂清漆浸漬由 Asahi-Schwebel公司所製造 的1 02 7MS玻璃布(厚度19μιη),並將其在80-120°C下乾 燥,以產生厚度50μιη的預浸體。將聚(對苯二甲酸乙二 醇酯)膜(厚度38μιη,此後縮寫爲「PET膜」)從一側及將 厚度15 μπι的聚丙烯膜(保護膜)從對立側疊加於其上, 以及,將疊層捲繞成捲。然後,以502 mm的寬度將此捲 割成長條以產生二捲5 0m之捲繞預浸體(玻璃布與樹脂 成份的構成比例(質量比)是1:5)。 <實例1 > 在電路形成之後(電路導體厚度1 8μηι),將具有PET 膜的保護膜分離預浸體層疊於厚度〇.2mm之銅包覆疊層 板(電路基板)的二側上。將PET膜分離,以及,將疊層熱 固化以在上述電路基板的一表面上形成厚度32μιη的絕緣 層。然後,以二氧化碳氣體雷射,在層疊於電路基板的一 表面上之絕緣層中,形成頂部直徑60μιη、底部直徑50μιη 的通孔。 -27- 200942117 所造成的電路基板浸漬於4(TC的含水溶液中5分 鐘,以鈾刻玻璃布,所述含水溶液是以離子交換水稀釋濃 度約50g/L的含氟硼酸之玻璃蝕刻溶液(由Meltex公司 所製造的「Enplate MLB GLASS ETCH ADDITIVE」)至 20 mL/L的濃度而取得的。然後,使通孔受到去塗抹處 理。去塗抹處理也作爲絕緣層的表面的粗糙化處理,以 及,包含浸漬於 60 °C的由 Meltex公司所製造的 「Melplate MLB-600 1」中 5 分鐘,浸漬於 8 0 °C的由 Meltex公司所製造的「Enplate MLB-479」中20分鐘,及 浸漬於 40°C的由 Meltex公司所製造的「Enplate MLB-790」中5分鐘,「Melplate MLB-6001」是作爲膨脹劑溶 液,「Enplate MLB-479」是溶液過錳酸鹼金屬鹽水溶 液,作爲氧化劑溶液,「Enplate MLB-790」作爲還原劑 溶液。 在玻璃蝕刻處理及去塗抹處理(粗糙化處理)之後, 以由Hitachi High-Technologies公司所製造的型號「SU-1500」之掃描式電子顯微鏡(SEM),觀察電路基板中的通 孔的剖面,以及,測量通孔側壁中的空隙長度(亦即,圖 1(e)中所示之通孔的側壁表面上具有開口的空隙S的長 度)及玻璃布的凸出長度。 在形成於電路基板中具有高玻璃布密度的纖維束的交 叉點處的通孔中,實施測量,以及,將SEM相片上最長 的空隙長度及最長的凸出長度取爲代表値。 如圖3(a)所示,SEM相片上的「空隙長度」定義爲參 -28- 200942117 考點X與空隙S離側壁5 a最遠的位置之間水平方向(亦 即,與絕緣層4的上表面4a相平行之方向)上的線性距 離,參考點X是通孔5中的側壁5a中的空隙S的開口的 近似中心。如圖3(b)所示,SEM相片上的「凸出長度」 定義爲參考點X與玻璃布的尖端之間水平方向(亦即, 與絕緣層4的上表面4a相平行之方向)上的線性距離 B,參考點X是從通孔5中的側壁5a凸出的玻璃布1的 凸出部份的根部的近似中心。 在玻璃蝕刻處理之後,將部份電路基板分開。測量分 開的電路基板的通孔中的空隙長度,使其餘的電路基板受 到去塗抹處理,以及,測量其餘的電路基板的導通孔中玻 璃布的凸出長度。 此外,以下述方法測量絕緣層的表面粗糙度,以找出 Ra(算術平均粗糙度)=8 00 run。 <絕緣層的表面粗糙度測量> 使用非接觸式粗度儀(由Veeco Instruments公司所製 造的 WYKO NT33 00),在 121 μιηχ92μιη 的 50χ 透鏡之測 量範圍’在VSI接觸模式下,決定絕緣層的表面的Ra(算 術平均粗糙度)。 <實例2 > 除了以離子交換水將玻璃蝕刻溶液(由Meltex公司所 製造的「Enplate MLB GL AS S ETCH ADDITIVE」)稀釋至 -29- 200942117 3 5mL/L的濃度以取得含水溶液之外,以同於實例1的方 式,實施操作及測量。絕緣層的表面具有8 00nm的Ra(算 術平均粗糙度)。 <實例3 > 除了以離子交換水將玻瑪蝕刻溶液(由Meltex公司所 製造的「Enplate MLB GL AS S ETCH ADDITIVE」)稀釋至 5 OmL/L的濃度以取得含水溶液之外,以同於實例1的方 式,實施操作及測量。絕緣層的表面具有的Ra(算 術平均粗糙度)。 <比較實例1 > 除了省略玻璃蝕刻之外,以同於實例1的方式,實施 操作及測量。 <比較實例2 > 除了在絕緣層的表面的粗糙化處理(也作爲去塗抹處 理)之後實施玻璃鈾刻之外,以同於實例1的方式,實施 操作及測量。 <比較實例3 > 除了在絕緣層的表面的粗糙化處理(也作爲去塗抹處 理)之後實施玻璃蝕刻之外,以同於實例2的方式,實施 操作及測量。 -30- 200942117 <比較實例4 > 除了在絕緣層的表面的粗糙化處理(也作爲去塗抹處 理)之後實施玻璃蝕刻之外,以同於實例1的方式,實施 操作及測量。 實例1-3及比較實例1-4的結果顯示於表1中。 <表1 > 玻璃蝕 刻步驟 玻璃蝕刻 溶液濃度 玻璃布的凸出長度 (μιη) 導通孔側壁空隙長度 (μιη) 實例1 去塗抹之前 20 5 Λτττ m 實例2 去塗抹之前 35 3 實例3 去塗抹之前 50 2 4nr rTTr y\\s 比較實例1 flTf- Aver Mil "、、 10 ^TTC 撕 比較實例2 去塗抹之後 20 8 4nr 無 比較實例3 去塗抹之後 35 6 5 比較實例4 去塗抹之後 50 3 6 Ο 如同表1清楚可見般,在本發明的實例中,並未發現 通孔側壁上的空隙’以及’有效地蝕刻從通孔側壁凸出的 玻璃布。相反地’在比較實例中’當玻璃布的凸出藉蝕刻 來予以降低時’甚至通孔側壁中的玻璃布會被蝕刻而產生 空隙。如此’難以有效蝕刻。 <實例4 > 以無電銅電鍍的觸媒’處理實例3中去塗抹處理(粗 糙化處理)之後疊層及通孔的絕緣層的表面’以及’使其 -31 - 200942117 受到無電銅電鍍,接著,以硫酸銅電解電鍍,將通孔轉換 成經塡充之塞孔。 <實例5 > 將實例4中所取得的疊層的最外銅層(絕緣層上的銅 層)蝕刻以形成電路,因而取得4層印刷線路板。然後, 進一步在180 °C下實施退火處理30分鐘。所取得的導電 層之導電電鍍具有約30 μιη的厚度,以及,剝離強度爲 〇.8kgf/cm。根據日本工業標準(JIS) C648 1,評估剝離強 度。此外,在255 °C下烘烤15分鐘,所取得的多層印刷 配線板不會捲曲。 本申請案以在日本申請的專利申請號2007-3 03737爲 基礎,其內容於此一倂列入參考。 【圖式簡單說明】 圖1(a)-圖1(f)是本發明的多層印刷配線板之製造方 法的一個實施例的步驟之剖面視圖; 圖2(a)-圖2(c)是本發明的多層印刷配線板之製造方 法中形成含有塞孔的電路之步驟的剖面視圖; 圖3(a)及3(b)顯示本發明中「空隙長度」及「凸出長 度」的定義; 圖4(a)-圖4(e)是直到習知多層印刷配線板的製造步 驟中去塗抹處理之步驟的剖面視圖; 圖5(a)及(b)是習知多層印刷配線板的製造步驟中玻 200942117 璃蝕刻步驟及塞孔形成步驟的剖面視圖。 【主要元件符號說明】 1 :玻璃布 2 =熱固性樹脂成份 3 :預浸體For the high-density wiring of the multilayer printed wiring board, the top diameter of the through hole 5 is preferably not more than 75 μm, more preferably not more than 70 μm, and still more preferably not more than 67 μm. The method of the present invention proves to be particularly advantageous for the small diameter through hole 'glass cloth having a top diameter of not more than 75 μm protruding from the side wall surface of the through hole to become a more attractive problem'. After the via hole 5 is formed, the glass cloth 1 protruding from the wall surface of the through hole 5 of -20-200942117 is etched with a glass etching solution to eliminate the glass cloth 1 protruding from the wall surface of the through hole 5 (Fig. 1(e) ). As the glass etching solution, a conventional solution such as a hydrofluoric acid solution or a fluoroboric acid solution 'ammonium fluoride solution can be used. Examples of commercially available glass etching solutions include "Enplate MLB GLASS ETCH ADDITIVE" manufactured by Meltex Corporation and the like. Commercially available glass etching solutions are typically diluted prior to use. For example, when the glass etching solution is a fluoroboric acid solution, the concentration of fluoroboric acid is generally about 50 g/L, and the solution is diluted to 5 mL/L-200 mL with ion-exchanged water, distilled water, etc. before use. The range of L, preferably, is 10 mL/L to 100 mL/L. As an etching method, a method of immersing a laminate having a through hole in a solution, and a method of including a spray solution in a through hole, which is superior in permeability of the solution in the through hole. In order to suppress the protruding length of the glass cloth 1 after the smear treatment described below, it is preferable to use these solutions to perform etching of the glass cloth to etch from the side wall surface of the through hole to the surface of the through hole. The glass cloth inside the resin (insulating layer 4) can generally reach about 2 μm from the side wall surface of the through hole and inside the resin (insulating layer 4). Therefore, by using the uranium etching treatment of the glass etching solution, a void S having an opening can be formed on the side wall surface of the through hole 5 (see Fig. 1(e)). After the etching treatment of the glass cloth 1 using the above glass etching solution, the through holes 5 are subjected to a desmearing treatment (Fig. 1 (f)). With regard to this de-coating treatment, a method comprising immersing a laminate having the through holes 5 in an oxidizing agent solution, and a method of spraying the oxidizing agent solution into the through holes may be used. Examples of the oxidizing agent solution include concentrated sulfuric acid, chromic acid, or a mixed acid thereof, or an aqueous solution of an alkali metal manganate solution of 21 - 200942117 (sodium permanganate aqueous solution, potassium permanganate aqueous solution), etc., preferably An aqueous solution of an alkali metal manganate. These oxidizing agent solutions are commercially available chemicals for printing wiring boards, and these commercially available products can be used as they are. As the alkali metal permanganate salt solution, "Enplate MLB-4 97" manufactured by Meltex Co., Ltd., or the like can be used. By the smear treatment, the cured product (resin cured product) of the thermosetting resin component on the side wall of the through hole 5 is broken by the oxidizing agent, and the void formed by the etching treatment of the glass cloth can be eliminated. The above-described gap S having an opening on the side wall surface (see Fig. 1(e)). In order to surely eliminate the void S, it is necessary to sufficiently perform the thermal smearing treatment. Although the tip of the glass cloth is somewhat convex, the amount of protrusion can be small, and the protrusion formed during the laser processing (Fig. 1 (d)) for forming the through hole 5 (Fig. 1 (f)) is remarkable. The ground is small. In order to increase the flow of the plating solution in the through hole, the length of the glass cloth 1 protruding from the side wall of the through hole after the smear treatment is preferably not more than 6 μm, more preferably not more than 5 μm, still more preferably not more than 4 μm, And, further preferably, it is not more than 3 μm. In the desmear treatment using an aqueous solution of an alkali metal permanganate solution, it is preferred to use an expansion agent solution to carry out the expansion treatment before the treatment with the aqueous solution of the alkali metal permanganate solution, and to use an aqueous solution of an alkali metal permanganate solution. After the treatment, a reducing agent is preferably used to carry out a post treatment (neutralization treatment). The expander solution and the reducing agent solution are commercially available chemicals for printing the wiring board, and these commercially available products can be used as they are. Examples of the expander solution include "Melplate MLB-6001", "Melplate MLB-495", 200942117 "Melplate MLB-496" manufactured by Meltex, and the like, and examples of the reducing agent solution include those manufactured by Meltex Corporation. Enplate MLB-790M", and so on. The desmear treatment of the through holes using the oxidizing agent solution is also a roughening treatment of the surface of the insulating layer. In this case, in consideration of the formation of the ultra-precision wiring and the close adhesion strength of the wiring, the surface roughness of the insulating layer 4 after the roughening treatment is desirably not less than 表面.ίμιη and not more than 1.5 μm of the surface roughness Ra値. The surface roughness Ra値 is a number indicating the surface roughness, which is called arithmetic mean roughness. Specifically, the surface roughness Ra 取得 is obtained by measuring the distance of change in the measurement area as the absolute 値 of the height of the surface of the average line, and calculating the arithmetic mean 値. For example, using a WYKO NT3 3 00 manufactured by Veeco Instruments Co., Ltd., a V 接触 contact mode of a measurement range of a 50 Ω lens of 121 μηι χ 92 μm is obtained, and a number 値 is obtained, and the surface roughness Ra 値 is obtained from the obtained number. In the prior art document 2, the adhesion of a matrix resin which is melted by laser irradiation to a glass cloth, the inability of the fluoride to contact the glass cloth and the effective removal of the etching are pointed out. According to the study of the present inventors, these problems are not highlighted. This is considered to be the difference between the different curing states of the matrix resin resulting from the different treatments between the prior art document 2 and the present invention, since the method described in the prior art document 2 includes simultaneous heat curing in a batch The prepreg and the copper are simultaneously hot pressed to form the insulating layer and the conductive layer, but the process used in the embodiment of the present invention substantially comprises a two-step thermal curing process to form a conductive layer by electroplating, wherein the circuit is laminated on the circuit The prepreg on the substrate is thermally cured and annealed after the conductive layer is formed. In the present invention, the circuit substrate having the insulating layer can form a through hole (through hole) of -23-200942117 when necessary. The penetration holes can be formed by conventionally known methods, generally using mechanical drilling. Further, a method of chemically treating the surface of the copper foil and applying laser irradiation can also be used. In a multilayer printed wiring board, a through hole is usually formed in the core substrate. In the present invention, when an insulating layer such as the insulating layer 4 is accumulated, a via hole is usually obtained to obtain conduction. A method of manufacturing a multilayer printed wiring board according to the present invention, after forming a via hole in the insulating layer, further comprising: a glass etching process and a smearing process, a plating process of forming a conductive layer in the surface of the insulating layer by plasma, and After the formation of the conductive layer, the annealing process of the heated circuit substrate, and the formation of a circuit in the conductive layer. These steps can be carried out according to different methods well known to those skilled in the art and different methods for multilayer printed wiring boards. In the plating process for forming a conductive layer by electroplating, when the surface of the insulating layer is roughened, the adhesion of the conductive layer to the insulating layer can be enhanced by the fixing effect. As described above, therefore, in the de-smearing treatment after the etching treatment of the glass cloth, the insulating layer is preferably subjected to the simultaneous surface roughening treatment. In the plating process, plating is also formed in the via holes. The conductive layer is formed by electroplating using a combination of electroless plating and electrolytic plating. Alternatively, an electroplating ink having a pattern opposite to that of the conductive layer is formed, and the electroconductive layer is formed by electroless plating alone. The conductive layer is generally formed of copper, gold, silver, nickel, tin, or the like, and copper is preferred. The electrosurgical shovel layer preferably has a thickness of 1-3.1-3 μm, more preferably 33-2μηη', and the electrolytic plating layer has a thickness which is preferably from the thickness of the electroless ammonium layer to a total thickness of from 3 to 35 μm. More preferably 5-20μιη. Further, the via hole may be filled by a plug which is filled with plating after the formation of the layer 200942117. After the conductive layer is formed, for example, the circuit substrate (insulating layer and conductive layer) is heated at a temperature of about 15 〇 to 200 ° C for about 20 to 90 minutes to carry out an annealing treatment. The peeling strength of the conductive layer can be further enhanced and stabilized by the annealing treatment. Regarding the circuit forming step, for example, a reduction process, a semi-addition process, or the like can be used. In order to form a precision line, a semi-additive process is preferred, wherein the pattern anti-plating ink is applied to the electroless plating layer to form an electrolytic electric ore layer (pattern plating layer) having a desired thickness, and the pattern is resistant to electroplating ink. Separation, and the circuit is produced by rapid etching to remove the electroless plating. Figures 2(a) through 2(c) show an embodiment of a series of steps from conductive layer to circuit formation. A seed layer (conductive layer) 6 is formed on the surface of the insulating layer 4 and inside the via hole 5 by electrolytic plating (Fig. 2 (a)), and the pattern anti-electrostatic ink 7 is applied to the seed layer 6 to An electrolytic plating layer (pattern electrode layer) 8 is formed which completely fills the 0 hole, and then the pattern plating resist 7 is separated and the electroless ore layer 8 is removed by rapid starvation, thereby forming a plug hole 9 Circuit (Figure 2(c)). As described above, according to the method of the present invention, the length of the glass cloth 1 protruding from the wall surface of the through hole 5 formed in the insulating layer 4 containing the glass cloth 1 is sufficiently small' and the etch back phenomenon can be suppressed. Therefore, a highly reliable plug hole 9 can be surely formed. That is, it is possible to obtain a multilayer printed wiring board having a circuit including the plug hole 9 in which the insulating layer 4' containing the glass cloth 1 is formed by lamination from the side of the through hole 5 formed in the insulating layer 4 - 25- 200942117 The wall protrudes by a length of 6 μm or less, and the convex portion of the glass cloth 1 is embedded in the conductive layer (the seed layer 6 and the electrolytic plating layer 8) which forms the plug hole 9. The circuit board used for the manufacture of the multilayer printed wiring board of the present invention mainly means a glass epoxy substrate, a metal substrate, a polyester substrate, a polyimide substrate, a resin substrate, a thermosetting polyphenylene ether substrate, or the like, wherein One or both of the surfaces have a patterned conductive layer (circuit). The circuit substrate in the present invention also covers the inner layer circuit substrate of the intermediate product, and on the inner layer circuit substrate, an insulating layer and/or a conductive layer for the production of the multilayer printed wiring board will be formed. Since the adhesion between the insulating layer and the circuit board can be obtained, the surface of the conductive circuit layer is preferably pre-roughened by blackening or the like. In the following, the invention will be described in detail with reference to the embodiments and comparative examples. In the following, "parts" means "parts by mass". <Production of Prepreg> Liquid bisphenol quinone type epoxy resin (epoxy equivalent weight 180, "Epikote 828EL" manufactured by Japan Epoxy Resins Co., Ltd., 28 parts) and naphthalene type tetrafunctional epoxy resin (ring) "HP4700" manufactured by Dainippon Ink and Chemicals Co., Ltd., 28 parts) is dissolved in a mixed solution of methyl ethyl ketone (hereinafter abbreviated as "MEK", 15 parts) and cyclohexanone (15 parts). And stir and heat at the same time. A naphthol-based curing agent ("SN-485" manufactured by Tohto Kasei Co., Ltd., phenolic hydroxyl equivalent 200942117 215) and a curing catalyst (by SHIKOKU CHEMICALS Co., Ltd.) having a solid content of 50% was added to the mixed solution. "2E4MZ", 0.1 parts), spherical cerium oxide (average particle size 〇.5μιη, "SO-C2" manufactured by Admatechs, 70 parts), and polyvinyl butyral resin solution (by SEKISUI CHEMICAL) Manufactured "KS-1" solution, a solution of ethanol and toluene mixed in a ratio of 1:1 (mass ratio), having a solid content of 15% by mass, 30 parts), and rotating the mixer at a high speed to homogenize the mixture Disperse to produce a resin varnish. A 10 7 7MS glass cloth (thickness 19 μm) manufactured by Asahi-Schwebel Co., Ltd. was impregnated with the resin varnish, and dried at 80 to 120 ° C to produce a prepreg having a thickness of 50 μm. A poly(ethylene terephthalate) film (thickness 38 μm, hereinafter abbreviated as "PET film") is superposed thereon from one side and a polypropylene film (protective film) having a thickness of 15 μm from the opposite side, and , the laminate is wound into a roll. Then, this roll was cut into strips at a width of 502 mm to produce two rolls of 50 m wound prepreg (the composition ratio (mass ratio) of the glass cloth to the resin component was 1:5). <Example 1 > After the circuit formation (circuit conductor thickness 18 μm), a protective film separation prepreg having a PET film was laminated on both sides of a copper-clad laminate (circuit substrate) having a thickness of 22 mm . The PET film was separated, and the laminate was thermally cured to form an insulating layer having a thickness of 32 μm on one surface of the above circuit substrate. Then, through a carbon dioxide gas laser, a through hole having a top diameter of 60 μm and a bottom diameter of 50 μm was formed in an insulating layer laminated on a surface of the circuit substrate. -27- 200942117 The circuit substrate is immersed in 4 (TC aqueous solution for 5 minutes, uranium engraved glass cloth, the aqueous solution is diluted with ion exchange water to a concentration of about 50g / L of fluoroboric acid glass etching solution ("Enplate MLB GLASS ETCH ADDITIVE" manufactured by Meltex Corporation) was obtained at a concentration of 20 mL/L. Then, the through hole was subjected to a smear treatment. The smear treatment was also used as a roughening treatment of the surface of the insulating layer. And immersed in "Melplate MLB-600 1" manufactured by Meltex Co., Ltd. at 60 ° C for 5 minutes, and immersed in "Enplate MLB-479" manufactured by Meltex Corporation at 80 ° C for 20 minutes, and It was immersed in "Enplate MLB-790" manufactured by Meltex Co., Ltd. at 40 ° C for 5 minutes. "Melplate MLB-6001" was used as a swelling agent solution, and "Enplate MLB-479" was a solution of an aqueous solution of an alkali metal permanganate solution. As an oxidizing agent solution, "Enplate MLB-790" was used as a reducing agent solution. After the glass etching treatment and the smearing treatment (roughening treatment), the model "SU-150" manufactured by Hitachi High-Technologies Co., Ltd. Scanning electron microscope (SEM) of 0", observing the cross section of the through hole in the circuit substrate, and measuring the length of the gap in the side wall of the through hole (that is, on the side wall surface of the through hole shown in Fig. 1(e) The length of the slit S having an opening) and the protruding length of the glass cloth. In the through hole formed at the intersection of the fiber bundle having a high glass cloth density in the circuit substrate, measurement is performed, and the longest SEM photograph is obtained. The gap length and the longest bulging length are taken as representative 値. As shown in Fig. 3(a), the "void length" on the SEM photograph is defined as the position where the test point X and the gap S are farthest from the side wall 5 a. The linear distance between the horizontal direction (i.e., the direction parallel to the upper surface 4a of the insulating layer 4), the reference point X is the approximate center of the opening of the gap S in the side wall 5a in the through hole 5. (b), the "bump length" on the SEM photograph is defined as a linear distance between the reference point X and the tip end of the glass cloth in the horizontal direction (i.e., the direction parallel to the upper surface 4a of the insulating layer 4). B, the reference point X is a glass cloth 1 protruding from the side wall 5a in the through hole 5 Approximate center of the root of the protruding portion. After the glass etching process, part of the circuit substrate is separated. The length of the gap in the through hole of the separated circuit substrate is measured, the remaining circuit substrate is subjected to de-smearing treatment, and measurement The protruding length of the glass cloth in the via holes of the remaining circuit substrates. Further, the surface roughness of the insulating layer was measured in the following manner to find Ra (arithmetic mean roughness) = 800 run. <Measurement of Surface Roughness of Insulating Layer> Using a non-contact type roughness meter (WYKO NT33 00 manufactured by Veeco Instruments Co., Ltd.), the measurement range of a 50 χ lens of 121 μm χ 92 μιη 'in the VSI contact mode, the insulating layer was determined. The Ra of the surface (arithmetic mean roughness). <Example 2 > In addition to diluting a glass etching solution ("Enplate MLB GL AS S ETCH ADDITIVE" manufactured by Meltex Corporation) to a concentration of -29-200942117 3 5 mL/L with ion-exchanged water to obtain an aqueous solution The operation and measurement were carried out in the same manner as in Example 1. The surface of the insulating layer has an Ra (calculus average roughness) of 800 nm. <Example 3 > In addition to diluting a Boma etching solution ("Enplate MLB GL AS S ETCH ADDITIVE" manufactured by Meltex Co., Ltd.) to a concentration of 5 OmL/L with ion-exchanged water to obtain an aqueous solution, In the manner of Example 1, the operation and measurement were carried out. The surface of the insulating layer has Ra (arithmetic average roughness). <Comparative Example 1 > Operations and measurement were carried out in the same manner as in Example 1 except that the glass etching was omitted. <Comparative Example 2 > Operations and measurement were carried out in the same manner as in Example 1 except that the glass uranium engraving was carried out after the roughening treatment (also as a smear treatment) of the surface of the insulating layer. <Comparative Example 3 > Operations and measurement were carried out in the same manner as in Example 2 except that the glass etching was performed after the roughening treatment (also as a de-coating treatment) of the surface of the insulating layer. -30- 200942117 <Comparative Example 4> The operation and measurement were carried out in the same manner as in Example 1 except that the glass etching was performed after the roughening treatment (also as a smear treatment) of the surface of the insulating layer. The results of Examples 1-3 and Comparative Examples 1-4 are shown in Table 1. <Table 1 > Glass etching step Glass etching solution concentration Glass cloth protrusion length (μιη) Via hole side wall gap length (μιη) Example 1 Before applying smear 20 5 Λτττ m Example 2 Before smearing 35 3 Example 3 Desmear Before 50 2 4nr rTTr y\\s Comparative example 1 flTf- Aver Mil ",, 10 ^TTC tear comparison example 2 after application 20 8 4nr no comparison example 3 after application 35 6 5 comparison example 4 after application 50 3 6 Ο As is clearly seen in Table 1, in the example of the present invention, the voids on the sidewalls of the vias and the glass cloth protruding from the sidewalls of the vias were not effectively etched. Conversely, in the comparative example, when the convexity of the glass cloth is lowered by etching, even the glass cloth in the side wall of the through hole is etched to generate a void. So, it is difficult to effectively etch. <Example 4 > The surface of the insulating layer of the laminate and the via hole after the smear treatment (roughening treatment) in the electroless copper plating catalyst treatment Example 3 and 'there was -31 - 200942117 subjected to electroless copper plating Then, electrolytic plating is performed with copper sulfate to convert the through holes into the filled plug holes. <Example 5> The outermost copper layer (the copper layer on the insulating layer) of the laminate obtained in Example 4 was etched to form an electric circuit, thereby obtaining a 4-layer printed wiring board. Then, annealing treatment was further carried out at 180 ° C for 30 minutes. The conductive plating of the obtained conductive layer had a thickness of about 30 μm, and the peel strength was 〇8 kgf/cm. Peel strength was evaluated according to Japanese Industrial Standard (JIS) C648 1. Further, baking at 255 ° C for 15 minutes did not cause the multilayer printed wiring board to be curled. The present application is based on Japanese Patent Application No. 2007-3 03737, the disclosure of which is incorporated herein by reference. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1(a) to Fig. 1(f) are cross-sectional views showing the steps of an embodiment of a method of manufacturing a multilayer printed wiring board of the present invention; Fig. 2(a) - Fig. 2(c) are A cross-sectional view showing a step of forming a circuit including a plug hole in the method of manufacturing a multilayer printed wiring board of the present invention; and FIGS. 3(a) and 3(b) are views showing definitions of "void length" and "bulk length" in the present invention; 4(a) to 4(e) are cross-sectional views showing steps of a smear process in a manufacturing step of a conventional multilayer printed wiring board; and Figs. 5(a) and (b) are manufacturing of a conventional multilayer printed wiring board. Step in the glass 200942117 glass etching step and cross-sectional view of the plug forming step. [Main component symbol description] 1 : Glass cloth 2 = Thermosetting resin component 3 : Prepreg

4 :絕緣層 4a :上表面 5 :通孔 5 a :側壁 6 :種子層 7:圖案抗電鍍油墨 8 :電解電鍍層 9 :塞孔 1 0 :電路基板 1 1 :導電電路層 2 0 :塞孔 21 :導電膜 -33-4: insulating layer 4a: upper surface 5: through hole 5a: side wall 6: seed layer 7: pattern anti-electroplating ink 8: electrolytic plating layer 9: plug hole 1 0: circuit substrate 1 1 : conductive circuit layer 2 0 : plug Hole 21: Conductive film -33-

Claims (1)

200942117 十、申請專利範圍 1. 一種多層印刷配線板之製造方法,包括:藉由雷 射照射以在由預浸體所形成的絕緣層中形成通孔,以及, 使該通孔受到以玻璃鈾刻溶液之玻璃蝕刻處理,而後受到 以去氧化劑溶液的去塗抹處理,該預浸體包括經過熱固性 樹脂成分浸漬的玻璃布。 2. 如申請專利範圍第1項的方法,其中,該通孔具 有不大於75 μιη的頂部直徑。 3. 如申請專利範圍第1或2項的方法,其中,將該 預浸體層疊於該電路基板的至少一表面上、在降壓下加熱 及壓製該叠層、以及熱固化該預浸體,以形成該絕緣層。 4. 如申請專利範圍第1或2項的方法,其中,該氧 化劑溶液是過錳酸鹼金屬鹽溶液。 5. 如申請專利範圍第1或2項的方法,其中,使用 該氧化劑溶液的該通孔去塗抹處理係與使用該氧化劑溶液 的絕緣層表面粗糙化處理同時實施。 6. 如申請專利範圍第5項的方法,又包括電鍍程 序,用以藉由電鍍而在該絕緣層的粗糙化表面上形成導電 層。 7 .如申請專利範圍第6項的方法,又包括退火處理 步驟,用以在形成該導電層之後,將該絕緣層及該導電層 退火。 8.如申請專利範圍第7項的方法,又包括電路形成 步驟,用以在該導電層上形成電路。 -34- 200942117 9 · 一種多層印刷配線板,包括: 絕緣層,係藉由包括經過熱固性樹脂成分浸漬的玻璃 布之預浸體所形成, 通孔,係形成於該絕緣層上, 電路,含有在該導通孔中由導電層所形成的塞孔,及 玻璃布,從該導通孔的側壁突出不大於6μηι的長 度, ^ 其中,該玻璃布的凸出部份係嵌入於形成該塞孔的該 導電層中。 10.如申請專利範圍第9項的多層印刷配線板’其 中,該絕緣層係藉由積層法來予以形成。 1 1 .如申請專利範圍第9或1 〇項的多層印刷配線 板,其中,使該絕緣層的表面粗糙化而具有0.1-1.5μιη範 圍內的算術平均粗糙度(Ra)。 ❹ -35-200942117 X. Patent application scope 1. A method for manufacturing a multilayer printed wiring board, comprising: forming a through hole in an insulating layer formed by a prepreg by laser irradiation, and subjecting the through hole to glass uranium The solution is etched by a glass and then subjected to a smear treatment with a deoxidizing solution comprising a glass cloth impregnated with a thermosetting resin component. 2. The method of claim 1, wherein the through hole has a top diameter of no more than 75 μm. 3. The method of claim 1 or 2, wherein the prepreg is laminated on at least one surface of the circuit substrate, the laminate is heated and pressed under reduced pressure, and the prepreg is thermally cured. To form the insulating layer. 4. The method of claim 1 or 2, wherein the oxidant solution is an alkali metal permanganate solution. 5. The method of claim 1 or 2, wherein the through-hole smear treatment using the oxidizing agent solution is performed simultaneously with the surface roughening treatment of the insulating layer using the oxidizing agent solution. 6. The method of claim 5, further comprising a plating process for forming a conductive layer on the roughened surface of the insulating layer by electroplating. 7. The method of claim 6, further comprising an annealing step of annealing the insulating layer and the conductive layer after forming the conductive layer. 8. The method of claim 7, further comprising a circuit forming step of forming a circuit on the conductive layer. -34- 200942117 9 · A multilayer printed wiring board comprising: an insulating layer formed by a prepreg comprising a glass cloth impregnated with a thermosetting resin component, and a via hole formed on the insulating layer, the circuit containing a plug hole formed by the conductive layer in the via hole, and a glass cloth protruding from a sidewall of the via hole by a length not greater than 6 μm, wherein the protruding portion of the glass cloth is embedded in the plug hole. In the conductive layer. 10. The multilayer printed wiring board of claim 9 wherein the insulating layer is formed by a lamination method. The multilayer printed wiring board of claim 9 or claim 1, wherein the surface of the insulating layer is roughened to have an arithmetic mean roughness (Ra) in a range of 0.1 to 1.5 μm. ❹ -35-
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Cited By (2)

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Families Citing this family (37)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
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JP2015023251A (en) * 2013-07-23 2015-02-02 ソニー株式会社 Multilayer wiring board and manufacturing method therefor, and semiconductor product
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JP5905150B1 (en) * 2015-08-28 2016-04-20 ユニチカ株式会社 Glass cloth
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US10410883B2 (en) 2016-06-01 2019-09-10 Corning Incorporated Articles and methods of forming vias in substrates
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US11078112B2 (en) 2017-05-25 2021-08-03 Corning Incorporated Silica-containing substrates with vias having an axially variable sidewall taper and methods for forming the same
US11554984B2 (en) 2018-02-22 2023-01-17 Corning Incorporated Alkali-free borosilicate glasses with low post-HF etch roughness
CN108617102A (en) * 2018-04-10 2018-10-02 华中科技大学 A kind of production method of ceramic circuit board
EP3691421A1 (en) * 2019-01-29 2020-08-05 AT & S Austria Technologie & Systemtechnik Aktiengesellschaft Component carrier with embedded filament
CN110831350A (en) * 2019-11-14 2020-02-21 四会富仕电子科技股份有限公司 Method for manufacturing bottomless copper circuit board
CN111333342A (en) * 2020-02-18 2020-06-26 清远南玻节能新材料有限公司 Preparation method of three-dimensional pattern in glass hole
TWI768761B (en) * 2021-03-11 2022-06-21 萬億股份有限公司 Method for optimizing hole filling and making fine lines on printed circuit boards
KR102518456B1 (en) * 2022-10-11 2023-04-06 주식회사 중우나라 Method of manufacturing glass panel

Family Cites Families (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5017742A (en) * 1988-09-15 1991-05-21 Shipley Company Inc. Printed circuit board
JPH05153496A (en) * 1991-11-29 1993-06-18 Hitachi Medical Corp X-ray image pickup device, x-ray perspective device and x-ray television camera device used for them
JPH06314869A (en) * 1993-04-30 1994-11-08 Eastern:Kk Method of forming through hole on printed wiring board
US5527741A (en) * 1994-10-11 1996-06-18 Martin Marietta Corporation Fabrication and structures of circuit modules with flexible interconnect layers
TW323432B (en) * 1995-04-28 1997-12-21 Victor Company Of Japan
US5906042A (en) * 1995-10-04 1999-05-25 Prolinx Labs Corporation Method and structure to interconnect traces of two conductive layers in a printed circuit board
JP3766125B2 (en) 1995-10-16 2006-04-12 イビデン株式会社 Multilayer printed wiring board and manufacturing method thereof
KR20080017496A (en) * 1998-02-26 2008-02-26 이비덴 가부시키가이샤 Multilayer printed wiring board having filled-via structure
MY144573A (en) * 1998-09-14 2011-10-14 Ibiden Co Ltd Printed circuit board and method for its production
US6054761A (en) * 1998-12-01 2000-04-25 Fujitsu Limited Multi-layer circuit substrates and electrical assemblies having conductive composition connectors
JP4509247B2 (en) 1999-04-30 2010-07-21 東レ・ダウコーニング株式会社 Silicone-containing polyimide resin, silicone-containing polyamic acid and method for producing them
JP2001113527A (en) * 1999-10-15 2001-04-24 Risho Kogyo Co Ltd Thermosetting resin-impregnated prepreg and method for manufacturing the same
JP2002012667A (en) 2000-06-29 2002-01-15 Shin Etsu Chem Co Ltd Polyimidesilicone resin, solution composition thereof, and polyimidesilicone resin coating film
SG102588A1 (en) * 2000-08-03 2004-03-26 Inst Materials Research & Eng A process for modifying chip assembly substrates
JP4519297B2 (en) 2000-09-21 2010-08-04 イビデン株式会社 Via hole formation method
JP3399434B2 (en) * 2001-03-02 2003-04-21 オムロン株式会社 Method for forming plating of polymer molding material, circuit forming part, and method for manufacturing this circuit forming part
JP2002314254A (en) * 2001-04-11 2002-10-25 Toppan Printing Co Ltd Multilayer printed wiring board and its manufacturing method
JP2003124632A (en) 2001-10-16 2003-04-25 Nec Toppan Circuit Solutions Inc Multilayer printed wiring board and its manufacturing method
JP3941573B2 (en) * 2002-04-24 2007-07-04 宇部興産株式会社 Method for manufacturing flexible double-sided substrate
JP4054269B2 (en) 2003-03-20 2008-02-27 Tdk株式会社 Electronic component manufacturing method and electronic component
KR101131759B1 (en) * 2003-04-07 2012-04-06 이비덴 가부시키가이샤 Multilayer printed wiring board
JP3948624B2 (en) * 2003-09-11 2007-07-25 株式会社メイコー Multilayer circuit board manufacturing method
EP1713314A4 (en) * 2004-02-04 2010-06-02 Ibiden Co Ltd Multilayer printed wiring board
JP2005347424A (en) * 2004-06-01 2005-12-15 Fuji Photo Film Co Ltd Multi-layer printed wiring board and manufacturing method thereof
JP4929623B2 (en) 2004-06-21 2012-05-09 味の素株式会社 Thermosetting resin composition containing modified polyimide resin
US7359213B2 (en) * 2004-07-09 2008-04-15 The Agency For Science, Technology And Research Circuit board
JP4492242B2 (en) * 2004-07-29 2010-06-30 日産自動車株式会社 Semiconductor package
JPWO2006028098A1 (en) * 2004-09-10 2008-05-08 松下電器産業株式会社 Wiring board
TW200628536A (en) * 2004-11-30 2006-08-16 Ajinomoto Kk Curable resin composition
CA2589485A1 (en) * 2004-12-07 2006-06-15 Ronald W. Whittaker Miniature circuitry and inductive components and methods for manufacturing same
US7737368B2 (en) * 2005-09-30 2010-06-15 Sanyo Electric Co., Ltd. Circuit board and method of manufacturing circuit board
JP2007115840A (en) 2005-10-19 2007-05-10 Kyocera Corp Wiring board and manufacturing method thereof
JP4992396B2 (en) 2005-11-29 2012-08-08 味の素株式会社 Resin composition for interlayer insulation layer of multilayer printed wiring board
US20070295607A1 (en) 2005-11-29 2007-12-27 Ajinomoto Co. Inc Resin composition for interlayer insulating layer of multi-layer printed wiring board
JP5284146B2 (en) * 2008-03-13 2013-09-11 日本特殊陶業株式会社 Multilayer wiring board and manufacturing method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI506082B (en) * 2009-11-26 2015-11-01 Ajinomoto Kk Epoxy resin composition
TWI405516B (en) * 2011-04-27 2013-08-11 Unimicron Technology Corp Circuit board and manufacturing method thereof

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