TW200941599A - Method for fabricating a stack-type IC chip package - Google Patents
Method for fabricating a stack-type IC chip package Download PDFInfo
- Publication number
- TW200941599A TW200941599A TW097109546A TW97109546A TW200941599A TW 200941599 A TW200941599 A TW 200941599A TW 097109546 A TW097109546 A TW 097109546A TW 97109546 A TW97109546 A TW 97109546A TW 200941599 A TW200941599 A TW 200941599A
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- Taiwan
- Prior art keywords
- wafer
- bonding
- adhesive
- chips
- stack
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- H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
Description
200941599 九、發明說明: 【發明所屬之技術領域】 特別是指一種堆疊式 本發明係與晶片封裝製法有關 晶片封裝製法。 5【先前技術】 習有晶片進行封裳時,前置作業係先將晶圓切割成複 〇 ^個小片的晶片(die),而再依照不同的需求將晶片取下黏 著於合適的基板,並為㈣的電性連結及封膠作業。 一般堆疊式晶片封裝製作方式係先於基板上黏著第一 層之晶片,然後於第-層之晶片打上金屬導線,以使第一 層晶片與基板電性連結,接著再將第一層晶片頂部塗上接 合,,用以黏著欲堆疊於第二層之晶片,惟,由於第一層 之晶片上已設有導線,所以此時於上接合膠時必須十分小 心,以免汙染第一層晶片之導線焊墊,另外堆疊第二層晶 ❹is #時通常需要預留m置以避開第—層晶片之導線, 因此通常第二層晶片尺寸會較小於第一層晶片尺寸,而此 即為堆疊式晶片的製作上設下很大的限制,所以製備堆疊 式晶片之過程不僅限制過多,且第二層以上之上膠、黏著 之步驟亦十分繁複,此為其仍須改善之處。 【發明内容】 本發明之主要目的在於提供一種堆疊式晶片封裝製 法,其可以簡便晶片於堆疊時之流程,且可節省製作過程 4 20 200941599 5 ίο 15 緣是’為了達成前述目的,依據本發明所提供之—種 堆疊式晶片封裝製法,其步驟包含有:⑷提供一晶圓, 該晶圓具有-第-表面以及—第二表面’該第一表面上形 成有若干切割道,於該第二表面預定位置上塗佈一預定厚 ,接合膠’·⑴將該接合膠對應於伊謂道的位置,依預 =寬度進V曝光顯影去除,且使去除之寬度大於切割道之 度’(C)將該晶圓沿該切割道切割成複數晶片,該各晶 ^表面結合有-接合膠;(d)將步驟⑷^成之晶片以宜 接合膠面結合於-下層晶片上,而完成堆疊作業。^ 此,本發明透過上述之步驟流程,可使每—切割後 ,該阳片之第二表面黏合一接合膠,該接合膠具有一預定 f度且寬度小於切割後之該晶片,因此恰好可提供一 疊於下-層晶片之導線,方便晶片堆疊時之動作, 且可郎省製作過程中之成本。 【實施方式】 一為了詳細說明本發明之特徵及功效所在,茲舉以下之 較佳實施例並配合圖式說明如后,其中: 第一圖為本發明一較佳實施例之動作流程圖。 第二圖為本發明一較佳實施例之加工示意圖。 請參閱第-圖以及第二圖⑷至第二圖⑹其係 日^-較佳實關賴供之—獅疊式W封㈣法,其中 包含下列各步驟·· 、 (a)提供一晶圓U,該晶圓丨丨具有一第一表面以以 20 200941599 及一第二表面13,該第一表面丨丨上形成有若干切割道14, 於該第二表面13預定位置上塗佈接合膠15,使該接合膠 15具有一預定厚度,其中,塗佈的方式可為離心塗佈; (b)將該接合膠15對應於該切割道14的位置,依預 足見度進行曝光顯影去除,且去除之寬度大於切割道14之 寬度; 〇 (c)將該晶圓11沿該切割道14切割成若干晶片16, 且各該晶片16表面皆結合有一接合膠15,以形成堆疊晶片 10,其中該接合膠15可為C-stage接合膠,亦即為加壓加 10 熱型結合膠; (d)將步驟(c)完成之堆疊晶片1〇以其接合膠15 面堆疊於一下層晶片21上,而完成堆疊作業。 再請參閱第二圖(G)所示,本發明第一較佳實施例所提 供之一種堆疊式晶片封裝製法的實施狀態示意圖,堆疊晶 ^ 15片1〇,可直接堆疊於一晶片單元20上,該晶片單元20具 =一基板22、一下層晶片21、一導線23,下層晶片21黏 合於基板22上,並自該下層晶片21上將導線23打在該基 板22上,然後將堆疊晶片10置放於下層晶片21上,再加 壓加熱使接合膠Η黏合於下層晶片21上,而該接合膠14 2〇所提供之厚度,恰可避開下層晶片21上的導線23,俟該堆 疊晶片10黏著至下層晶片21後,再以導線18將該堆疊晶 片10與基板22做電性連結。 本發明創作重點在於晶片底面先製成一層預定厚度之 接合膠’再以加壓加熱方式將堆疊晶片(10)黏著於下層晶片 200941599 上 :至於本發明所_之堆疊晶片封裝製法,其晶片堆義 成;作Γ是三層以上也可利用本發明快‘ μ 1上可知,本發3㈣可達成之功效在於:^便堆疊曰 .5 時之轉及㈣打線空間,因此可節省製作過: 之成本。 © 本發明之上述各構件僅係用來說明,並非用以限制本 利範圍,其他之等效構件替換’亦應為本案之 200941599 【圖式簡單說明】 第一圖為本發明一較佳實施例之動作流程圖; 第二圖(A)係本發明一較佳實施例之加工示意圖 第二圖(B)係本發明一較佳實施例之加工示意圖 5 第二圖(C)係本發明一較佳實施例之加工示意圖 以及 第二圖(D)係本發明一較佳實施例之加工示意圖 第二圖(E)係本發明一較佳實施例之加工示意圖 第二圖(F)係本發明一較佳實施例之加工示意圖 第二圖(G)係本發明一較佳實施例之加工示意圖 10 【主要元件符號說明】 堆璧晶片1 〇 第二表面13 晶片16 下層晶片21 晶圓11 第一表面12 切割道14 接合膠15
導線18 晶片單元20 基板22 導線23 8
Claims (1)
- 200941599 十、申請專利範圍: \一種Γ疊式晶片封裝製法,其步驟包含有: (a) &供一晶圓,曰 表面,該m 第—表面以及一第 弟表面上形成有若干切割道,該第二 ^置上塗佈-狀厚度接合膠, 表面預定 該接合膠可被曝光顯影去10 進行該接合膠對應於該切财的位置,依預定寬度 '义顒影去除; 片表】1)將該晶圓沿該切割道切割成若干晶片,且各該晶 白結么古一社人滿· 柃 法法 結合有一接合膠; (d)將步驟(C)完成之各該晶片以其接合膠面結合 下層晶片上’而完成晶片堆疊作業。 ’便據申請專利範圍第1項所述之堆疊式晶片封裝製 其中:該步驟(b)中去除之寬度大於該切割道之寬度。 ’俊據申請專利範圍第1項所述之堆疊式晶片封裝製 其中:該接合膠係為c-stage接合膠。 法4·俊據申請專利範圍第1項所述之堆疊式晶片封裝製 其中:該步驟(a)中之接合膠塗佈的係採用離心塗佈 9
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TW097109546A TW200941599A (en) | 2008-03-18 | 2008-03-18 | Method for fabricating a stack-type IC chip package |
JP2008103015A JP2009224743A (ja) | 2008-03-18 | 2008-04-11 | 積層式チップパッケージの製造方法 |
US12/264,653 US20090239339A1 (en) | 2008-03-18 | 2008-11-04 | Method of stacking dies for die stack package |
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2008
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- 2008-04-11 JP JP2008103015A patent/JP2009224743A/ja active Pending
- 2008-11-04 US US12/264,653 patent/US20090239339A1/en not_active Abandoned
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