TW200933821A - Fin-JFET - Google Patents
Fin-JFET Download PDFInfo
- Publication number
- TW200933821A TW200933821A TW097143260A TW97143260A TW200933821A TW 200933821 A TW200933821 A TW 200933821A TW 097143260 A TW097143260 A TW 097143260A TW 97143260 A TW97143260 A TW 97143260A TW 200933821 A TW200933821 A TW 200933821A
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- Prior art keywords
- fin
- forming
- jfet
- gate
- mosfet
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Classifications
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- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Description
200933821 九、發明說明: 【先前技術】 達成半導體產業中的奈米級整合之持續挑戰為藉由縮小 裝置佔據面積來將不斷増加的數目個裝置(例如’電晶髏) 製造至不斷減小的區域中,同時保持高產率及可靠性。已 • 冑由在管理相關聯短通道效應(例如,歸因於閘極與源極/ 汲極擴散區域之間的電荷共用的臨限電壓(vt)之減小)的同 時按比例縮小電晶想通道長度而主要針對數位應用達成此 〇 挑戰。此已產生厚度減小的閘極絕緣體(例如,氧化物 層)、增加的通道摻雜濃度及各種三維結構建構技術之使 用。 在先前方法中,已在水平面中製造電晶體。一種解決上 述奈米級挑戰之先前方法為在垂直平面上建構電晶體,實 質上’將電晶體定向在邊緣上以減少每一電晶體在水平面 中所需的地盤,例如,在薄的垂直半導體層(例如,以薄 的壁狀形式提供之矽(Si) ’例如具有一薄絕緣層之鰭)上形 ® 成場效電晶體(FET)。多個閘極可由獨立式垂直定向之鰭 形成,例如’兩側中之每一者上有一個閘極,其中該等閘 極經電連接以協同調整閘極間的通道。將形成於此等鰭狀 結構上之FET稱為鰭式FET或多閘極FET結構(MuGFET)。 金氧半導體(MOS)場效電晶體(亦即,MOSFET)及接面 場效電晶體(亦即,JFET)之基本組態係熟知的。MOSFET 閘極藉由施加電壓至閘極來控制電流,從而引起半導體之 表面中之場效應,且引起閘極下的晶圓表面中之電荷之聚 135783.doc 200933821 集或耗盡,此視閘極下的晶圓中之摻雜導電類型及閘極電 壓之極性而定。電荷之此聚集或耗盡在閘極下形成一導電 通道,其將一源極區域連接至一汲極區域。11通道1^1〇8電 晶體(亦即,NMOS)具有形成於p型晶圓中之n型源極區域 及汲極區域》當施加一正的閘極-源極電壓vgs時藉由耗 盡通道區域之電洞及將電子吸引至表面,在p型區域之表 面上(恰好在絕緣層下)形成η通道。相反地,p通道M〇s電 晶體(亦即’ PMOS)具有形成於n型主體中之p型源極區域 及汲極區域。當施加一負的閘極-源極電壓(例如,Vgs) 時’藉由耗盡通道區域之電子及將電洞吸引至表面,在n 型通道區域之表面上形成p通道。 JFET組態具有一形成於閘極導艘下之接面。同mqsfet 之情況相同’可形成具有η通道之JFET(亦即,nJFET)或且 有P通道之JFET(亦即’ pJFET)。此外,可將jfet製造為像 耗盡型裝置(在零閘極電壓下常開且傳導,藉由在閘極上 施加一具有在大約1.2伏特至1.8伏特範圍内之量值的反向 偏壓(對nJFET為正且對pJFET為負)而斷開),或一增強型 裝置(在零閘極電壓下常關,藉由在閘極上施加一小的正 向偏壓(對nJFET為正且對pJFET為負)而接通)。 藉由充當閘極之接面(而非絕緣閘極)來施加場。在(例 如)nJFET之操作期間’電流在閘極下的經播雜碎區中自源 極流至汲極。隨著nJFET閘極電壓增加,一耗盡電荷之區 域(耗盡區域)展開,從而夾斷傳導路徑。歸因於缺少可用 的行動電荷,耗盡區域像絕緣體一樣動作,且因此該區域 135783.doc 200933821 隨著其寬度增加而具有夾斷(亦即’限制)電流之效應° nJFET可與增強型MOSFET相反地操作。在增強型 nMOSFET中,增加閘極電壓使通過通道之電流增加。然 而,在nJFET中,增加閘極電壓使通過通道之電流減小。 互補MOS邏輯(亦即,CMOS)使用P通道MOSFET及η通道 MOSFET作為構建塊。在反相器中’藉由將閘極與汲極連 接在一起而使每一 η型MOSFET(亦即,nMOSFET)與一 p型 MOSFET(亦即,pMOSFET)互補。閘極上之高電壓將使 nMOSFET傳導且使pMOSFET不傳導。閘極上之低電壓引 起相反傳導性。MOSFET主要用於數位、記憶體及類比電 路應用中。然而,已知JFET能更好地滿足具有高信雜比、 低參數不匹配、線性及低閃爍雜訊之類比組件需要的類比 要求。 鰭式MOSFET至今之發展針對低電壓數位及記憶體應用 強調了效能及密度β詳言之,已將焦點放在減少短通道效 應、亞臨限斜率(與減小的臨限電壓及不能完全斷開電晶 體相關聯)及給定通道寬度之有效面積。已在形成鰭式 MOSFET之先前方法中舉例說明了若干非平面結構。最 初,在矽溝槽側壁上形成MOSFET頻道。其後,使用一方 向性蝕刻技術建構一"圍繞閘極"式垂直MOSFET以形成一 矽柱,該柱為介電質所圍繞且具有一在柱之頂部上源極、 在底部上之汲極及兩者之間的閘極。在另一先前方法中, 使用一絕緣體上矽(SOI)組態舉例說明一橫向鰭式 MOSFET,藉此SOI係藉由單晶矽柱下之橫向氧化而形 135783.doc 200933821 成,從而使該枉與支撐晶圓分離’並且沿著鰭形成源極、 通道及汲極。已製造出具有變化之效能及複雜性程度的鰭 式MOSFET結構之其他變體。 【實施方式】 提供用於整合鰭式JFET與鰭式MOSFET之方法、裝置及 系統。一方法實施例包括在一基板上形成至少一個縛式 MOSFET及在該基板上形成至少一個鰭式JFET。一般熟習 此項技術者將認識到與在於同一晶粒上製造鰭式M0SFET ® 及鰭式JFET兩者時使用三維設計相關聯之益處’如本揭示 案中所陳述,該等益處包括數位能力與改良之類比能力之 整合。另外,讀者將瞭解與將鰭式JFET及鰭式m〇SFET製 造為具有類似高程(例如,高度)相關聯之製造優點’如目 前所揭示,鰭式JFET結構在其他尺寸(例如’寬度及長度) 中比鰭式MOSFET更大以在類比電壓範圍下操作。 如本文中所使用,"鰭式FET"可指代鰭式MOSFET及/或 鰭式JFET中之任一者或兩者。先前已將術語"鰭式FET"互 參 換地用為"鰭式MOSFET"之簡寫術語’此指示鰭式結構裝 置之單一變化(例如,鰭式MOSFET) »然而,本揭示案包 括另一類型之具有鰭式結構之FET(例如,鰭式JFET),如 本文中所使用,將術語"鰭式FET"擴展以一般指代鰭式 MOSFET、鰭式JFET、鰭式MESFET(金屬半導體場效電晶 體,其具有一替代pn接面之金屬半導體肖特基障壁接面, 且其行為類似於JFET),及/或所製造的具有鰭式結構之任 何其他FET。 135783.doc 200933821 二本文中描述了本發明之特定實施例,例如,包括一 或多個常開(例如’耗盡型)nJFET及/或pJFET之實施例;
仁本發明之實施例不限於此,且亦可包括常關(例如,增 強型)JFFT I 。此外’本發明之實施例可包括具兩種極性之 常開及常關MESFET ’其經實施具有一鰭式結構。本發明 實施例不限於用特定材料(諸如’梦及_化鎵(GaAs))製 造之FET。 在下文中’術語”晶圓"與"基板"可互換地使用且將其理 解為包括絕緣體上矽(S〇I)或藍寶石上矽(S〇s)技術、經摻 雜及未經摻雜之半導體、由底部半導體基座支撐之矽的磊 晶層及其他半導體結構。如本文中所使用,術語"基板"或 基板總成"可包括多個基於半導體之結構,其具有一暴露 之半導體表面。半導體無需基於矽。舉例而言,半導體可 為矽鍺、鍺或砷化鎵0當在以下描述中參考"基板"時,可 已利用先前製程步驟在半導體結構及/或基座之中或之上 形成區域或接面。 如本文中所使用,"層"可指代使用沈積、生長或其他材 料聚集過程形成於基板上之層。術語"層"意謂著包括半導 體產業所特有之層,諸如"障壁層"、"介電層"及"導電層"。 術語"層"亦意謂著包括在在半導體技術範圍之外的技術中 所具有之層’諸如玻璃上之塗層。如本文中所使用,"端 子••可一般指代鰭式FET(例如,鰭式JFET或鰭式MOSFET) 之源極、汲極、閘極或主體。 在本揭示案之以下詳細描述中,參看隨附圖式,該等圖 135783.doc -10- 200933821 式形成實施方式之一部分,且在其中以說明方式展示可實 踐本揭示案之一或多項實施例。足夠詳細地描述此等實施 例以使一般熟習此項技術者能夠實踐本揭示案之實施例, 且應理解,可利用其他實施例且在不脫離本揭示案之範疇 的情況下可作出過程、電氣及/或結構之改變。 在該等圖式中,參考數字之第一數字指代使用其的圖 式,而參考數字之剩餘兩個數字指代在若干圖式中始終使 用的本揭示案之實施例的相同或等效部分。圖式之縮放不 表示本文中所說明之各種元件的精確尺寸及/或尺寸比 率。 根據本揭示案之一或多項實施例,(例如)用於數位或類 比應用的至少一個可撓電壓鰭式JFET(例如,nJFET及/或 pJFET)係同至少一個鰭式M〇SFET、/或pM〇s — 起製造於積體電路中,例如,在數位CM〇s組態中。整合 鰭式MOSFET與鰭式jFET支援廣泛多種應用 、混合信號設 计(例如,具有藉由相同製程步驟一起製造的類比電路及 數位電路)’其具有減小的額外複雜性(不同於使用平面 CMOS(例如,在水平面中製造的無鰭式結構之m〇sfet)實 施JFET的先前混合信號設計方法)。根據本揭示案之實施 例’用相對較少數目(例如,23)個額外製造步驟將通道不 在平行於基板之平面中之三維JFET(例如,鰭式JFET)(其 與通道不在平行於基板之平面中之三維m〇sfet(例如,鰭 式MOSFET)相容)整合在一起。 類比電路(其功能基於比例)之準確度可視輸入信號與輸 135783.doc 200933821 出信號之間的關係之精確度而定;因此,類比電路可易受 雜訊攻擊。將類比電晶體電路與數位電晶體電路組合在$ 一晶片上以節省空間之積體電路可包括用於在晶片層級上 隔離類比電路與數位電路之措施。本文中未展示該等特徵 以不使本揭示案之態樣模糊。 MOSFET縮放可減少所使用之面積,從而使得成本降 低。可更密集地封裝較小MOSFET,從而產生較小晶片或 每一單位面積具有更強計算能力之晶片。每一積體電路之 成本可與每一晶圓可製造的晶片之數目有關。因此,較小 的積體電路可允許每一晶圓有更多晶片,從而降低每一晶 片之價格。 θ 隨著電晶體變得更小,石夕中產生電晶體之性質中之多者 的原子之數目減少。在晶片製造期間,隨機過程變化可影 響電晶體之大小,隨著電晶體縮小,該等變化變為總電晶 體大小之較大百分比。因此,電晶體特性可變得確定性較 低而統計性較高,且統計變化可增加設計難度。 實施於塊狀矽及SOI上的具有垂直通道以及水平通道之 鰭式M0SFET係一般熟習此項技術者已知的。此等三維鰭 式結構(例如,垂直鰭式結構)之缺點中之一者為增加的構 形變化。可廣泛變化之構形可使製造過程變複雜,例如, 使在各種高度之結構上形成觸點更困難。根據本揭示案之 一或多項實施例,提供一種用於減少鰭式Fet裝置之構形 之方法》 圖1A至圖1C說明根據本揭示案之—或多項實施例的在 135783.doc -12- 200933821 半導體製造過程中之一特定點處的具鰭式MOSFET結構 128之積體電路100的若干視圖。該等圖式未按比例繚製。 圖1A說明俯視圖’圖1B說明沿切割線1B_1B截取之橫截面 圖’且圖1C說明沿切割線1C_1C截取之橫截面圊。雖然本 文中描述(例如)雙閘極鰭式MOSFET結構且在以下圖式中 .展不其’但本揭示案之實施例不限於此。本文中所展示及 /或描述的本揭示案之一或多項實施例之態樣可應用於其 他多閘極組態’例如,三閘極組態。 Ο 如圖1A至圖1C中之一或多者中所展示,本揭示案之一 或多項實施例包括一形成於一底部絕緣體層1〇4(例如,底 部氧化物(BOX))上方之矽(si)層ι〇2(例如,SOI層),及一 形成於矽層102上方之厚絕緣體層106(例如,介電質)。在 一或多項實施例中’將厚絕緣體層1〇6形成為具有一約 1,〇〇〇埃之厚度;然而,實施例不限於此。如所展示,藉 由底部絕緣體層104將鰭式M0SFET結構(例如,128)與半 • 導體基板105(例如’塊狀矽晶圓)隔開。可藉由另一方法將 梦層102及絕緣體層1〇4沈積或聚集在各別下伏層上,例如 藉由熱氧化一個晶圓、接著將另一晶圓接合至該晶圓如 形成SOI晶圓所已知的。在一或多項實施例中,可將絕緣 體層104形成為具有一大約145 nm之深度。在一或多項實 施例中,矽層102可形成於絕緣體層1〇4上方。厚絕緣體層 106在形成鰭式結構128時充當用於圖案化之遮罩。此遮罩 可由(例如)二氧化矽(Si〇2)之一薄層及氮化矽(Si3N4)之一 薄層形成,該等層構成厚絕緣體層106,該等層未在圖“ 135783.doc -13- 200933821 至圖1C中個別展示’因為該技術係此項技術中所熟知的。 如讀者將瞭解’所製造的鰭式FET裝置可視摻雜之選擇 而組態成純質、P型或n型鰭式FET裝置。如讀者將瞭解, 厚絕緣體層106可由諸如二氧化矽(si02)、氮化碎 (SiN/Si2囊3N4) 1氧切(Si〇為)之材料或其他介電材 料形成。 Ο 遮蔽且蝕刻被厚絕緣髏層106所覆蓋的矽層102中之開 口,使用光微影技術圖案化具有一特定寬度(w)、高度 ⑻、長度(L)及定向之半導體鰭。舉例而言,可移除上述 的氧化物及氮化物遮罩層之—部分,留下遮罩之將界定簿 式結構128之部分。如圖1A及圖㈣所展示,&化物及氣 化物遮罩層之-部分已(例如)藉由反應性離子予 以移除,以界定鰭式結構(例如,128)之位置。在各種實施 例中,此製程步驟用以確^底部絕緣體層1()4上的轉式結 構之位置及大小’該等韓式結構例如可形成__cm〇s裝置 之一對錄式MOSFET結構,例如,與一 cm〇s裝置中之兩 個互補電晶體相關冑,一電晶體為p通道電晶體且另一電 晶體為η通道電晶體,一或多項實施例,在圖Μ至圖 1L中展示形成於底部絕緣體層上之單一韓式_Ετ結 構。在-些實施例中’如-般熟f此項技術者所理解使 用其他微影及蚀刻技術形成適當之韓式^)^構 韓式M〇SFET裝置之—些鰭式結構^分(例如,閉極導 體)可她鄰隔離部分(例如,在裝置、晶片區域及/或塊狀 導雜之間)’諸如如圖mt所示之122。根據—或多項 135783.doc •14- 200933821 實施例,每一縛可具有一寬度(w),其足夠薄以被環繞間 極(圖1A至囷1C中未展示,但其可藉由稍後處理形成)完全 耗盡。如熟習此項技術者將瞭解,鰭式結構128之s〇I矽 1〇2部分充當通道區域,以用於在完成的鰭式m〇sfet裝 置"開通"時使電流流過。根據一或多項特定實施例,每一 鰭可具有近似於MOSFET鰭式結構通常已知的長度及高度 . 的長度(L)及而度(H);然而,本揭示案之實施例不限於特 定尺寸。圖1B及圖1C展示寬度(w)、長度及高度尺 〇 寸之定向。 在圖1A至圖1C中展示彼此平行地配置的兩個鰭;然 而,本揭示案之實施例不限於此。可將該結構延伸以包括 垂直及/或水平方向上之額外閘極。根據一或多項實施 例,可輕微摻雜(例如,1〇〗5個原子/cm3) 一在各別鰭上越 過長度(L)而延伸之通道區域。 圖1D至圖1F說明根據本揭示案之一或多項實施例的在 參半導體製造過程中之一特定點處的具鰭sMOSFET結構(例 如,128)之積體電路1〇〇的若干視圖。圖1〇說明俯視圖, 圖1E說明沿切割線1E-1E截取之橫截面圖,且圖1F說明沿 切割線1F-1F截取之橫截面圖。在形成該等_sM〇sFErj^ 構128之後,在該等鰭式MOSFET結構之剩餘厚絕緣體層 106及矽層102(例如,圖1B中所示的結構128之s〇i部分 102)上方生長或沈積一具適當介電常數之閘極介電層 108’如圖1D至圖㈣所展示,其包括一在側壁區域之上 之層及在側壁區域上之至少一薄層。在_或多項實施例 135783.doc 200933821 中’將閘極介電層108形成為具有一比厚絕緣體層1〇6之厚 度小付多的厚度;然而’本發明之實施例不限於特定比 例。為了清楚地說明本發明之實施例之特定特徵,該等囷 式未按比例繪製,亦未按相對比例繪製。舉例而言,可相 對於針對厚絕緣體層106所展示之尺寸誇示該等圖式中所 說明的閘極介電層108之比例,厚絕緣體層ι〇6之尺寸可實 際上比閘極介電層108厚一或多個數量級。在一或多項實 施例中’閘極介電層108可由二氧化石夕(si〇2)製成。 圖1G至圖II說明根據本揭示案之一或多項實施例的在半 導體製造過程中之另一特定點處的具鰭sMOSFET結構(例 如’ 128)之積體電路1〇〇的若干視圖。圖1G說明俯視圖, 圖1Η說明沿切割線1 Η-1Η截取之橫截面圖,且圖11說明沿 切割線11-11截取之橫截面圖。 在各種實施例中’閘極形成於閘極介電層1〇8上方。在 底部絕緣體層104及鰭式結構(例如,圖丨Ε中所示之錄式結 構128)之部分上沈積一導電層11 〇(例如,閘極導體),使得 閘極介電層108之外部表面之部分為該閘極材料(例如,導 電層110)所覆蓋。隨後圓案化導電層110,且導電層110包 括一閘極觸點平台塾部分(gate e〇ntaet ianding pad p〇rti〇n)lll,可在進一步處理步驟中在該部分lu上形成 一閘極連接。根據本揭示案之一或多項實施例,該等縛式 結構128之寬度(圖1A至圖1C中之W)通常係薄的。舉例而 言’該等鰭式結構128可經尺寸設定以使得寬度比高度尺 寸或長度尺寸中之任一者小得多。 135783.doc • 16- 200933821 一般熟習此項技術者將瞭解,已在鰭式結構(例如, 128)與周圍矽隔離部分(例如,結構122)之間提供足夠空 間,使得閘極觸點平台墊部分lu可凹陷至一高程,於該 兩程上形成之閘極觸點將具有與鰭式結構(例如,128)高程 處於準平面的一頂部表面。料面意味著一種構形,其並 #精確的平面’而是使其相關聯峰及谷之量值經處理以便 • 減輕兩者間之差異。如圖1H中所示,閘極觸點平台墊部分 111經充分凹陷至鰭式結構(例如,128)高程以下,以允許 在其上形成一具有一厚度之閘極觸點,該厚度可由鰭式結 構(例如,128)高度之一部分部分或完全地抵消。根據一或 多項實施例,導體層110及平台墊部分ιη係由相同材料形 成,該材料可為適當類型(例如,n型或p型)之金屬性、完 全矽化之多晶矽(”FUSP)或經摻雜多晶矽(,,P〇Ly")及其他 材料。 雖然本文中可參考"一閘極"(亦即,單數閘極)來描述導 馨電層且在圖1G及圖1H中將導電層展示為係電連接的且 形成於一各別鰭式結構128之相對側壁107上,但一般熟習 此項技術者將瞭解,可在鰭式結構128之垂直表面上形成 分開形成且視情況獨立操作的多個閘極,例如,形成於相 對側壁107上之第一(前)閘極及第二(後)閘極,或一三閘極 裝置等。多閘極裝置藉由控制額外通道區域而有助於更大 電流流經該裝置。 一般熟習此項技術者將瞭解,閘極導體(例如,具有閘 極觸點平台墊區域丨丨丨之導電層11〇)與半導體開口邊界之 135783.doc -17- 200933821 間的空間(例如,間隙120)可維持在最小尺寸,亦即,在仍 維持兩者之間的隔離的同時儘可能地使空間保持為小的。 此等間隙120可在製造過程中之另一點處用隔片填充劑(例 如,隔片氧化物)填滿。舉例而言,根據多項實施例中之 一者,可將導電層(例如,閘極導體11〇及/或)與周圍矽隔 離部分(例如,結構122)之間的該等間隙i 20製造為具有最 小尺寸。在另一實例中,根據多項實施例中之一者,可在 導電層11〇(例如,閘極導體)與源極及汲極觸點墊位置(例 如,參見圖1J及圖1L中的源極及汲極觸點墊佔據面積I% 位置)之間留下最小空間124。 如圖1H中所示,組態源極及汲極,以使得當各別鰭式 MOSFET裝置為"開"時,電流可在鰭式結構128中於源極與 汲極之間(例如,在鰭式結構128之矽層1 〇2之側壁107中)流 動。舉例而言,電流可垂直於圖1H中的圖紙之平面流動。 一般熟習此項技術者將瞭解,若干技術可用於在隔片形成 之前或之後形成源極及汲極觸點延伸部分(未圖示)。舉例 而言,藉由植入、適當摻雜或藉由形成肖特基障壁而在平 坦頂部梦上界定源極區域及汲極區域,例如,如圖1G及圖 II中所示,進入至SOI 102中。雖然在圖ig及圖II中說明 了 一種源極及汲極定向,但本發明之實施例不限於此,例 如’源極區域及汲極區域可與圖1G及圖II中所示之彼等區 域相反。可藉由一般熟習此項技術者所已知的技術(例 如’脈衝電漿摻雜(PLAD))來執行源極區域及汲極區域及 其延伸部分之摻雜。在圖1G中以114指示與一對應鰭式結 135783.doc •18- 200933821 構相關聯之源極及汲極植入窗口,該等植入窗口通常指示 經暴露以進行摻雜之區域(其他區域經適當遮蔽以防止換 雜)。如一般熟習此項技術者將理解,用於特定摻雜技術 之植入窗口的精確遮罩圖案可與圖1G中藉由植入窗nU4 通常所說明的圖案相同或不同。 藉由使用遮蔽及光微影技術輕微摻雜一在暴露的各別源 極及没極區域之表面以下的區域來形成各別源極及汲極延 伸部分(未圖示)。在源極及汲極區域周圍的源極及汲極延 伸部分已完成後,可針對每一各別區域使用適當摻雜劑以 已知濃度植入源極及没極區域(關於額外細節請參見以下 摻雜劑論述)。在植入源極及汲極後,可退火源極及汲極 以將摻雜劑驅趕至源極及;及極中。在一些實施例中,可將 源極及汲極在大約lOOOt下退火大約5秒鐘。在形成源極 及汲極之後,可用額外CMOS製程步驟處理鰭式厘0!51^丁 結構128。亦可沿著鰭式結構(例如,128)在垂直方向上形 成多個閘極以及源極及沒極區域。 為了在同一晶粒上有效率地製造不同類型之鰭式 MOSFET及鰭式JFET(稍後論述),可針對特定鰭式FET裝 置同時執行一些摻雜過程。舉例而言,在形成11通道鰭式 MOSFET及/或n通道鰭式JFET之源極及汲極區域時使用一 適虽的η型分布。通常,為此等目的使用諸如砷(As)之摻 雜劑;然而,本發明之實施例不限於此。相反地,在形成 P通道鰭式MOSFET及/或1)通道鰭式JFET之源極及汲極區域 時使用一 P型分布(例如,通常為硼(B))。又,本發明之實 135783.doc • ]9· 200933821 施例不限於特定摻雜劑》在形成η通道鰭sM〇SFET閘極 時使用11型導電材料(例如,經摻雜多晶矽),且/或用n型分 布(例如’通常為砷(As))處理在ρ通道鰭式jfet之ρη接面上 方之閘極。在形成卩通道鰭SM〇SFET閘極時使用ρ型導電 材料(例如,經摻雜多晶矽),且/或用p型分布(例如,通常 • 為硼(B))處理在11通道鰭式J,FET之pn接面上方之閘極。熟 . 習此項技術者將瞭解可藉以使用常見遮罩、圖案化及摻雜 過程將類似摻雜分布(doPing Profile)同時應用於不同鰭式 FET結構之方式。將關於鰭式JFET之製造於下文進一步論 述此方式。 圖1J至圖1L說明根據本揭示案之一或多項實施例的在半 導體製造過程中之另一特定點處的具鰭式M〇SFET結構(例 如’ 128)之積體電路100的若干視圖。圖丨】說明俯視圖, 圖ικ說明沿切割線丨尺—丨尺截取之橫截面圖,且圖il說明沿 切割線1L-1L截取之橫截面圖。觸點墊佔據面積126位於該 ❹ 等鰭式MOSFET結構128上,以用於各別源極及汲極金屬 化連接(例如,經由通路)。另外,至少一個且較佳複數個 觸點墊佔據面積126位於閘極觸點平台墊區域U1上。沈 積、遮蔽且蝕刻一隔片介電質112以形成圖u至圖1L中所 ,說明之實施例。 用隔片介電質112填充圖ig及圖1H中所示的在導電層 no或閘極觸點平台墊區域lu與周圍矽隔離結構122之間 的間隙120以增加所得構形之平面性。視鰭式結構128與導 電層110(包括閘極觸點平台墊區域m)之間的相對高度而 135783.doc -20- 200933821 二隔片介電質112可在閘極觸點平台塾區域丨i〗上延 伸’如圖1K中所示。然而’閘極觸點平台墊區域⑴之相 對高度可經設計以比圖1K中所示的進一步垂直延伸,以使 得隔片介電質112之蝕刻或平面化可穿過隔片介電質 (例如在其上)而暴露閘極觸點平台塾區域1 1〗,例 如,以提供至閘極導電層11〇之閘極觸點平台墊區域1U中 的觸點墊佔據面積126之可到達性。以此方式可將鰭式 結構128以及源極、汲極及閘極觸點墊之頂部製造成具有 大體上相同的高度(亦即,準平面構形)。 本揭示案之上述實例實施例提供一準平面構形,其中源 極、汲極及閘極觸點平台墊高程相對於鰭式結構高程凹 藉此簡化後績觸點圖案化。此外,在本揭示案之一或 多項實施例中,藉由儘可能地靠近一閘極導體定位各別源 極及汲極觸點平台佔據面積(例如,126)而將源極/汲極串 聯電阻減小至先前方法鰭式M0SFET裝置組態之串聯電阻 以下。一般熟習此項技術者將瞭解,高源極/汲極電阻易 於使短通道益處無效。 根據本揭示案之一或多項實施例,在一共同製造過程中 將趙式MOSFET與鰭式JFET整合在一起,例如,藉由同一 製造製程步驟來製造鰭式jFET之部分及鰭式MOsfet之部 分。在將鰭式JFET與鰭式MOSFET整合在一起時,使用n 型摻雜劑(針對nJFET及PMOS裝置組態)輕微摻雜鰭式結構 (例如,圖1B中所示之矽層1〇2),且使用p型摻雜劑(針對 PJFET及NMOS裝置組態)輕微摻雜鰭式結構。 135783.doc •21 200933821 圖2A至圖2C說明根據本揭示案之一或多項實施例的在 半導體製造過程中之一特定點處的積體電路200之一鰭式 JFET結構的若干視圖。如上文所提及,可使用共同製造製 程步驟在製造其他鰭式JFET裝置(例如,nJFET裝置及/或 pJFET裝置)的同時且在製造鰭式MOSFET裝置(例如, - NMOS及/或PMOS裝置,諸如結合圖1A至圖1L描述的裝 . 置)的同時在同一基板上製造圖2A至圖2C中所說明之鰭式 JFET,以形成兩種類型裝置之部分。然而,為了清楚地說 〇 明鰭式JFET製造,圖2A至圖2C以及其後的圖2D至圖2F之 說明省略展示任何其他裝置。圖2A說明JFET鰭式結構的 俯視圖,圖2B說明沿切割線2B-2B截取之橫截面圖(例如, 穿過JFET鰭式結構之侧視圖),且圖2C說明沿切割線2C-2C截取之橫截面圖(例如,穿過JFET鰭式結構之端視圖)。 圖2A至圖2C說明具有一矽(Si)層202(例如,SOI層)的鰭 式JFET結構200之一實施例,該矽層202形成於底部絕緣體 層204(例如,底部氧化物(BOX)上方。如圖2A至圖2C之實 ❹ 施例中所示,藉由底部絕緣體層204將鰭式JFET結構與半 導體基板205(例如,塊狀矽晶圓)隔開。矽層202及絕緣體 . 層204可沈積或聚集在各別下伏層(例如,熱生長之二氧化 矽)上。在一或多項實施例中,可在絕緣體層204上方形成 矽層202達一特定鰭高度(HF);然而,本揭示案之實施例 不限於特定尺寸。在將鰭式JFET與鰭式MOSFET—起整合 在同一晶圓上的情況下,鰭式JFET及鰭式MOSFET之鰭係 由同一矽層(例如,圖1B至圖1C中之矽層102及圖2B至圖 135783.doc -22- 200933821 2C中之矽層202)形成,可將鰭式JFET及鰭式MOSFET之該 等鰭式結構製造為具有大體上相同的高度,以使得達成鰭 式FET裝置之準平面構形。 根據一或多項實施例,在鰭式FET鰭的預期位置上方於 矽層202之上形成一厚氧化物(或其他絕緣體)層206。根據 一或多項實施例,將鰭式JFET厚氧化物層206形成為具有 一大約1,000埃之厚度;然而,本揭示案之鰭式JFET實施 例不限於此。在一些實施例中,厚氧化物層206可為二氧 化矽(Si02)。 (例如)藉由使用已知光阻及光微影技術遮蔽且蝕刻厚絕 緣體層206,以圖案化具有一特定鰭寬度(WF)、長度及定 向之半導體鰭。舉例而言,可移除厚氧化物層206之一部 分,從而留下界定該等鰭式結構之遮罩之部分。如熟習此 項技術者將瞭解,可(例如)藉由反應性離子蝕刻(RIE)移除 矽層202之未被厚氧化物層206遮蔽之部分,以形成該等鰭 式結構。在一些實施例中,使用其他微影及蝕刻技術形成 適當之鰭式結構,其將如下文所論述經進一步處理成為鰭 式JFET。根據一或多項實施例,藉由用以形成鰭式 MOSFET裝置之鰭的相同製程步驟同時形成(例如,遮蔽、 圖案化及蝕刻)鰭式JFET裝置之一或多個鰭。根據一或多 項實施例,在圖2A至圖2F中展示形成於底部絕緣體層上之 單一鰭式JFET結構。 在由矽層202形成鰭之後,在鰭式JFET鰭式結構上方(且 根據一或多項實施例,同時在鰭式MOSFET鰭式結構(若存 135783.doc -23- 200933821 在)上方)(包括在發側壁區域之上及在補壁區域上)生長 或以其他方式形成(例如,藉由氧化)具適當介電常數之薄 問極介電層208。因此,相對於韓式結構上之厚氧化物層 206之厚度’閘極介電層挪之形成不將很大厚度添加至錄 式JFET縛式結構之頂部。將開極介電層2〇8形成為具有一 ’ &匕厚氧化物*層206薄得多的厚i,且(例如)可比厚氧化物層 . 6之尺寸薄或多個數量級。一般熟習此項技術者將瞭
解,可與先前所論述之鰭式M〇SFET裝置之閘極介電層 Ο 108(例如’與間極介電層1〇8相同的層)同時形成鰭式JFET 裝置之閘極介電層208。 藉由進一步圖案化,自沿著鰭式JFET鰭式結構側壁之各 處(例如,在如圖2A中所示之部分B、D&F處)選擇性地移 除閘極介電層208。在自該等側壁移除該等介電層以暴露 下面的發層202時,亦可自鰭之頂部移除閘極介電層2〇8及 /或厚氧化物層206之一些或全部。因此,閘極介電層2〇8 _ 可保留且/或可暴露矽層202之上的厚氧化物層206(圖2A展 示閘極介電層208已移除,暴露部分b、D及F處的厚氧化 物層206)。然而’用以自該等側壁移除閘極介電層2〇8之 過程並不可觀地影響鰭之頂部上的厚氧化物層2〇6,如圖 2A及圖2B中所說明,氡化物層2〇6保留。用以自該等側壁 選擇性地移除該閘極介電層之方法係熟知的,例如,可使 用光微影技術、定向姓刻等》如一般熟習此項技術者將瞭 解’根據在一共同基板上形成至少一個鰭式JFET裝置及至 少一個鰭式MOSFET裝置之一或多項實施例,用以自鰭式 135783.doc -24· 200933821 JFET結構之部分的側壁移除閘極介電層208之處理步驟係 形成鰭式MOSFET結構所需的製造步驟之補充。因此,儘 管處理步驟之數量比形成一鰭式MOSFET所必需之步驟稍 微增加,但可根據本發明之一或多項實施例在與鰭式 MOSFET相同的晶圓上製造鰭式JFET。 - 圖2D至圖2F說明根據本揭示案之一或多項實施例的在 半導體製造過程中之另一特定點處的積體電路200之一鰭 式JFET結構部分的若干視圖。圖2D說明俯視圖,圖2E說 © 明沿切割線2E-2E截取之橫截面圖(例如,穿過JFET鰭式結 構之側視圖),且圖2F說明沿切割線2F-2F截取之橫截面圖 (例如,穿過JFET鰭式結構之端視圖)。請注意,圖2D中之 切割線2F-2F位於不同於圖2A中所示之切割線2C-2C的一 位置處,以說明不同特徵。圖2F說明穿過在鰭式JFET閘極 以下的通道之切片,通道長度垂直於圖紙之平面自汲極 (在圖紙之平面之下)延伸至源極(在圖紙之平面之上)。 JFET閘極接面長度確定通道長度(圖2A/2B及圖2D/2E中 之Lc)及通道寬度(圖2E及圖2F中之Wc)。JFET鰭式結構之 鰭寬度(WF)有時亦被稱為鰭式結構之厚度,如圖2A及圖 2C中所示。JFET鰭寬度(WF)通常比MOSFET鰭之寬度(亦 即,厚度)(例如,圖1A及圖1B中之W)大。舉例而言,在 於一共同基板上形成至少一個鰭式JFET及至少一個鰭式 MOSFET時,可將與至少一個鰭式JFET相關聯之一鰭式結 構形成為具有比與該至少一個鰭式MOSFET相關聯之一鰭 式結構大的一寬度。根據本揭示案之一或多項特定實施 135783.doc -25- 200933821 例,鳍式JFET寬度(Wf)為大約1〇〇 nm;然而,實施例不限 於此尺寸可使用多個趙(例如,平行的)以容納一給定驅 動電流。藉由一特定JFET之所要操作特性(其臨限電壓及 通道摻雜劑濃度)確定相對kM〇sfet鰭寬度(亦即,厚度) 的額外JFET鰭寬度(亦即,厚度)。 根據本揭示案之一或多項實施例,臨限電壓之量值在負 - 1,2伏特(-1.2 V)至負U伏特(_1.5 V)之範圍内,且藉由一 具有源極處之雙接面閘極合併所誘發之耗盡區域之斷開條 ® 件來界定。可將通道長度(例如’圖2A及圖2B中所示之
Lc)、没極與閘極之間的距離(例如,圖2A及圖2B中所示之 LD)及源極與閘極之間的距離(例如,圖2A及圖28中所示之 Ls)調整至所需的施加電壓及所要的裝置線性。可在一共 同基板上製造各種尺寸之鰭式jFET,例如,實施例不限於 任何特定尺寸或不限於特定尺寸集合。根據一或多項實施 例,在一基板上形成具有一第一尺寸集合的第一數目個半 _ 導體鰭,且在該基板上形成具有一第二尺寸集合的第二數 目個半導體鰭。該第一尺寸集合及該第二尺寸集合至少具 有不同的汲極至閘極間距及源極至閘極間距,以便達成不 同的鰭式JFET操作特性(例如,操作電壓及線性)。根據本 發明之一或多項實施例,形成具有類似高度尺寸之鰭以提 供一準平面構形。不同於MOSFET裝置,藉由適當的尺寸 選擇’ JFET裝置可承受高達30-50伏特之電壓,因此暗示 比MOSFET裝置相對較大的通道容積。 如上所述’藉由自側壁移除閘極介電層208來暴露矽層 135783.doc -26- 200933821 202沿著鰭式JFET結構之側壁的部分(例如,圖2B中所示之 部分B、D及F)。部分B、D及F為分別形成鰭式JFET之源 極、汲極及閘極區域之部分,其中在多晶矽("POLY")沈積 之前暴露矽層202。厚氧化物層206及閘極介電層208保留 在鰭式JFET結構之其他部分上,該等部分包括處於各別末 . 端處之部分A及G、在源極區域與閘極區域之間的長度為
Ls之部分C及在閘極區域與汲極區域之間的長度為LD之部 分E。移除部分D内的沿著鰭式JFET結構之側壁之閘極介 Ο 電層208露出閘極區域中具有一長度Lc之矽通道。 在(多個)pJFET裝置之暴露閘極區域上方、在(多 個)nJFET裝置之暴露源極/汲極區域上方同時形成(例如, 沈積且圖案化)原位摻雜之η型多晶矽(例如,SiGe POLY),且將η型多晶石夕作為(多個)NMOS裝置之η型POLY 閘極。沈積POLY以使其與沿著側壁及在鰭式JFET鰭式結 構之頂部上的任何剩餘厚氧化物層206(及閘極介電層 208,若存在)之上的暴露矽接觸。同樣地,在(多個)nJFET 裝置之暴露閘極上方、在(多個)pJFET裝置之暴露源極/汲 極區域上方同時形成(例如,沈積且圖案化)原位摻雜之P型 POLY,且將p型POLY作為(多個)PMOS裝置之p型POLY閘 極0 如圖2F中所示,閘極導電層217(例如,POLY)係沿著鰭 式結構側壁之部分直接接觸矽層202而置放。後續熱循環 將POLY摻雜劑自POLY驅趕至鄰近矽中,從而形成側面擴 散接面區域209(例如,JFET裝置之閘極接面)。讀者將瞭 135783.doc -27- 200933821 解且如圖2E中所示,nJFET將因此具有(例如)形成於η型半 導體(例如,202)上方的一 η型多晶矽源極導電層(例如, 213)、一 η型多晶矽汲極導電層(例如,215)及一 ρ型多晶矽 接面-閘極導電層(例如,217)。相反地,pJFET將具有(例 如)形成於P型半導體上方的一 P型多晶矽源極導電層(例 - 如,213)、一 ρ型多晶石夕汲極導電層(例如,215)及一 η型多 . 晶矽接面-閘極導電層(例如,217)。與JFET結構之矽202接 觸的經適當摻雜之多晶矽形成源極、汲極及閘極接面之間 〇 的適當接面(例如,圖2F中所示之擴散區域209)。 如圖2D至圖2F中所指示,展示鰭式JFET通道長度(Lc)及 通道寬度(Wc)。如圖2E及圖2F中所示,通道沿著矽鰭式結 構之該(該等)側壁定位,其中通道寬度(Wc)對應於鰭式結 構高度(HF)。然而,本發明之實施例不限於此。一般熟習 此項技術者亦將瞭解用於移除厚氧化物層206及在鰭式結 構之頂部上形成通道之處理步驟。 熟習此項技術者將認識到,可針對位於同一晶圓上之鰭 式MOSFET及鰭式JFET同時形成半導體鰭式結構(例如, 藉由相同製造製程步驟)。另外,熟習此項技術者將瞭 解,藉由共同製造步驟,可根據一 CMOS技術製造多個 nJFET 、 pJFET 、 NMOS及PMOS裝置,亦即,在一共同基 板上具有用η型半導體摻雜形成之裝置及用ρ型半導體摻雜 形成之裝置。因此,根據本揭示案之關於在一基板上製造 至少一個鰭式MOSFET及在該基板上製造至少一個鰭式 JFET之實施例,PMOS及nJFET裝置之η型半導體可大體上 135783.doc -28 - 200933821 同時一起摻雜(例如,藉由同一製造製程步驟),且nmos 及pJFET裝置之p型半導體可同時一起摻雜(例如,藉由另 一相同製造製程步驟)。 根據本揭示案之一或多項實施例,藉由一共同製造過程 將鰭式MOSFET與鰭式JFET—起整合在同一晶粒上且形 成。舉例而言’可同時形成鰭式MOSFET及鰭式JFET之半 導體層;且可藉由共同處理步驟同時圖案化鰭式MOSFET 及歸式J F E T之錄式結構(例如,柱)且由同·一半導體層形成 該等鰭式結構。其後,可同時摻雜鰭式MOSFET(例如,鰭 式pMOSFET)及鰭式JFET(例如,鰭式nJFET)之η型半導體 鰭式結構,且可在另一步驟同時摻雜鰭式MOSFET(例如, 鰭式nMOSFET)及鰭式JFET(例如,鰭式pJFET)之p型半導 髏鰭式結構。如先前所描述,可同時在鰭式JFET結構及鰭 式MOSFET結構上方形成一或多個介電層。如先前所論 述,對於不同類型FET裝置之類似摻雜的區域,亦可同時 完成整合式鰭式JFET與鰭式MOSFET之各別源極、汲極及 閘極區域的進一步形成及摻雜。可在形成NMOS裝置之閘 極及在形成pJFET裝置之pn接面之η部分時同時施加η型 POLY。可在形成PMOS裝置之閘極及在形成nJFET裝置之 pn接面之p部分時同時施加p型POLY。 圖3說明一記憶體系統301,其包括一耦接至一記憶體裝 置320之處理器310,該記憶體裝置320包括記憶體單元之 一陣列300,例如,一記憶體陣列。記憶體裝置320包括本 揭示案之一或多項實施例,例如,一具有根據一 CMOS製 135783.doc -29· 200933821 程而形成於一共同基板上之至少一個鰭式JFET及至少一個 鰭式MOSFET的積體電路。記憶體系統3〇1可包括分離之 積體電路,或處理器310及記憶體裝置32〇兩者可在同一積 體電路上。處理器310可為微處理器或某一其他類型之控 制電路,諸如特殊應用積體電路(ASIC)。 為清楚起見,已將電子記憶體系統3〇1簡化以集中於與 本揭不案有特定相關性之特徵。記憶'體裝置32〇包括記憶 體單元之一陣列300。如一般熟習此項技術者將瞭解,該 等s己憶體單元至感測線及源極線之連接方式視該陣列是 NAND架構、N0R架構及AND架構還是某一其他記憶體陣 列架構而定。 圖3之實施例包括用以鎖存經由1/0電路36〇在1/〇連接 362上提供的位址信號之位址電路340。藉由列解碼器344 及行解碼器346接收且解碼位址信號以存取記憶體陣列 300。根據本揭示案’熟習此項技術者將瞭解位址輸入 連接之數目視記憶體陣列300之密度及架構而定,且位址 數目隨此憶體單元之增加數目及記憶體區塊及陣列之增 加數目兩者而增加。 記憶體單元之陣列300包括可利用與程式化相關聯之操 作電壓的單元。記憶體裝置32〇藉由使用感測/緩衝器電路 感測記憶體陣列行中之電壓及/或電流變化來讀取記憶體 陣列3〇〇中之資料,在此實施例中,感測/緩衝器電路可為 讀取/鎖存電路350。讀取/鎖存電路350可經耦接以讀取且 鎖存來自記憶體陣列300之一列資料。包括1/〇電路36〇以 135783.doc -30· 200933821 用於經由1/〇連接362與處理器360進行雙向資料通信。包 括寫入電路355以將資料寫入至記憶體陣列3〇()。 控制電路370解碼由控制連接372提供的來自處理器31〇 之k號。此等信號可包括晶片信號、寫入致能信號及位址 鎖存彳s號,該等信號用以控制對記憶體陣列3 〇〇之操作, 肖等操作包括讀取、寫入、恢復及擦除操作。在各種實施 例中,控制電路370負責執行來自處理器31〇之指令以執行 本揭示案之操作及程式化實施例。控制電路3 7〇可為狀態 ❹ 機、序列器或某一其他類型之控制器。熟習此項技術者將 瞭解,可提供額外電路及控制信號,且已減少圖3之記憶 體裝置細節以有助於說明簡單性。記憶體系統3〇丨之特定 組件可處理類比信號,例如,可操縱一類比信號且隨後用 儲存於記憶體陣列中之數位值數位化該類比信號。此外, 記憶體系統301可實施為晶片上系統之部分。 圖4為根據本揭示案之一或多項實施例的具有記憶體裝 ❹置之記憶體模組的功能方塊圖,該記憶體裝置包括具有形 成於一共同基板上之至少一個鰭式JFET及至少一個轉式 MOSFET的一或多個積體電路。雖然參考記憶體模組4〇〇 • 論述之概念可適用於其他類型之抽取式或攜帶型記憶體 (例如’ USB快閃磁碟)且意欲在本文中所使用之"記愧體模 組"之範疇内’但圖4將記憶體模組4〇〇說明為記憶卡。舉 例而言,記憶體模組400可實施為晶片上系統之部分。 在一些實施例中,記憶體模組400將包括外殼405(如所 描繪)以封閉一或多個記憶體裝置420,但該外殼並非對於 135783.doc -31 - 200933821 所有裝置或裝置應用均為必需的。至少一個記憶體裝置 420包括記憶體單元之一陣列,其包括本揭示案之一或多 項實施例’例如,整合式鰭式MOSFET及鰭式JFET。在存 在的情況下,外殼405包括用於與主機裝置通信之一或多 個觸點415。主機裝置之實例包括數位相機、數位記錄及 播放裝置、PDA、個人電腦、記憶卡讀取器、介面集線器 及其類似物。對於一些實施例,觸點415採取標準化介面 之形式。舉例而言,對於USB快閃磁碟之情況,觸點415 可採取USB類型A公連接器之形式。然而,一般而言,觸 點415提供用於在記憶體模組4〇〇與具有與觸點415之相容 接受器之主機之間傳遞控制、位址及_/或資料信號之介 面。 記憶體模組400可視情況包括額外電路41 〇,該額外電路 410可為一或多個積體電路及/或離散組件。對於一些實施 例’額外電路41 0可包括一記憶體控制器,該記憶體控制 器用於控制跨多個記憶體裝置420之存取及/或用於提供一 外部主機與一記憶體裝置42〇之間的一轉譯層。舉例而 言’觸點415之數目與至一或多個記憶體裝置42〇的連接之 數目之間可能不存在一對一對應。因此,記憶體控制器可 選擇性地輕接記憶體装置420之I/O連接以在適當時間於適 當I/O連接接收適當信號或在適當時間於適當觸點415提供 適當k號。類似地’主機與記憶體模組4〇〇之間的通信協 疋可不同於存取記憶體裝置420所需的通信協定。記憶體 控制器可接著將自主機接收之命令序列轉譯為適當的命令 135783.doc •32· 200933821 序列,以 逆取對記憶體裝置420之所要存取。除了 列之外,該轉譯可進一步包括信號電壓位準之變化 序 額外電路410可進一步包括不與記憶體裝置— 關的功能性,諸如可由八81(:執行之邏輯功能。又,Λ目 路410可包括用以限制對記憶體模組4〇〇之讀取或寫入電 之電路,諸如密碼保護、生物測定或其類似者。額 410可包括用以指示記憶體模組4〇〇之狀態的電路。舉例而
言,額外電路410可包括用以判定電力是否供應至記憶體 模組400且記憶體模組400目前是否被存取及顯示記憶體模 組之狀態之指示(諸如,通電時之固體光及存取時之閃爍 光)的功能性。額外電路410可進一步包括用以幫助調節記 憶體模組400内之功率需求之被動裝置,諸如去耦合電容 器。 ° 圖5為根據本揭示案之一或多項實施例的晶片上系統58〇 之功能方塊圖,該晶片上系統58〇具有形成於一共同基板 上之至少一個鰭式jFET及至少一個鰭式M〇SFET。根據一 或多項實施例,晶片上系統580包括至少一個類比組件582 及至少一個數位電路組件584。該(該等)類比組件582包括 一或多個鰭式JFET 580,且該(該等)數位組件584包括一或 多個.鳍式MOSFET 588,其中該(該等)鰭式jFET 586及該 (該等)鰭式MOSFET 588係根據一 CMOS製程而形成於一共 同基板上。根據一或多項實施例,該(該等)數位組件584包 括處理器,該處理器耦接至一具有一記憶體單元陣列之 °己憶體裝置’諸如圖3中所說明及上文所述之記憶鱧系統 135783.doc •33· 200933821 301 ;然而,本發明之實施例不限於此。該等類比組件582 可包括(例如)放大器、波形成形電路及其他信號處理電路 及元件。 供整合鰭式JFET與縛式MOSFET之方法、裝置及系 統》—方法實施例包括在一基板上形成至少一個鰭式 MOSFET及在該基板上形成至少一個鰭式JFET。 ❹ 〇 儘管本文中已說明並描述了特定實施例,但一般熟習此 項技術者將瞭解’可用一經計算以達成相同結果之配置來 替代所展示之特定實施例。本揭示案意欲涵蓋本揭示案之 各種實施例之更改或變化。將理解,以說明性方式而非以 限制方式來作出以上描述。當回顧以上描述時以上實 < J之組σ及本文中未特定描述之其他實施例將為熟習此 項技術者所顯而易見。本揭示案之各種實施例之範脅包括 使用以上結構及方法之其他助。因此,應參考隨附之申 請專利範圍連同此等t請專㈣圍被賦予之等效物之完整 範圍來確疋本揭示案之各種實施例之範嘴。 在上述詳細描述中,出於簡化本揭示案之目的,將各種 特徵起群聚於單—實施例中。不應將本揭示案之方法解 、本揭不案之所揭示實施例必須使用比每一申請項 ::確列舉之特徵多的特徵的意圖^更確切地說如以 專利範圍所反映’發明標的物處於少於單一所揭示 實施例之所要特徵 此併入至實施方二中。因…下申請專利範圍藉 式中’其中每一申請項作為一獨立實施例 135783.doc -34- 200933821 而依賴於其自身。 【圖式簡單說明】 圖1A說明根據本揭示案之一或多項實施例的在半導體製 造過程中之特定點處的鰭式MOSFET結構之俯視圖。 圖1B說明根據本揭示案之一或多項實施例的圖1A中所 說明之半導體製造過程中之特定點處的鰭式M〇SFET結構 沿著切割線1B-1B截取之橫截面圖。 圖ic說明根據本揭示案之一或多項實施例的圖lA中所 說明之半導體製造過程中之特定點處的鰭式M〇SFET結構 沿著切割線1C-1C截取之橫截面圖。 圖1D說明根據本揭示案之一或多項實施例的半導體製造 過程中之另一特定點處的鰭式MOSFET結構之俯視圖。 圖1E說明根據本揭示案之一或多項實施例的圖1D中所 說明之半導體製造過程中之特定點處的鰭式M〇SFET結構 沿著切割線1E-1E截取之橫截面圖。 圖1F說明根據本揭示案之一或多項實施例的圖1D中所 說明之半導體製造過程中之特定點處的鰭式M〇SFET結構 沿著切割線1F_1F截取之橫截面圖。 圖1G說明根據本揭示案之一或多項實施例的半導體製造 過程中之第三特定點處的鰭式MOSFET結構之俯視圖。 圖1Η說明根據本揭示案之一或多項實施例的圖1 〇中所 說明之半導體製造過程中之特定點處的鰭式m〇SFEt結構 沿著切割線1H-1H截取之橫截面圖。 圖II說明根據本揭示案之一或多項實施例的圖1G中所說 135783.doc -35· 200933821 明之半導體製造過程中之特定點處的鰭式M〇SFet結構沿 著切割線1I-1I截取之橫截面圖。 圖1J說明根據本揭示案之一或多項實施例的半導體製造 過程中之第四特定點處的鰭式MOSFET結構之俯視圖。 圖1K說明根據本揭示案之一或多項實施例的圖^中所說 明之半導體製造過程中之特定點處的鰭式M〇SFet結構沿 著切割線1K-1K截取之橫截面圖。 ❹ 圖1L說明根據本揭示案之一或多項實施例的圖1J中所說 明之半導體製造過程中之特定點處的鰭式MOSFET結構沿 著切割線1L-1L截取之橫截面圖。 圖2 A說明根據本揭示案之一或多項實施例的半導體製造 過程中之特定點處的鰭式JFET結構之俯視圖。 圖2B說明根據本揭示案之一或多項實施例的圖2A中所 說明之半導體製造過程中之特定點處的鰭式JFET結構沿著 切割線2B-2B截取之橫截面圖。 〇 圖2C說明根據本揭示案之一或多項實施例的圖2A中所 說明之半導體製造過程中之特定點處的鰭式;]^7結構沿著 切割線2C-2C截取之橫截面圖。 圖2D說明根據本揭示案之一或多項實施例的半導體製造 ' 過程中之另一特定點處的鰭式JFET結構之俯視圖。 圖2E說明根據本揭示案之一或多項實施例的圖2d中所 說明之半導體製造過程中之特定點處的韓式;雕結構沿著 切割線2E-2E截取之橫截面圖。 圖2F說明根據本揭示案之—或多項實施例的圖2d中所 135783.doc •36- 200933821 說明之半導體製造過程中之特定點處的鰭式JFET結構沿著 切割線2F-2F截取之橫截面圖。 圖3為根據本揭示案之一或多項實施例的記憶體系統之 功能方塊圖,該記憶體系統具有一記憶體裝置,該記憶體 裝置包括具有形成於一共同基板上之至少一個鰭式JFET及 . 至少一個鰭式MOSFET的一或多個積體電路》 圖4為根據本揭示案之一或多項實施例的記憶體模組之 功能方塊圖,該記憶體模組具有一記憶體裝置,該記憶體 裝置包括具有形成於一共同基板上之至少一個韓式WET及 至少一個鰭式MOSFET的一或多個積體電路。 圖5為根據本揭示案之一或多項實施例的晶片上系統之 功能方塊圖,該晶片上系統具有形成於一共同基板上之至 少一個鰭式JFET及至少一個鰭式M〇SFET。 【主要元件符號說明】 100 102 104 105 106 107 108 110 111 112 ❿ 積體電路 矽(Si)層 底部絕緣體層 半導體基板 厚絕緣體層 側壁 介電層 第一導電層 閘極觸點平台塾部> 隔片介電質 135783.doc -37- 200933821 120 間隙 122 矽絕緣結構 124 最小空間 126 源極及汲極觸點墊佔據面積 128 鰭式結構/鰭式MOSFET結構 >· 200 積體電路 - 202 矽(Si)層/半導體鰭式結構 〇 204 底部絕緣體層 205 半導體基板 206 厚氧化物層 208 閘極介電層 213 源極導電層 215 汲極導電層 217 閘極導電層 300 記憶體單元陣列 301 記憶體系統 310 處理器 320 記憶體裝置 - 340 位址電路 344 列解碼器 346 行解碼器 350 讀取/鎖存電路 355 寫入電路 360 I/O電路 135783.doc -38- 200933821 362 I/O連接 370 控制電路 372 控制連接 400 記憶體模組 405 外殼 • 410 額外電路 415 觸點 420 記憶體裝置 ❹ 580 晶片上系統 582 類比組件 584 數位組件 586 鰭式JFET 588 鰭式MOSFET Η 南度 Hf 鰭高度 ❹ L 長度 Lc 通道長度 L〇 汲極與閘極之間的距離 - Ls 源極與閘極之間的距離 W 寬度 WF 鰭寬度 135783.doc -39-
Claims (1)
- 200933821 十、申請專利範圍: 1. 一種形成電晶體之方法’其包含: 在一基板(105、205)上形成至少一個鰭式MOSFET (100);及 在該基板(105、205)上形成至少一個鰭式JFET(200)。 2. 如請求項1之方法,其中形成至少一個鰭式JFET(200)包 括:根據一 CMOS製程形成多個具有鰭式結構(200)之 nJFET裝置及pJFET裝置° 〇 3.如請求項1之方法,其中將與該至少一個鰭式JFET(200) 相關聯之一鰭式結構(2〇〇)形成為具有比與該至少一個鰭 式MOSFET(IOO)相關聯之一鰭式結構(128)大的一寬度。 4. 如請求項1之方法,其中形成至少一個鰭式 MOSFET(IOO)包括:根據一 CMOS製程形成多個具有鰭 式結構(128)之NMOS FET及 PMOS FET。 5. 如請求項1之方法,其中該方法包括: 根據一 CMOS製程形成多個鰭式MOSFET(IOO)及鰭式 V JFETX200);且 其中同時摻雜鰭式MOSFET(IOO)及鰭式JFET(200)之η 型半導體鰭式結構(128、200),且在另一步驟同時摻雜 鰭式MOSFET(IOO)及鰭式JFET(200)之ρ型半導體鰭式結 構(128 、 200)。 6. 如請求項1之方法,其中同時摻雜鰭式pMOSFET(lOO)及 鰭式nJFET(200)之鰭式結構(128),且同時摻雜鰭式 nMOSFET(lOO)及鰭式pjFET(200)之鰭式結構(200)。 135783.doc 200933821 7_如請求項1之方法,其中形成該至少一個鰭式JFET(200) 及該至少一個鰭式MOSFET(IOO)包括: 在該基板(105、205)上同時形成至少一個鰭式JFET半 導體鰭(200)及至少一個鰭式MOSFET半導體鰭(128); 同時形成一在該鰭式JFET(200)鰭及該鰭式MOSFET (100)鰭上方延伸之介電層(108、208);及 同時形成一在該鰭式JFET(200)鰭及該鰭式MOSFET (100)鰭上方延伸之第一導電層(110)。 〇 8.如請求項7之方法,其中形成該至少一個鰭式JFET(200) 包括: 選擇性地移除與源極(B)區域、汲極(F)區域及閘極(D) 區域相關聯之該介電層(208)。 9.如請求項8之方法,其中形成該第一導電層(110)包括: 同時形成一鰭式MOSFET(IOO)閘極及至少一個鰭式 JFET(200)端子。 _ 10.如請求項9之方法,其中形成該第一導電層(110)包括: ❹ 同時形成一 η型NMOS閘極及pJFET閘極(217)。 11. 如請求項9之方法,其中形成該第一導電層(110)包括: 同時形成一n型NMOS閘極及nJFET源極(213)及汲極 (215)。 12. 如請求項9之方法,其中形成該第一導電層(110)包括: 同時形成一 p型PMOS閘極及nJFET閘極(217)。 13. 如請求項9之方法,其中形成該第一導電層(110)包括: 同時形成一 P型PMOS閘極及pJFET源極(213)及汲極 135783.doc 200933821 (215)。 14.如請求項9之方法,其中該方法包括: 使用不同於該第一導電層(110)經摻雜之一第二導電層 形成至少一個鰭式JFET(200)端子。 15·如請求項1之方法,其中形成具有一準平面構形的該至 ’個韓式MOSFET(l 00)及該至少一個鰭式jFet(200) » 16. —種形成至少一個鰭式JFET(2〇〇)之方法,其包含: 形成至少一個半導體鰭式結構(202); 在該至少一個鰭式結構(202)上方形成一介電層 (208); 自該至夕個韓式結構(202)之與源極(b)區域、没極 (F)區域及閘極(D)區域相關聯之部分選擇性地移除該介 電層(208); 在源極(213)區域及汲極(215)區域上方形成一第一導 電層; 在閘極(2Π)區域上方形成一第二導電層;且 其中該帛二導電層具有不同於該第—I電層之一類型 換雜。 17.如請求項16之方法,其中: 將第一數目個半導體鰭(202)形成為具有一第一尺寸集 合; ' 將第二數目財導趙錄(2〇2)形成為具有一第二尺寸集 合;且 ^ 其中該第-尺寸集合及該第二尺寸集合至少具有不同 135783.doc 200933821 的汲極至閘極間距及源極至閘極間距,以便達成不同的 錯式JFET(200)操作電壓及線性。 18. —種晶片上系統(5〇8),其包含: 具有一鰭式JFET(200)之至少一個類比電路組件 (582); 包括一處理器(3 10)及一耦接至該處理器(3 10)之記憶 體裝置(320)之數位電路組件(584);且 其中至少一個數位電路組件(584)具有一鰭式MOSFET © (1〇〇),且該鰭式JFET(200)及該鰭式MOSFET(IOO)係根 據一 CMOS製程形成於一共同基板(105、205)上。 19. 一種積體電路,其包含: 在一基板(105、205)上之至少一個鰭式JFET(200); 在該基板(105、205)上之至少一個鰭式MOSFET (100);且 其中該至少一個鰭式JFET(200)及該至少一個鰭式 MOSFET(IOO)具有一準平面構形。 20·如請求項19之積體電路,其中該準平面構形包括: 一閘極導電層觸點平台墊(111),其凹陷至不超過一源 . 極及汲極高度之一高度;及 在半導體結構之間的用隔片介電質(112)填充之區域。 21.如請求項19之積體電路,其中: 鰭式MOSFET(IOO)源極延伸部分及汲極延伸部分係形 成於位於離該基板(105、205)最遠、鄰近於一閘極介電 層(108)之一半導體鰭(128)表面上,以便減小串聯電 135783.doc 200933821 阻;且 源極觸點及汲極觸點係形成於位於離該基板(105、 205)最遠之該半導體鰭(128)表面上。 22. —種形成場效電晶體之方法,其包含: 在一基板(105、205)上形成多個MOSFET(IOO); 在該基板(105、205)上形成多個JFET(200);及 . 藉由至少一個製造製程步驟在半導體鰭(102、202)上 共同地形成該等MOSFET(128)結構及該等JFET(200)結 ® 構。 23. 如請求項22之方法,其中該方法包括在JFET半導體鰭 (202)上方形成一MOSFET閘極介電層(108、208)。 24. 如請求項22之方法,其中該方法包括選擇性地移除該閘 極介電層(208)以暴露半導體鰭之與JFET(200)源極(B)區 域、汲極(F)區域及閘極(D)區域相關聯之部分。 25. 如請求項24之方法,其中該方法包括: 在NMOS閘極上方及在半導體鰭(202)之與pJFET源極 ❹ (213)區域及汲極(215)區域相關聯之暴露部分上方形成 一 η型導電層;及 .在PMOS閘極上方及在半導體鰭(202)之與nJFET閘極 (217)區域相關聯之暴露部分上方形成一 p型導電層。 135783.doc
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TWI392058B (zh) | 2013-04-01 |
WO2009067140A3 (en) | 2009-08-13 |
US9076662B2 (en) | 2015-07-07 |
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