CN107221534B - Finfet为基础的闪存胞 - Google Patents

Finfet为基础的闪存胞 Download PDF

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CN107221534B
CN107221534B CN201710165125.3A CN201710165125A CN107221534B CN 107221534 B CN107221534 B CN 107221534B CN 201710165125 A CN201710165125 A CN 201710165125A CN 107221534 B CN107221534 B CN 107221534B
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gate
semiconductor
forming
fins
layer
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CN107221534A (zh
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彼特·巴尔斯
朱尔根·法尔
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GlobalFoundries US Inc
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GlobalFoundries Inc
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    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H01L27/1211—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate

Abstract

本发明涉及FINFET为基础的闪存胞，提供一种制造半导体装置的方法，其包括提供半导体基材，在半导体基材的逻辑区中形成第一多个半导体鳍片，在半导体基材的存储区中形成第二多个半导体鳍片，在第一多个半导体鳍片的诸鳍片之间、及第二多个半导体鳍片的诸鳍片之间形成绝缘层，在第一与第二多个半导体鳍片及绝缘层上方形成电极层，自栅极电极层起在逻辑区中的第一多个半导体鳍片的半导体鳍片上方形成栅极，以及自栅极电极层起在逻辑区中第二多个半导体鳍片的诸半导体鳍片之间形成感测栅极与控制栅极。

Description

FINFET为基础的闪存胞
技术领域
大体上，本发明是关于集成电路与半导体装置的领域，并且更特别的是关于闪存胞(flash memory cell)。
背景技术
诸如CPU、储存装置、ASIC(特定应用集成电路)及类似先进集成电路在制作时，需要根据已指定电路布局，在给定芯片面积上形成大量电路组件。在各式各样的电子电路中，场效应晶体管代表一种重要类型的电路组件，其实质决定此等集成电路的效能。大体上，目前经实践用于形成场效应晶体管(FET)的制程技术有多种，其中，就许多类型的复杂电路系统而言，金属氧化物半导体(MOS)技术鉴于操作速度及/或功率消耗及/或成本效益，由于特性优越，是目前最有前途的其中一种方法。于使用例如CMOS技术制作复杂集成电路期间，举例来说，数百万个N沟道晶体管及/或P沟道晶体管是在包括结晶半导体层的基材上形成。
虽然尖端平面型晶体管架构就效能及控制性可获得显著优点，但鉴于进一步装置扩缩，已提出新的晶体管组态，其中可提供“三维”架构以尝试获得所欲沟道宽度，而同一时间，仍对流经沟道区的电流维持优越的控制性。为此，已提供所谓的FinFET，可在里面于SOI(硅绝缘体)基材的薄主动层中形成硅的薄片或鳍片，其中至少可在鳍片的两侧壁上、且可能在其顶端表面上，提供栅极介电材料与门极介电材料，藉以实现“双闸”或“三闸”晶体管，其沟道区可全空乏。一般而言，在尖端应用中，半导体(例如：硅)鳍片的宽度等级为10nm至20nm，且其高度等级为30nm至40nm。因此，FinFET晶体管架构在本文中亦可称为多闸晶体管栅极，可就提升栅极电极连至各个沟道区的有效耦合提供优点，但不需要对应缩减栅极介电材料的厚度。此外，通过提供此非平面型晶体管架构，亦可增加有效沟道宽度，以使得对于给定的整体晶体管尺寸，可增强电流驱动能力。基于这些理由，为了以非平面型晶体管架构为基础提供增强的晶体管效能，已下了很大的努力。
注意到的是，平面型及三维晶体管装置两者都可根据取代栅极方法或门极先制方法来形成。在取代栅极技巧中，所谓的“虚设”或牺牲栅极结构在初始时形成，并且在进行用以形成装置的许多程序操作中留在原位，例如形成掺杂源极/漏极区，进行退火程序以修复因离子布植程序对基材所造成的破坏，并且活化植入的掺质材料。在程序流程中的一些制点，移除牺牲栅极结构以界定就装置形成HKMG栅极结构处的栅极凹穴。另一方面，使用栅极先制技巧涉及跨布基材形成材料层堆叠，其中材料堆叠包括高k栅极绝缘层(具有大于5的介电常数k)、一或多个金属层、多晶硅层、以及保护性覆盖层，例如氮化硅。进行一或多个蚀刻程序以图型化材料堆叠，藉以就晶体管装置界定基本栅极结构。根据本发明的电熔丝的形成可轻易地在取代栅极与栅极先制两程序流程中整合。
另一方面，逐渐地可能必须将非挥发性闪存胞并入精细的半导体装置中，其中闪存技巧代表一种有前途的技术，可将里面的MOS技术有效率地应用于形成储存胞。为此，基本上，提供一种场效应晶体管，里面的晶体管操作受到控制，另一方面，是通过栅极电极来提供，如以上所述，其另外包括与控制栅极电极电气绝缘、并与场效应晶体管的沟道区及漏极区电气绝缘的浮动栅极。浮动栅极代表性场效应晶体管的控制栅极电极内的介电电荷储存区，并且可保持静置的电荷载子，其进而影响场效应晶体管的电流流动行为。浮动栅极中静置的电荷载子可在建立特定操作模式时予以注射，其亦称为存储胞的编程设计，其中本身有负作用，诸如热载子注射及类似者，亦即，任何类型的漏电流产生机制，可能会产生电荷载子并入电荷储存区的现象。所以，在正常操作模式中，注入电荷储存区的电荷载子从而可能显著影响流经晶体管沟道区的电流，这可通过适当的控制电路系统来侦检。另一方面，存储胞一经抹除，便可移除电荷储存区中的电荷载子，举例来说，通过建立适当的电压条件来移除，由此建立场效应晶体管在正常操作模式期间的可侦检的不同操作行为，亦即以标准供应电压进行操作期间的行为。
闪存胞(即包含浮动栅极的场效应晶体管的闪存胞)的概念虽然提供具有中等高信息密度与低访问时间的非挥发性储存机制，事实仍证明，进一步装置扩缩及相对精细掩膜技术的兼容性可能难以基于用于形成非挥发性储存晶体管的习知概念来达成。尤其是，过去尚未能成功形成与FinFET装置整合的闪存胞。
鉴于上述情况，本发明提供相较于所属技术领域已改善效能特性、并且整合于制造FinFET装置的程序流程里的(快闪)存储胞。
发明内容
以下介绍本发明的简化概要，以便对本发明的一些态样有基本的了解。本概要并非本发明的详尽概述。用意不在于指认本发明的重要或关键要素，或叙述本发明的范畴。目的仅在于以简化形式介绍一些概念，作为下文更详细说明的引言。
大体上，本文中所揭示的专利目标是关于闪存胞。根据本发明，闪存胞可基于FinFET装置来形成。尤其是，可在晶圆的逻辑区中FinFET装置的制造程序流程中整合晶圆的存储区中闪存胞的制造。
提供一种制造半导体装置的方法，其包括提供半导体基材，例如半导体主体基材或SOI基材，在半导体基材的逻辑区中形成第一多个半导体鳍片，在半导体基材的存储区中形成第二多个半导体鳍片，在第一多个半导体鳍片的鳍片之间及第二多个半导体鳍片的鳍片之间形成绝缘层(例如，可由二氧化硅所组成或包含二氧化硅的氧化物层)，在第一与第二多个半导体鳍片及绝缘层上方形成电极层，自栅极电极层起在逻辑区中的第一多个半导体鳍片的半导体鳍片上方形成(FinFET装置的)栅极，以及自栅极电极层起在逻辑区中第二多个半导体鳍片的诸半导体鳍片之间形成(存储胞的)感测栅极与控制栅极。自相同的电极层起形成位于逻辑区的栅极、及感测栅极与控制栅极。
再者，提供一种形成半导体装置的方法，其包括在晶圆的逻辑区中形成FinFET装置，并且在晶圆的存储区中形成闪存胞。逻辑区中形成具有第一高度的第一半导体鳍片，并且在存储区中形成具有比第一高度更大的第二高度的第二半导体鳍片。再者，在第一与第二半导体鳍片上方形成电极层，并且自电极层起在第一半导体鳍片上方形成FinFET装置的栅极。再者，自电极层起，形成与诸第二半导体鳍片的半导体鳍片的第一侧壁邻接的存储胞的感测栅极、以及与所述第二半导体鳍片的该半导体鳍片的第二侧壁邻接的存储胞的控制栅极。
另外，提供一种制造闪存胞的方法，其包括在半导体基材上形成多个半导体鳍片，就多个半导体鳍片的子集形成浮动栅极，以及在多个半导体鳍片之间形成第一绝缘层。使第一绝缘层凹陷至比多个半导体鳍片的高度更小的高度，并且在多个半导体鳍片的子集上方形成牺牲栅极。在诸牺牲栅极之间形成第二绝缘层，之后，移除牺牲栅极。在第一绝缘层中形成凹口，并且就多个半导体鳍片的子集在凹口中形成感测栅极与控制栅极。第一与第二绝缘层可以是氧化物层。
此外，提供一种闪存胞，其包括形成于半导体基材上的半导体鳍片，例如半导体主体基材或SOI基材，其中，半导体鳍片包含第一侧壁及第二侧壁。闪存胞亦包括邻接于半导体鳍片的第一侧壁而成的感测栅极、形成于感测栅极与半导体鳍片的第一侧壁之间的第一高k电介质(举例而言，k>5)、与半导体鳍片的第二侧壁邻接的控制栅极、配置于控制栅极与半导体鳍片的第二侧壁之间的浮动栅极、以及形成于浮动栅极与控制栅极之间的第二高k电介质(举例而言，k>5)。
附图说明
本发明可搭配附图参照以下说明来了解，其中相似的参考组件符号表示相似的组件，并且其中：
图1图根据本发明的一实施例展示闪存胞；以及
图2a至2l绘示用于制造与图1所示类似的闪存胞的例示性程序流程。
尽管本文所揭示的专利目标易受各种修改和替代形式所影响，其特定具体实施例仍已通过图式中的实施例予以表示并且在本文中予以详述。然而，应了解的是，本文中特定具体实施例的说明用意不在于将本发明限制于所揭示的特定形式，相反地，如随附权利要求书所界定，用意在于涵盖落于本发明的精神及范畴内的所有修改、均等例、及替代方案。
具体实施方式
下面说明本发明的各项说明性具体实施例。为了澄清，本说明书中并未说明实际实作态样的所有特征。当然，将会领会的是，在开发任何此实际具体实施例时，必须做出许多实作态样特定决策才能达到开发者的特定目的，例如符合系统有关及业务有关的限制条件，这些限制条件会随实作态样不同而变。此外，将了解的是，此一开发努力可能复杂且耗时，虽然如此，仍会是受益于本发明的所属领域技术人员的例行工作。
以下具体实施例经充分详述而使所属领域技术人员能够利用本发明。要理解的是，其它具体实施例基于本发明将显而易见，并且可施作系统、结构、程序或机械变更而不脱离本发明的范畴。在以下说明中，提出特定数值细节是为了得以透彻理解本发明。然而，将显而易见的是，本发明的具体实施例无需此等特定细节也可予以实践。为了避免混淆本发明，并且详细揭示一些众所周知的电路、系统配置、结构组态以及程序步骤。
本发明现将参照附图来说明。各种结构、系统及装置在图式中只是为了阐释而绘示，为的是不要因所属领域技术人员众所周知的细节而混淆本发明。虽然如此，仍将附图包括进来以说明并阐释本发明的说明性实施例。本文中使用的字组及词组应了解并诠释为与所属领域技术人员了解的字组及词组具有一致的意义。与所属领域技术人员了解的通常或惯用意义不同的词汇或词组(即定义)的特殊定义，用意不在于通过本文词汇或词组的一致性用法提供暗示。就一词汇或词组用意在于具有特殊意义的方面来说，即有别于所属领域技术人员了解的意义，此一特殊定义应会按照为此词汇或词组直接且不含糊地提供此特殊定义的定义方式，在本说明书中明确提出。举例而言，所属领域技术人员在完整阅读本发明之后将了解的是，措辞“B上方的A”并不受限于理解A直接布置于B上，亦即，A与B实体接触。
空间参考“顶端”、“底端”、“上”、“下”、“垂直”、“水平”及类似者于本文中使用时，若涉及FinFET的结构，可为求便利性而使用。这些参考的用意在于仅为了教示目的而以与图式一致的方式加以使用，而且用意不在于当作FinFET结构的绝对参考。举例而言，FinFET可按照与图式所示方位不同的任何方式予以空间定向。提及图式时，“垂直”用于指称为正交于半导体层表面的方向，而“水平”用于指称为平行于半导体层表面的方向。“上”用于指称为远离半导体层的垂直方向。安置于另一组件“上面”(“下面”)的一组件相较于该另一组件，位于较远离(较靠近)半导体层表面处。
如所属领域技术人员完整阅读本申请书后将轻易了解的是，本方法适用于例如NMOS、PMOS、CMOS等各种技术，并且轻易地适用于各种装置，包括但不限于逻辑电路、存储装置、以及尤其是闪存胞。可在CMOS制造程序中整合此等制造技巧。本文中所述的技巧与技术可用于制作MOS集成电路装置，包括NMOS集成电路装置、PMOS集成电路装置、以及CMOS集成电路装置。尤其是，本文中所述的程序步骤搭配形成集成电路用栅极结构的任何半导体装置制作程序来利用，此等集成电路包括平面型及非平面型这两种集成电路。虽然用语“MOS”适当地系指具有金属栅极电极及氧化物栅极绝缘体的装置，该用语全文用于意指包括传导栅极电极(金属或其它传导材料都可以)的任何半导体装置，该传导栅极电极置于栅极绝缘体(氧化物或其它绝缘体都可以)上方，进而置于半导体主体基材上方。
本发明大体上提供用于制造FinFET装置的程序流程中整合而成的存储胞用的制造技巧。尤其是，提供一种非挥发性闪存胞，其包含单面快闪栅极，并且整合于全空乏FinFET装置中。可提供NAND或NOR闪存胞架构。在NOR架构的内部电路组态中，诸个别存储胞以并联方式连接，使装置能够达到随机存取的目的。此组态实现微处理器指令随机存取所需的短读取时间。NOR闪存架构是低密度、高速读取应用的理想选择，这类应用大部分仅进行读取，通常称为符码储存应用。另一方面，开发NAND闪存架构作为高密度数据储存的替代优化选择，放弃随机存取能力来换取更小的胞元尺寸，使得芯片尺寸更小且每个位的成本更低。这是通过建立以串联方式连接的多个内存晶体管所构成的数组来达成。
在所提供的闪存胞中，可在半导体鳍片的一侧提供控制/编程设计栅极与浮动栅极，并且可在半导体鳍片的另一侧提供感测栅极(快闪栅极)。可形成与半导体鳍片中所形成的沟道区较为接近的感测栅极。高k电介质可用于将半导体鳍片与感测栅极隔离，并且将浮动栅极与控制栅极隔离。可在半导体鳍片与浮动栅极之间形成穿隧氧化物。存储胞的程序设计可基于对控制栅极施加的高电压所造成的热载子注射来实现，而抹除可通过使电荷载子穿过高k电介质穿隧至控制栅极来实现。可就本文中所揭示的闪存胞分别达到通过充电或放电而使临限电压可控制并有效推移。事实上，浮动栅极的累积电荷可显著影响半导体鳍片的功函数，由此充电/控制临限电压。
图1根据本发明的一实施例，展示可用于NAND架构中的单一闪存胞100。闪存胞100可以是晶圆上所形成的存储胞数组的部分。可在相同的晶圆上形成其它主动及被动半导体装置。存储胞100及存储胞数组可以是集成电路的部分。
闪存胞100包含半导体层101。半导体层101可由任何适当的半导体材料所构成，诸如硅、硅/锗、硅/碳、其它II-VI族或III-V族半导体化合物及类似者。半导体层101可以是主体半导体基材的部分，其中可形成绝缘区域，例如浅沟槽绝缘物。主体半导体基材可以是硅基材，尤其是单晶硅基材。可使用其它材料来形成半导体材料，举例如锗、硅锗、磷酸镓、砷化镓等。绝缘区域可界定主动区，并且将闪存胞与相同基材上所形成的其它主动或被动装置电隔离。绝缘区域可以是相连沟槽隔离结构的部分，并且可通过蚀刻主体半导体基材并以例如硅的一些介电材料填充所形成的沟槽来形成。原则上，半导体层101可包含于SOI晶圆中。在这种情况下，半导体层101是在主体半导体基材上所形成的绝缘/埋置型氧化物层上形成。举例而言，埋置型氧化物层可包括诸如二氧化硅的介电材料，并且可以是所具厚度范围自约10nm至20nm的超薄埋置型氧化物(UT-BOX)。
半导体鳍片102是在半导体层101上形成。图1中所示的半导体鳍片102可以是半导体层101上所形成的多个半导体鳍片其中一者。半导体鳍片102可通过蚀刻或磊晶生长而由半导体层101来形成。半导体鳍片102可通过任何合适的微影程序组合来形成，其可涉及形成图型及选择性蚀刻材料。举例而言，半导体鳍片102可使用双图型化程序来形成，例如阻剂上置阻剂图型化技巧(其可包括微影-蚀刻-微影-蚀刻(LELE)程序或微影-冻结-微影-蚀刻(LFLE)程序)。在其它具体实施例中，鳍片可使用干涉微影、压模微影、光微影、极紫外线(EUV)微影、或x射线微影来形成。多个半导体鳍片可沿着半导体层101的表面顺着长度方向平行延伸，并且顺着与半导体层101的表面垂直的高度方向延展。
半导体鳍片102可具有小于50nm的窄宽度。氧化物层(图未示)可在半导体层101上形成，在这种情况下，鳍片穿过氧化物层连至半导体层101。应领会的是，半导体鳍片102可呈现适当的掺质浓度，以便界定对应的漏极与源极区。另外，待形成FinFET装置的沟道区可通过适度掺杂半导体鳍片102的各别区域来形成。在替代实施例中，沟道区可能维持未掺杂。
绝缘层103是在半导体层101的曝露表面上、半导体鳍片102的侧壁上、以及半导体鳍片102的顶端上形成。绝缘层103可包含例如二氧化硅的氧化物材料或由其所制成。存储胞100中包含三个栅极，即感测栅极110、浮动栅极120及控制栅极130。绝缘层103作用为用于浮动栅极120的穿隧氧化物。可在感测栅极110与半导体鳍片102之间形成所具介电常数k大于5的高k介电材料以形成感测栅极电介质115，并且可在控制栅极130与浮动栅极120之间形成所具介电常数k大于5的高k介电材料以形成控制栅极电介质135。高k介电材料可包含诸如氧化铪、二氧化铪及氮氧化铪硅其中至少一者的过渡金属氧化物。相同或不同的材料可用于形成感测栅极电介质115及控制栅极电介质135。浮动栅极120必须通过电气绝缘材料来完全围绕。举例而言，绝缘层103的薄型部分可包覆浮动栅极120的顶端表面及半导体鳍片102的顶端表面。
感测栅极110及控制栅极130可包含功函数调整层。功函数调整层可包含氮化钛或所属技术领域已知的任何其它适当的功函数调整金属或金属氧化物。感测栅极110、浮动栅极120及控制栅极130可包含多晶硅。感测栅极110、浮动栅极120及控制栅极130各可包含金属栅极。金属栅极的材料可取决于待形成晶体管装置属于P沟道晶体管还是N沟道晶体管。在晶体管装置为N沟道晶体管的具体实施例中，此金属可包括La、LaN或TiN。在晶体管装置为P沟道晶体管的具体实施例中，此金属可包括Al、AlN或TiN。
如图1所示，可在半导体鳍片102、感测栅极110、浮动栅极120及控制栅极130上方形成层间电介质150。浮动栅极120可通过层间电介质150、绝缘层103及控制栅极电介质135来绝缘。层间电介质150可包含例如二氧化硅的氧化物材料或由其所制成。层间电介质150中形成用于电接触感测栅极110与控制栅极130的接触部160。包含导电结构170的第一金属化层可在层间电介质150上方形成并与接触部160电气及机械接触。传导结构170与接触部160可包含金属，例如铜或铝。
在下文中，参照图2a至2l说明用于制造类似于图1所示半导体装置的例示性程序流程。在这些图中，若有提供的话，顶列展示俯视图，而底列分别沿着此等图式的俯视图中所示A-A及B-B线条展示截面图。左栏分别展示晶圆形成诸如FinFET装置等主动装置处的逻辑区，而右栏分别展示晶圆形成存储胞处的存储区。含大写L的参考组件符号指逻辑区，而含大写M的参考组件符号指存储区。逻辑区与存储区可通过绝缘区域彼此分开。然而，在图中，逻辑区与存储区展示为彼此分开。
在图2a所示的制造阶段中，举例而言，提供的是包含硅的半导体基材201L、201M。半导体基材201L、201M可以是主体半导体基底或上覆半导体绝缘体(SOI)基材，如以上所述。掩膜层202L、202M是在半导体基材201L、201M上方形成。掩膜层202L、202M可包含例如氮化硅的氮化物材料，或由其所组成。半导体基材201L、201M举例而言，可包含掺杂区，用于提供FinFET装置的沟道区。
通过包含沉积并图型化光阻(图未示)的标准微影技巧，将掩膜层202L、202M图型化并将其当作蚀刻掩膜用于蚀刻半导体基材201L、201M(若提供SOI半导体基材，则将埋置型绝缘层上形成的半导体层蚀刻)，如图2b所示。通过蚀刻程序，分别在逻辑区及存储区中形成半导体鳍片203L、203M。在相同的蚀刻程序中，可在视为适当的情况下形成浅沟槽隔离。蚀刻程序可包含反应性离子蚀刻或化学湿蚀刻，并且可在之后进行化学机械研磨。图2b中的虚圆表示可形成源极/漏极着落垫的区域，如所属技术领域中已知者。
在图2c所示的制造阶段中，例如包含二氧化硅的氧化物层204L、204M是在半导体基材201L、201M及半导体鳍片203L、203M上形成。在所示实施例中，在为了形成氧化物层204L、204M而进行的氧化程序期间维持掩膜层202L、202M。在氧化程序之后，于产生的结构上方沉积多晶硅层205L、205M。在沉积多晶硅层205L、205M期间，剩余掩膜层202L、202M的侧表面及/或顶端表面上可以或可不存在氧化物层204L、204M的一部分。为了形成存储胞的浮动栅极而在存储区中形成多晶硅层205M。逻辑区中必须完全移除多晶硅层205L，而存储区中必须图型化多晶硅层205M，以便形成浮动栅极。移除逻辑区中的多晶硅层205L及图型化存储区中的多晶硅层205M，举例而言，可通过在两区域中适当地植入多晶硅层205L、205M来达成。图2d中绘示适当的倾斜布植程序。
倾斜布植套装程序含第一布植阶段I1、第二布植阶段I2以及第三布植阶段I3。在各该阶段I1、I2及I3中，可使用相同的植入物种。植入物种举例而言，可包含氮。在第一布植阶段I1期间，进行自垂直于半导体基材201L、202M的顶端起的布植。在第二布植阶段I2期间，进行左起的布植(左倾斜布植)。进行第一布植I1与第二布植I2的顺序可反过来。
第三布植I3是右起的布植(右倾斜布植)，在进行之前，先在存储区中的多晶硅层205M上方形成结构化掩膜层206，如图2d所示。结构化掩膜层206保护多晶硅层205M位于存储区的部分，此等部分是在存储区中特定半导体鳍片203M的右表面上方形成，此等右表面通过结构化掩膜层206掩蔽而不在第三布植阶段I3期间布植。在图2d中，受掩蔽半导体鳍片以参考组件符号203Ma表示，而未受结构化掩膜层206掩蔽的半导体鳍片以参考组件符号203Mb表示。举例而言，可交替地配置受掩蔽半导体鳍片203Ma及未受掩蔽半导体鳍片203Mb。
这三个布植阶段I1、I2及I3完成之后，多晶硅层205L、205M的布植部分举例而言，可通过对未掺杂多晶硅具有选择性的湿化学蚀刻程序来移除。图2e展示产生的结构。逻辑区中的多晶硅层205L遭受完全地移除。在存储区中，存储区中受结构化掩膜层206掩蔽的特定半导体鳍片203Ma的右表面上形成的多晶硅层205M位于存储区中的部分得以维持，并且将会形成最终制造的存储胞的浮动栅极207。
移除多晶硅层205L、205M的布植部分之后，在此结构上方形成氧化物层208L、208M，如图2f所示。此氧化物材料通过化学机械研磨来沉积并且平坦化。在平坦化期间，可完全移除掩膜层202L、202M在半导体鳍片203的顶端上的剩余部分。若考虑适当的话，可在逻辑区中维持半导体鳍片203L上的薄层型掩膜层202L。在存储区中，可形成包含浮动栅极207并且通过隔离鳍片203Mb(无相邻浮动栅极的半导体鳍片)彼此分开的存储胞。
在图2g所示的制造阶段中，使考虑的逻辑与存储区凹陷。可沉积适当图型化的蚀刻掩膜，并且可进行单步骤或多步骤蚀刻程序。如图2g所示，在逻辑区中对氧化物层208L的氧化物材料、及半导体鳍片203L与半导体基材201L的半导体材料进行非选择性蚀刻。如与图2f所示结构相比较，逻辑区中所产生结构的凹陷程度可约为35nm至45nm，例如40nm，亦即，半导体鳍片203L及氧化物层208L两者的顶端表面的高度位准得以缩减。另一方面，存储区中进行的蚀刻程序对半导体鳍片203M及浮动栅极207的材料具有选择性。如与图2f所示结构相比较，存储区中氧化物层208M的所产生表面的凹陷程度可约为15nm至25nm，例如20nm。存储区中的浮动栅极207及半导体鳍片203M的顶端表面的高度位准在完成蚀刻程序之后，高于逻辑区中半导体鳍片203L的顶端表面的高度位准。存储区中氧化物层208M的曝露表面的高度位准在完成蚀刻程序之后，高于逻辑区中氧化物层208L的高度位准。逻辑区中半导体鳍片203L的高度(垂直延展部)可低于存储区中半导体鳍片203M(或203Ma与203Mb)的高度。
在图2h所示的制造阶段中，保护层209L、209M是在图2g所示的结构上方形成。保护层209L、209M可包含氮化物材料，并且在以较晚阶段(请参阅下文所述)的所述例示性取代栅极方法为背景而移除牺牲栅极期间，用于保护底层半导体鳍片203L、203M及浮动栅极207。注意到的是，若考虑适当的话，可进行用于形成光晕区等的各个布植步骤，并且可沉积栅极氧化物层。例如包含多晶硅或由其所组成的牺牲电极层210L、210M是在逻辑与存储区中形成，并且通过例如包含氮化物材料的结构化蚀刻掩膜211L、211M来图型化，如图2h所示。接着可形成间隔物并且布植源极/漏极区。
氧化物层212L、212M是在图2h所示的结构上方形成，并且举例而言，通过化学机械研磨来回向研磨至蚀刻掩膜211L、211M，而且之后，将蚀刻掩膜211L、211M移除，以便获得图2i所示的结构。蚀刻掩膜211L、211M可通过干蚀刻或通过研磨来移除。
在图2j所示的制造阶段中，牺牲电极层210L、210M，举例而言，通过化学湿蚀刻来移除，然后使氧化物层208L、208M凹陷至低于半导体鳍片203L、203M(203Ma、203Mb)其中一者的高度位准。对氧化物层212L、212M选择性地蚀刻牺牲电极层210L、210M。保护层209L、209M在移除牺牲电极层210L、210M期间且可能在氧化物层208L、208M中的凹口形成期间保护半导体鳍片203L、203M的顶端表面，而且随后遭受移除。
如图2k所示，在移除牺牲电极层210L、210M之后，于氧化物层208L、208M中形成凹口，并且于凹口中形成高k介电层213L、213M。凹口中的高k介电层213L、213M上方填充栅极电极层214L、214M，举例而言，包含金属或由其所组成，例如钨或铝。半导体鳍片203L、203M的表面上方可另外形成功函数调整材料。填入凹口之后，栅极电极层214L、214M，举例而言，通过化学机械研磨来平坦化至氧化物层212L、212M的高度位准。在存储区中，平坦化程序导致形成感测栅极215、以及与感测栅极215分开的控制栅极216。如与存储区作比较(对照图2g的描述)，栅极电极214L因逻辑区中半导体鳍片203L的高度缩减而得以在平坦化期间维持不变。在逻辑区中，产生包含至少两个半导体鳍片203L的FinFET装置，而在存储区中，形成多个闪存胞，图2k的底列中绘示这两者。个别闪存胞通过绝缘半导体鳍片203Mb来彼此分开。
图2l展示图2k的结构在形成接触部221L、221Ma、221Mb、并且形成第一金属化层的金属线222L之后的情况。在形成接触部221L、221Ma、221Mb之前，可先进行硅化程序以降低介于此等接触部与逻辑区中所形成FinFET装置、及存储区中所形成存储胞的诸电极之间的接触电阻。半导体鳍片103L、103M至少有部分(即包含源极/漏极区的部分)可遭受硅化。产生的金属硅化物可由举例如硅化镍、镍铂硅化物、硅化钴等各种不同材料所构成，并且此类金属硅化物区的厚度可随特定应用而变。为形成金属硅化物区而进行的典型步骤涉及沉积一层耐火金属，进行造成耐火金属与下层半导体材料(例如含硅材料)起反应的初始加热程序，进行用以将耐火金属层未反应部分移除的蚀刻程序，以及进行用以形成金属硅化物最终相的另外的加热程序。
如图2l所示，在逻辑区中，金属线222L经由接触部221L连接至FinFET装置的源极/漏极区。在存储区中，金属线经由接触部221Ma连接至感测栅极，其它金属线经由接触部221Mb连接至控制栅极。
一般来说，注意到的是，个别半导体鳍片203的漏极及/或源极区可通过层间电介质中所形成经适当设计的接触结构来个别接触，以便将半导体鳍片的各该对应的漏极及/源极区与可控制互连结构连接，其可组配成能够(至少一次)控制末端部分与共享节点的连接，诸如晶体管的漏极端或源极端。在一些说明性态样中，可控制互连结构可包含举例来说，相较于尖端FinFET装置以更少关键限制条件为基础所形成的晶体管组件，由此提供反复重新组配尖端晶体管组件的可能性。可控制互连结构可包含诸如电阻性结构的导体及类似者，其可从低阻抗状态切换到高阻抗状态至少一次，以便能够将对应的半导体鳍片与共享电路节点拆接。举例而言，可控制互连结构可连接至外部测试设备，以便根据所思特定晶体管的要求，适当地设定晶体管组态，例如电流驱动能力，而在其它实例中，可条件性判定所思晶体管的实际功能状态，并且可基于侦检到的功能状态，进行互连结构的对应控制。
如所属领域技术人员将会轻易领会的是，虽然以上就NAND闪存胞作说明，仍可依照类似方式就NOR架构进行制造与FinFET装置整合的存储胞的程序流程，其中需要另外的着落垫(landing pads)。
结果是，本文中提供设有单面感测栅极(快闪栅极)的非挥发性闪存胞，其可包括于FinFET装置中，举例而言，包括于全空乏FinFET装置中。存储胞的制造程序可完全整合在用于形成FinFET装置的程序流程中。
以上所揭示的特定具体实施例仅属描述性，正如本发明可用所属领域技术人员所明显知道的不同但均等方式予以修改并且实践而具有本文教示的效益。举例而言，以上所提出的程序步骤可按照不同顺序来进行。再者，如上面权利要求书中所述除外，未意图限制于本文所示构造或设计的细节。因此，证实可改变或修改以上揭示的特定具体实施例，而且所有此类变例全都视为在本发明的范畴及精神内。要注意的是，本说明书及所附权利要求书中如“第一”、“第二”、“第三”或“第四”等类用以说明各个程序或结构的术语，仅当作此些步骤/结构节略参考，并且不必然暗喻此些步骤/结构的进行/形成序列。当然，取决于精准的要求语言，可以或可不需要此类程序的排定顺序。因此，本文寻求的保护系如以上权利要求书中所提。

Claims (19)

1.一种制造半导体装置的方法，其包含：
提供半导体基材；
在该半导体基材的逻辑区中形成第一多个半导体鳍片；
在该半导体基材的存储区中形成第二多个半导体鳍片；
在该第一多个半导体鳍片的所述鳍片之间、及该第二多个半导体鳍片的所述鳍片之间形成绝缘层；
在所述第一与第二多个半导体鳍片及该绝缘层上方形成电极层；
由该电极层本身形成栅极于该逻辑区中的该第一多个半导体鳍片的半导体鳍片上方；以及
由该电极层本身形成感测栅极及控制栅极于该存储区中的该第二多个半导体鳍片的半导体鳍片之间。
2.如权利要求1所述的方法，还包含在该存储区中的该绝缘层中形成凹口，并且其中，所述感测栅极与浮动栅极是在该绝缘层中所形成的所述凹口中形成。
3.如权利要求1所述的方法，还包含在该逻辑区中的所述栅极与所述半导体鳍片之间、及该存储区中的所述感测栅极与所述半导体鳍片之间形成高k介电层。
4.如权利要求1所述的方法，还包含在该存储区中的所述控制栅极与所述半导体鳍片之间形成浮动栅极。
5.如权利要求1所述的方法，还包含在所述逻辑与存储区中的所述第一与第二多个半导体鳍片与该绝缘层上方形成牺牲栅极层，并且在形成该电极层之前先移除该牺牲栅极层。
6.如权利要求1所述的方法，其中，形成所述感测栅极与所述控制栅极包含将该存储区中的该电极层向下研磨至该第二多个半导体鳍片的所述半导体鳍片的顶端表面的位准。
7.一种形成半导体装置的方法，其包含在晶圆的逻辑区中形成FinFET装置，并且在该晶圆的存储区中形成闪存胞，其包含：
在该逻辑区中形成具有第一高度的第一半导体鳍片；
在该存储区中形成具有大于该第一高度的第二高度的第二半导体鳍片；
在所述第一与第二半导体鳍片上方形成电极层；
由该电极层本身形成该FinFET装置的栅极于所述第一半导体鳍片上方；以及
由该电极层本身形成该闪存胞的感测栅极与所述第二半导体鳍片的半导体鳍片的第一侧壁邻近，并且由该电极层本身形成该闪存胞的控制栅极与所述第二半导体鳍片的该半导体鳍片的第二侧壁邻近。
8.如权利要求7所述的方法，还包含：
以比该第一高度更低的第三高度在所述第一半导体鳍片之间、及以比该第一高度更大，与该第二高度实质相等的第四高度在所述第二半导体鳍片之间形成氧化物层；以及其中
该FinFET装置的该栅极是在该逻辑区中的该氧化物层上部分形成，而该闪存胞的该感测栅极与该控制栅极是在该存储区里的该氧化物层中所形成的凹口中形成。
9.如权利要求7所述的方法，还包含：
在形成该FinFET装置的该栅极、及该闪存胞的所述感测与控制栅极之前，先在所述第一与第二半导体鳍片的顶端表面与侧表面上方形成半导体层；
将该半导体层从所述第一与第二半导体鳍片的所述顶端表面、并且自所述第一半导体鳍片的所述侧表面移除；以及
在该存储区中自该半导体层起形成该闪存胞的浮动栅极。
10.如权利要求7所述的方法，还包含在该FinFET装置的该栅极的侧表面、及该控制栅极的侧表面上形成高k介电层。
11.如权利要求7所述的方法，还包含在形成该电极层之前，先在所述第一与第二半导体鳍片上方形成牺牲电极层、图型化该牺牲电极层以在所述第一与第二半导体鳍片上方形成取代栅极、在所述取代栅极之间形成绝缘层、以及移除所述取代栅极。
12.一种制造闪存胞的方法，其包含：
在半导体基材上形成多个半导体鳍片；
为该多个半导体鳍片的子集形成浮动栅极；
在该多个半导体鳍片之间形成第一绝缘层；
使该第一绝缘层凹陷至比该多个半导体鳍片的高度更小的高度；
在该多个半导体鳍片的该子集上方形成牺牲栅极；
在所述牺牲栅极之间形成第二绝缘层；
移除所述牺牲栅极；
在该第一绝缘层中形成凹口；以及
为该多个半导体鳍片的该子集在所述凹口中形成感测栅极与控制栅极。
13.如权利要求12所述的方法，其中，所述感测栅极与所述控制栅极是通过下列步骤来形成：在所述凹口中、该多个半导体鳍片的该子集上方、及该第二绝缘层上方形成栅极层、以及将因此形成的该栅极层回向研磨至该多个半导体鳍片的该子集的高度位准。
14.如权利要求12所述的方法，还包含在所述感测栅极与该多个半导体鳍片的该子集之间形成高k电介质。
15.如权利要求12所述的方法，还包含在该多个半导体鳍片的该子集与所述控制栅极之间形成浮动栅极。
16.一种闪存胞，其包含：
半导体鳍片，形成于半导体基材上并包含第一侧壁与第二侧壁；
感测栅极，形成与该半导体鳍片的该第一侧壁邻近；
第一高k电介质，形成于该感测栅极与该半导体鳍片的该第一侧壁之间；
控制栅极，形成与该半导体鳍片的该第二侧壁邻近；
浮动栅极，配置于该控制栅极与该半导体鳍片的该第二侧壁之间；以及
第二高k电介质，形成于该浮动栅极与该控制栅极之间，
其中，与该半导体鳍片的该第一侧壁与该第二侧壁邻近的凹口中形成电极层，由该电极层本身形成该感测栅极及该控制栅极。
17.如权利要求16所述的闪存胞，其中，该半导体鳍片的、该感测栅极的、该浮动栅极的、及该控制栅极的顶端表面彼此实质齐平。
18.一种具有存储区与逻辑区的半导体装置，其中，该存储区包含如权利要求16所述的闪存胞，而该逻辑区包含FinFET装置，其中：
该FinFET装置包含：
半导体鳍片，包含该FinFET装置的沟道区、并且由与该闪存胞的该半导体鳍片相同的材料所制成；以及
栅极电极，由与该闪存胞的该感测栅极与该控制栅极相同的材料所制成，其中，于该半导体鳍片上方形成该电极层，并且由该电极层本身形成该栅极电极。
19.如权利要求18所述的半导体装置，其中，该FinFET装置的该半导体鳍片的高度低于该闪存胞的该半导体鳍片的高度。
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