TWI357112B - Etched nanofin transistors - Google Patents

Description

1357112 IX. DESCRIPTION OF THE INVENTION: TECHNICAL FIELD OF THE INVENTION The present disclosure relates generally to abundance conductor elements and, more particularly, to nano fin fin transistors. [Prior Art]

The semiconductor industry has a need to reduce component size, such as transistors, and to increase the market orientation of component density on substrates. Some product targets include reduced power consumption, higher performance, and smaller size. Figure 1 shows the general trends and relationships of various component parameters with a factor k as the adjustment factor. The continual shrinking of MOSFET technology to deep sub-micron ranges with channel lengths below 〇丨 micron (1 〇〇 nano or 1000 angstroms) poses a significant problem for conventional transistor structures. For example, the junction depth should be much smaller than the channel length. Therefore, referring to the transistor 100 shown in Fig. 1, the channel depth 101 should be on the order of hundreds of angstroms in terms of the channel length 1 〇 2 of about 1000 angstroms long. Such a shallow connection r

The surface is difficult to form using conventional implantation and diffusion techniques. Very high levels of channel doping are required to suppress short channel effects such as drain induced barrier lowering, critical voltage roll off, and subcritical conduction. Leakage current is an important issue in low voltage and CMOS circuits and systems operating on lower power batteries, especially in DRAM circuits. The threshold voltage is small to connect to significant overdrive and reasonable switching speeds. However, as shown in Figure 2, a small threshold voltage results in a relatively large secondary critical leakage current. 5 1357112

Some of the designs proposed for this problem use a transistor with an ultra-thin body or a transistor whose surface space charge region increases as other transistors shrink in size. A dual-gate or double-gate transistor structure has also been proposed to reduce the transistor. For example, in the industry, "double gate, refers to a transistor with a front gate and a back gate, which can be separated and independent of voltage vines" and "two gates," meaning that the two gates are the same The structure that is driven at the potential. An example of a two-gate element structure is a fin FET. A "three closed pole" structure and a surrounding gate structure have been proposed. In a "three-gate," structure, the gate is located on three sides of the channel. In a surrounding gate structure, the gate surrounds or surrounds the transistor channel. The surrounding gate structure provides access to the transistor channel Expected control, but it is actually difficult to implement the structure.

Figure 3 shows a double gate MOSFET having a drain, a source, and a gate before and after isolating the semiconductor body with a gate insulating layer, and also showing the electric field generated by the pole. Some of the characteristics of the dual gate and/or two gate MOSFETs are better than conventional bulk MOSFETs because they are better shielded from the source terminal of the channel than the single gate. The electric field produced. The surrounding gate further shields the electric field generated by the drain electrode from the source. Therefore, the sub-critical leakage current characteristics are improved because the sub-critical current decreases more rapidly when the gate voltage is lowered when the double-gate and/or two-gate MOSFETs are turned off. Figure 4 generally shows the improved subcritical characteristics of the dual gate, the two gates, or the surrounding gate MOSFET compared to the subcritical characteristics of conventional bulk MOSFETs. 5A-C illustrate a conventional fin FET. Figure 5A shows a top view of the fin FET, and Figure 5B shows the fin FET along line 5B-5B of 6 504 '1357112

End view. The fin FET 503 is shown to include a first source/drain region second source/drain region 5 0 5 and a fin 5 5 6 extending between the first and second source drain regions . The scorpion fin acts as an electro-crystal, wherein the channel between the first and second source/drain regions is . A gate insulating layer 507, such as hafnium oxide, is formed on the fin, and a gate 508 is formed on the fin on the oxide layer. The fins of the conventional fin FET are shown formed on the buried oxide 509. Figure 5C shows an etching technique used to fabricate the fins of a fin FET. As shown in Figure 5C, the width of the fin is defined by microelectron beam lithography and etching. Therefore, the width of the fin is initially small (1 F). The width of the fin is then reduced by oxidation or etching, as indicated by arrow 510. [Summary of the Invention] Sidewall spacer technology to etch ultra-thin fins into the wafer and utilize these etched nano-fins to have a nano-fin-like transistor surrounding the gate. Several embodiments etch the nano-fin in a crucible The zinc nano-fins are used in the body region of a CMOS transistor, where both the thickness and the passivity of the transistor body have a size smaller than the lithography size. For example, certain embodiments are thick. An ultra-thin nanofin of the order of 20 nm to 50 nm. One of the objects of the subject matter relates to a method of forming a crystal. According to an 'embodiment, a fin is formed from a crystalline substrate. Forming a first source/drain region under the fin of the substrate. The surface of the fin/body main horizontal post-forming layer or the most nano-made substrate Provided as a method for the road leader. The inside should form 7 1357112 a surrounding gate insulation Forming a surrounding gate around the Korean material, a second source/3⁄4 pole region is formed in the top of the fin-shaped insulating layer by the surrounding gate insulating layer, and a hole is etched in one of the upper layers, Forming a fin pattern in the hole to form a fin pattern, and using a corresponding mask to enter the crystal substrate to be related to a transistor from the basic point of view. A transistor crystal substrate Having a trench etched therein to form a bottom of the fin from the semiconductor fin; a first source/drain region; and a second source/drain region, top to a first and a second source/a vertical channel region in the fin. The transistor also includes a surrounding gate, the gate insulating layer being formed on the fin-shaped pole formed on the fin Surrounded and insulated by the gate. The fin has a name less than a minimum feature size and other views, embodiments, advantages, and descriptions of the subject matter and the sturdy squat and reference pattern And become more obvious I? [Embodiment] The following detailed description of the system The accompanying drawings, which are set forth herein, are in the <Desc/Clms Page number>> </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; Other solid surround gates are used, and the object is isolated. The fin embodiment is formed in the substrate wall spacer from which the fin is formed. Embodiments include: forming a crystal on a substrate Forming a gate insulating layer between the finned bungee regions and surrounding the crystal substrate, the surrounding gate layer and the fin are separated by 4 faces. Features can be seen from the rear to the i. The details of the present invention are shown to describe the matter. The viewpoint of the embodiment of the subject matter can be exemplified and can be used at 8 1357112.

Structural, logical, and electrical changes are made from the scope of the subject matter. In the following description, the terms "wafer" and "substrate" are used interchangeably and generally refer to any structure on which an integrated circuit is formed, and also refers to such a phase during the various stages of bulk circuit fabrication. Structure. Both terms include hetero and undoped semiconductors, semiconductor epitaxial layers on a supporting semiconductor or insulating material, combinations of such layers, and other types of structures known in the art. The term "horizontal" is defined as a plane parallel to the known plane or surface of the wafer substrate, regardless of the orientation of the wafer or substrate. The term “vertical” refers to the direction perpendicular to the horizontal definition defined above. Prepositions such as "upper", "side", "higher", "lower", "square" and "lower" are defined in relation to conventional planes or faces on the upper surface of a wafer or substrate. What is the orientation of the wafer or substrate. However, the following detailed description is not to be considered as limiting, and the scope of the invention is limited only by the scope of the appended claims and the scope of the equivalents Disclosed herein are nano fin transistors, and a fabrication technique in which nano fins are etched into a substrate or wafer and used to make single crystal nano fin transistors. Examples of nano-fins. It will be appreciated by those skilled in the art that after reading and understanding the present disclosure, other semiconductors are used to form nano-fins. The subject matter of this subject provides a nano-fin-shaped transistor with vertical channels, wherein Having a first source/deuterium region at the bottom of the fin and a second source/drain region at the fin portion. Figures 6A-6L illustrate a process for forming a nanofin-shaped transistor, according to the target Several embodiments of the object. The square table of this or the like is such as Zhongda Zhihe, the top of the book 9 1357112 in a dream wafer ± deposited nitride #, and covered with a layer of amorphous (a-silicon) tantalum nitride. Figure 6A shows The amorphous germanium defines a side view of the hole 612 and forms a structure 6ΐ after the sidewall spacer 614. The holes 612 extend to the tantalum nitride 615, which is located, for example, on the substrate 616 of the dream wafer. The embodiment forms the sidewall spacer by oxidizing the amorphous dream. Figure 6B shows a side view of the structure 61 i after covering the structure with a thick layer of amorphous germanium 616. Figure 6c shows at least Flattening, shown by arrows, to the structure 611 after removal of the oxide on the amorphous germanium. A chemical mechanical polishing (CMP) process can be used to planarize the structure. This leaves oxidation. An elongated rectangular pattern of objects 614, also referred to as a "racetrack" pattern, is exposed on the surface. The width of the lines of the pattern is determined by the thickness of the oxide, rather than the reticle and lithography, for example, the thickness of the oxide. Available in 2 nanometers to In the range of 50 nanometers, according to several embodiments. Figure 6D shows the runway pattern selectively covering one 氧化物$ oxide and exposing other portions of the oxide. Removing the exposed oxide portion, Electrically shown. An etching process, such as a potassium hydroxide (KOH), is performed to remove the amorphous dream. The oxide, or the mask shown in Fig. 6D, and the remaining oxidation after the last name a portion of the material that protects the nitride during etching. After removing the amorphous germanium, the nitride 6 15 can be etched, and then directional silver etching is performed, which etches the wafer 6 16 to below the nitride Scheduled depth. The vapor pattern protects the localized regions from etch, resulting in a dream fin 617 that protrudes from the lower surface of the wafer. As shown in Figure 6E. 6F and 10 1357112 Γ::: The top view and the view of the structure are doped with the fins.乂 and after the grooves at the bottom of the recordings. For example, Figure 6F = 2: The trap in the tank forms conduction · 618 (for example, the source line). The bottom or bottom portion of the Korean material forms a source/and a polar region. These: Shape: The material is quite thin. The dopant in the trench can completely diffuse below ^ -. The strips may be in a column or row direction. 2 B6ii illustrates the formation of a gate insulating layer 619 around the Korean 617, and the structure 611 after the gate material 620 is formed and separated by the gate. For example, the embodiment uses thermal oxidation of the fins. The gate material 620 can be polysilicon or metal &amp;&amp;&gt; according to several embodiments.

The top and side views along line 6J-6J of the first array embodiment are not shown separately from the 6J diagram. The structure 611 is backfilled with an insulating crucible 621 (e.g., oxide) and trenches are formed on the sides of the minerals. The pole winding material 622', such as polysilicon or metal, may be deposited and directionally etched to remain only in the sidewalls and in contact with the surrounding gates of the fins. The S gate material and the gate winding can be etched to make it concave below the top of the fins. The oxide can be backfilled again and planarized to leave only oxide on the surface. The contact opening and the drain doping region can then be etched to the top of the pillars and implanted into the drain region, and metal contacts are made to the drain regions by conventional techniques. In this example, the metal winding can extend along the "X direction" and the buried source winding can extend in a direction perpendicular to the plane of the drawing. The 6JC and 6L diagrams respectively show along the second array. The top view of the line 11 1357112 6L-6L of the embodiment and the structure, and the illustration, the backfilling of the insulating material 621 (e.g., oxide) "gate winding winding two directions" along the recordings 617 The groove is directional, such as polycrystalline hard or metal, which is deposited and in contact with each other. Can be two:: on the side wall and with the closing of the material and the gate winding wire '钭, so that it is concave and lower than the fins. Fill the entire structure, back with an insulating material (such as oxide)

Planar to leave only oxide on the surface. The opening and the liquid-doped regions can then be contacted to the pillars (4) and implanted into the non-polar regions, and metal contacts are made to the non-polar regions by conventional techniques. In this case, the metal winding may extend in a direction perpendicular to the plane of the drawing, and the buried source winding may extend in the "χ direction".

In the first and second array embodiments, the buried source/drain may be implanted prior to forming the surrounding gate insulating layer and surrounding the gate. Figure 6L shows one of the complete impurity structures having source, drain regions 623 and 624, recessed gate 62A, and source/drain region winding 618. These nano-recorded FETs can have a large aspect ratio and conduct more current than the nanowire feT. Figure 7 shows a top view of the layout of a nano-kun of a nano-bound transistor array, according to several embodiments. The figure shows two side wall spacers 714 "raceway" and further shows the side wall spacer portions removed by etching. The holes used to ritualize the sidewall spacers are in the smallest feature size (1F). The reticle strips 725 have a minimum feature size (if) width and are separated by a minimum feature size (1F). In the illustrated layout, the rows of the nano-buckles have a central-to-center spacing of approximately 2F, and the 12 1357112

The columns of nano-fin fins have a central to central spacing of approximately 1 F. In addition, as shown in FIG. 7, since the nano fins are formed on the sidewalls of the holes by sidewall spacers, the center-to-center between the first and second columns corresponds to the nano-fins. The amount of thickness of the article is slightly less than 1F (if-τ'), and the center-to-center spacing between the second and third columns will be slightly greater than 1F (1F+AT) corresponding to the thickness of the iso-nano fin. Generally, the center-to-center spacing between the first and second columns will be slightly less than the feature size interval (NF-ΔT) corresponding to the thickness of the nano-materials, and the center between the second and third columns. The amount of center-to-center spacing corresponding to the nano-pits is slightly greater than the feature size spacing (NF+ ΔT). 〆-

The distance Δ, the fin and the thick 9 fins &gt; in the polar touch contact configuration Figure 8 shows the process for fabricating a nano fin transistor, according to several embodiments of the present document. At 8 2, a fin is formed from the crystalline substrate. For example, the fins can be etched from the wafer. At 827, a first source/drain region is formed at the bottom of the substrate within the substrate. Because the fin is thin, the dopant can diffuse below the entire extent of the fin. At 828, a surrounding gate insulating layer is formed around the fins; and at 8 2 9, a ring gate is formed around the fins and is isolated therefrom by surrounding the gates. The structure formed by backfilling with insulating material at 830. The trench is engraved and adjacent to the surrounding gate to form and contact the gate line, as shown by 331. Some embodiments form two gate lines that are opposite sides of the surrounding gate. The gate lines may be oriented to contact the surrounding gates on the long sides of the nano fin junctions or may be oriented to contact the surrounding gates on the short sides of the nanofin structure. That is, the gate lines can be formed in a row or direction. At 832, 13 two source/drain contacts are formed on top of the fins. In Fig. 826, the layer 1 of the crystalline substrate is placed in the hole and the amorphous layer is adhered to the hole. Several implementations degenerate the structure with the first layer. Removing the amorphous sidewall oxide pattern, in the example, the thickness of the shape, which corresponds to the thickness in the second direction, and the a-silicon » % corresponds to several embodiments between the sidewalls The mask of the pattern is used for the substrate. The region, with the formation of a second source/drain region at 833, forms a fin from the crystalline substrate, such as the first embodiment, according to several embodiments of the subject matter. A layer is formed on 934, and at 935, the holes are etched or otherwise formed. In some embodiments, the crystalline amorphous germanium layer is formed with a tantalum nitride layer sandwiched between the crystalline substrates and a hole is etched into the tantalum nitride layer. At 936, sidewalls of the layer defining the periphery of the hole are formed with sidewall gaps. The amorphous germanium layer is oxidized to form the sidewall spacers. The material (a-silicon) backfills the hole, and at 937, the embodiment shown in Figures 6B and 6C, the flattening of the oxide on the upper surface, leaving a "runway, or rectangular pattern of spacers. 93. Forming fins from the sidewall spacers can be implemented by a reticle and an etch process. In some solid fin patterns, the first profile has a first profile at a minimum feature size, and A direction perpendicular to the second has a thickness of the second section corresponding to the sidewall of the oxide being less than the minimum feature size. At 939, the sidewall spacer of the lower fin pattern of the layer 3 is removed. The photomask of the object is etched to the crystalline substrate. The tantalum nitride layer is patterned into a fin, and then the tantalum nitride layer is etched to serve as the crystalline substrate, and the fin is removed at 94. The mask layer (e.g., tantalum nitride) is exposed to 14 1357112 to the top of the surname

Figure ί is a simplified block diagram of a high order organization of several embodiments of memory elements in accordance with several embodiments of the subject matter. The memory element 1042 is shown to include a memory array 1 〇 43 and a read/write control circuit 1044 for performing operations on the memory array through communication lines or channels 1 〇 45. The memory component 1042 shown may be a memory card or a memory module, such as a single inline memory module (SIMM) and a dual inline memory module (DIMM). ). Those skilled in the art will appreciate that after reading and understanding the present disclosure, the semiconductor fins of the memory array and/or control circuitry can be fabricated using the etched nanofuse transistors, as described above. The structure and manufacturing method of these components have been described above.

The memory array 1 043 includes some memory cells 1046. The memory cells in the array are arranged in columns and rows. In some embodiments, the word line 1〇47 connects the memory cells in the columns, and the bit line 1048 connects the memory cells in the rows. The read/write control circuit 1044 includes a word line selection circuit ι 49 (which functions to select a desired column), a bit line selection circuit 1050 (which functions to select a desired line), and a read circuit 105. 1 (which acts to detect the memory state of the memory cells in the selected memory array 1 043). Figure 11 shows a diagram of an electronic system 1152 having one or more nano-fin transistors. Several embodiments. The electronic system 52 includes a controller 1153, a busbar 1154, and an electronic component 1155, wherein the busbar 1154 provides a pass 15 1357112 channel between the controller 1153 and the electronic component 1155. In several embodiments, the controller and/or electronic component comprises a nanoflip transistor as described above. The illustrated electronic system 1152 can include, but is not limited to, information processing components, wireless systems, telecommunications systems, fiber optic systems, optoelectronic systems, and computers.

Figure 12 shows a diagram of an embodiment of a system 1256 having a controller 1257 and a memory 1 258. The controller and/or memory can include a nanoflip transistor in accordance with several embodiments. The illustrated system 1 2 5 6 also includes an electronic device 1259 and a busbar 1260 for providing the controller and the electronic device, as well as a communication channel between the controller and the memory. The busbar can include an address, a data bus, and a control bus, each of which is independently configured; or a common communication channel can be used to provide address, information, and/or control, the use of which is managed by the controller . In an embodiment, the electronic device 1 259 can be an additional memory similar to the memory 1 285 configuration. An embodiment may include one or more peripheral devices 1261 connected to the busbar 1260. Peripheral devices may include a display, additional storage memory, or other control elements that may operate in conjunction with the controller and/or the memory. In an embodiment, the controller is a processor. Any of the controller 1257, the memory 1258, the electronic device 1259, and the peripheral device 1261 can comprise a nanofoil transistor in accordance with several embodiments. The system 1256 can include, but is not limited to, information processing equipment, telecommunications systems, and computers. Applications containing nanofuse transistors as described in this disclosure include electronic systems for memory modules, device drivers, power modules, communication modems, processor modules, and special application modules And can include multi-layer, multi-chip modules. Such circuitry may further be a sub-component of various electronic systems 16 1357112, such as clock television mobile phones, personal computer automobiles, industrial control systems, aircraft, and others.

The s S stealth can be implemented as a memory element containing a nanowire-shaped transistor according to several embodiments. It will be appreciated that embodiments can also be implemented on any size and type of hidden circuitry and are not intended to be limited to a particular type of memory component. The memory class 33 includes DRAM, SRAM (Static Random Access Memory) or a secret memory. In addition, the DRAM can be generally referred to as SGRAM (Synchronous Graphics Random Access Memory), SDRAM (Synchronous Dynamic Random Access Memory). Synchronous DRAM with memory), SDRAM 11, and DDR SDRAM (Double-Speed SDRAM). Various oils u Emerging memory technologies can use transistors with these pressure-dependent strain channels.

The disclosure includes several processes, circuit diagrams, and unit structures. This subject matter is not limited to a specific process sequence or logical configuration. Although the specific embodiments have been shown and described herein, it will be understood by those skilled in the art that the <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; This application is intended to cover adaptations or variations of the subject matter. 4 The above description is intended to be illustrative and not limiting. The combination of the above-mentioned embodiments, and other embodiments, is apparent to those skilled in the art and the scope of the invention is to be understood by reference to the scope of the appended claims and the equivalents The maximum range is determined. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 shows the general trend and relationship of various component parameters with a coefficient k as an adjustment factor. 17 1357112 Figure 2 shows the subcritical leakage current of a conventional 矽MO SFET. Figure 3 shows the double gate MOSFET with the drain, source, front and back gates isolated by the gate insulator and the semiconductor body, and the electric field generated by the drain. Figure 4 generally shows the improved subcritical characteristics of the dual gate, the two gates, or the surrounding gate MOSFET compared to the subcritical characteristics of conventional bulk MOSFETs. 5A-C illustrate a conventional fin FET.

6A-6L illustrate a process for forming a nano fin transistor, in accordance with several embodiments of the subject matter. Figure 7 shows a top view of the layout of the nano-fin of a nano-fin transistor array, in accordance with several embodiments. Fig. 8 is a view showing a process for fabricating a nano fin-shaped transistor, according to several embodiments of the subject matter. Figure 9 illustrates a process for forming a fin from a crystalline substrate, in accordance with several embodiments of the subject matter.

Figure 10 is a simplified block diagram of a high order organization of several embodiments of memory elements in accordance with several embodiments of the subject matter. Figure 11 shows a diagram of an electronic system having one or more nano fin transistors, in accordance with several embodiments. Fig. 12 is a diagram showing an embodiment of a system having a controller and a memory. [Main component symbol description] 18 1357112

100 transistor 102 channel 503 fin FET 504 first source / 505 ' 622 second source / drain region 506 fin 507, 618 gate 508 ' 6 1 9 gate 509 buried oxide layer 510 arrow 611 Structure 612 Hole 613 Amorphous germanium 614, 714 sidewall spacer 615 tantalum nitride layer 616 substrate 617 fin fin 618 conductive line 619 gate insulation A 620 gate material 621 insulation 622 gate winding material 623, 624 Source 725 Mask Band 1042 Memory Element 1043 Memory Array 1044 Read/Write 1045 Channel 1046 Memory Single 1047 Character Line 1048 Bit Line 1049 Character Line Select Circuit 1050 Bit Line Select 1051 Read Circuit 1152 Electronics System 1153 ' 1 257 Controller 1154 , 1260 sink 1155 Electronic component 1252 ' 1256 Series 1252 ' 1 25 8 Memory 1259 Electronic device 1261 Peripheral device / 汲 · Polar region insulation / bungee region into the control circuit element selection circuit flow Row 19

Claims (1)

1357112 Dijon &gt; 1VT Patent Case ico Year Month Amendment X. Patent application scope: A method for forming a transistor, comprising at least the following steps: forming a fin from a crystalline substrate, wherein forming the fin comprises the steps of: depositing a material on the crystalline substrate Etching the material using a reticle pattern having a minimum feature length to define at least two holes in the material, wherein the material Having surrounding and defining a sidewall of each of the holes, and wherein each of the holes has a width of a minimum feature length (F); &amp; each of the sidewalls surrounding and defining the holes Forming sidewall spacers; forming a fin pattern from the sidewall spacers, wherein the fin pattern provides a side gate array of one side gate, wherein a first column is adjacent to The center-to-center spacing of one of the first columns - and the center-to-center spacing is the minimum feature length (F) minus the thickness of the fins (Δ T), and the second column versus The center-to-center spacing of one of the second columns adjacent to the second column is the minimum feature length (F) plus the thickness of the rotating grip (ΔT); and the use of the fin map The master is used as a mask to engrave the binding from the crystalline substrate, wherein the Korean has a thick sound corresponding to the minimum characteristic length in the direction of the whistle ~, * thickness And having a profile thickness smaller than that of the first direction perpendicular to the first direction, '^ minimum feature length, wherein the first direction is a temporary _ t β mussel and one of the crystalline substrates The surface 20^357112 is parallel, and the second direction is substantially parallel to the surface of the crystalline substrate, and a first source/drain region is formed under the fin in the substrate; Forming a surrounding gate insulating layer; forming a surrounding gate around the fin, and the surrounding gate is isolated from the fin by the surrounding gate insulating layer; and forming in the top of the fin A second source/drain region. 2. The method of claim 1, wherein the forming a fin from a crystalline substrate comprises forming a fin from a crystalline germanium substrate. 3. The method of claim 1, wherein the forming a first source/drain region under the fin in the substrate comprises implanting in a trench adjacent to the substrate A dopant is added and the dopant is diffused below the fin. 4. The method of claim 3, wherein the diffusion comprises diffusing the dopant into the bottom of the fin. 5. The method of claim 1, wherein the forming a surrounding gate insulating layer comprises forming yttrium oxide. 6. The method of claim 1, further comprising recessing the surrounding gate 21 1357112 such that the height of the surrounding gate is lower than the height of the fin. 7. The method of claim 1, further comprising forming a gate contact adjacent the surrounding gate and in contact with the surrounding gate. 8. The method of claim 1, further comprising forming at least one gate line adjacent to and in contact with the surrounding gate. 9. The method of claim 8, wherein the forming the at least one gate line adjacent to the surrounding gate and contacting the surrounding gate comprises forming a first gate line and a second gate a first gate line adjacent to and in contact with a first side of the surrounding gate, the second gate line being adjacent to and in contact with a second side of the surrounding gate, the first and second side systems Located on the opposite side of the fin. 10. The method of claim 8, wherein the fin has a rectangular range, the rectangular range including a short side and a long side 'which is adjacent to the surrounding gate and the surrounding gate Contacting at least one of the gate lines includes forming a gate line to contact the surrounding gate on the long side. 11. The method of claim 8, wherein the fin has a rectangular range, the rectangular range having a short side and a long side, wherein the surrounding gate is formed adjacent to the surrounding gate Contacting at least one gate 22 1357112 line includes forming a gate line to contact the surrounding gate on the short side. 12. The method of claim 1, wherein said forming a surrounding gate comprises forming a polysilicon surrounding the gate. A method of forming a transistor, comprising at least the following steps: Etching a fin from a crystalline germanium substrate, wherein the fin is engraved from the crystalline substrate comprising the steps of: depositing a material on the crystalline germanium substrate; using one having a minimum characteristic length A reticle pattern etches the material' to define at least two holes in the material, wherein the material provides sidewalls that surround and define each of the holes, and wherein each of the holes has a minimum width a length (F); forming a sidewall spacer on each of the sidewalls surrounding and defining the aperture; Forming a sinuous pattern from the sidewall spacers, wherein the smear pattern provides an array of sidewall spacers, wherein a first column and a center-to-center spacing adjacent to a second column of the first column are the minimum The feature length (F) minus the thickness of the fin (ΔΤ), and the center of the second column adjacent to the third column of the second column is the minimum feature length (F) plus the fin The thickness of the object (Δ!); and using the fin pattern as a mask to etch the fin from the crystalline germanium substrate '23 1357112, which gives the fin a first direction Corresponding to a profile thickness of a minimum feature length, and having a profile thickness less than the minimum feature length in a second direction perpendicular to the first direction, wherein the first direction is substantially associated with a surface of the crystalline germanium substrate Parallel 'and the second direction is substantially parallel to the surface of the crystalline germanium substrate, a first source/' and a polar region are formed under the substrate in the substrate; • around the fin Forming a surrounding gate oxide; in the fin Forming a polycrystal around the gate to surround the gate, and the polysilicon surrounding the gate is isolated from the fin by the surrounding gate oxide; and forming a second source/汲 in the top of the fin Polar zone. 14. The method of claim 13, wherein the forming a surrounding gate oxide comprises thermally oxidizing the fin from the crystalline germanium substrate. 15. forming a transistor The method comprises at least the steps of: etching a fin from a crystalline substrate, the fin having a cross-sectional thickness corresponding to a minimum feature length in a first direction and perpendicular to the first direction a second direction having a profile thickness less than the minimum feature length, the first direction being substantially parallel to a surface of the crystalline substrate and the second direction being substantially parallel to the surface of the crystalline substrate Wherein etching a fin from the crystalline substrate comprises the steps of: 24 The third material is removed from the defined wide wall pattern by the deposition "on the crystalline substrate; the material is etched using a reticle pattern having a small feature length of the current θ In the material, at least two holes are formed in the ϋ~, 丫 boundary, wherein the material provides a side wall of the hole &+ &gt; 母, and wherein each of the holes is the minimum feature length (F); forming a backlash wall on each of the sidewalls surrounding the drum defining the holes; forming a fin pattern from the sidewall spacers, wherein the Hans are provided for the sidewall spacer array , wherein a first column and B are adjacent to the center-to-center spacing of the first-second column is the minimum feature length (F) minus the thickness of the fin (ΔΤ), and the second column is adjacent to the second column The center-to-center spacing of one of the columns is the minimum feature length (F) plus the thickness of the fin (ΔT); the reticle corresponding to the recording pattern is used to surpass the crystalline group to form from the substrate a fin; forming a lower portion of the fin below the substrate a first source/> and a polar region; a surrounding gate insulating layer is formed around the fin; a surrounding gate is formed around the fin and the surrounding gate is surrounded by the gate insulating layer and the The fin is isolated; and a second source/pole region is formed in the top of the fin. The method of claim 5, wherein the forming of the gate insulating layer comprises thermal oxidation 17. The method of claim 15, wherein the forming a surrounding gate comprises etching the gate to lower the gate tip On the top surface of the fin. 1 8. A method of forming an array of transistors, comprising at least: Forming a nitride layer on a silicon wafer; forming an amorphous layer on the nitride layer; patterning and etching at least one hole in the amorphous layer; oxidizing the amorphous layer in the amorphous Forming an oxide sidewall spacer on the sidewall of the germanium layer; backfilling the void with an amorphous germanium; planarizing to expose the oxide sidewall; patterning and etching the oxide sidewall to form a fin pattern; Removing the amorphous germanium; etching the nitride layer leaving a nitride of a fin pattern under the germanic sidewall of the fin pattern; etching the germanium using the nitride of the fin pattern as a mask a wafer to etch a fin from the germanium wafer; implanting a dopant and diffusing the dopant to form a conductive line under the etched fins, the dopant providing the germanium a first source of the fins &gt; and a pole region, 26 1357112 forming a surrounding gate insulating layer on the fins; forming a surrounding gate around the fins and surrounding The gate is isolated from the fins by the surrounding gate insulating layer; forming gate lines of adjacent transistors in the array adjacent to and in contact with the surrounding gates; Forming a second source/drain region of the fins. 19. The method of claim 18, wherein said forming a surrounding gate insulating layer comprises thermally oxidizing said fins etched from said crystalline germanium substrate. 20. The method of claim 18, wherein the forming a surrounding gate comprises forming a polycrystalline silicon gate. 2 1 . A semiconductor structure comprising an array of transistors arranged in rows and columns, each transistor comprising: a crystalline substrate having a trench etched therein to form a crystalline semiconductor fin from the substrate The fin has a cross-sectional dimension smaller than a minimum feature size; a first source/drain region and a second source/drain region, the first source/drain region being formed on the crystalline substrate Inside the fin bottom, the second source/drain region is formed in the top of the fin to define a vertical between the first and second source/drain regions within the fin Directional channel 27 1.357112 region, a gate insulating layer formed around the fin; and a surrounding gate formed around the fin and isolated from the fin by the gate insulating layer One of the first column and the center-to-center spacing adjacent to the second column of the first column is the minimum feature size spacing (NF) minus the thickness of the fin structures, and the second column is adjacent to the first The center-to-center spacing of one of the third columns is the minimum feature size spacing (NF) plus the thickness of the fin structures. 22. The semiconductor structure of claim 21, wherein the above The crystalline substrate comprises ruthenium. 23. The semiconductor structure of claim 21, wherein the crystalline substrate is a crystalline germanium wafer. 24. The semiconductor structure of claim 21, wherein the surrounding gate insulating layer comprises hafnium oxide. 25. The semiconductor structure of claim 21, wherein the surrounding gate comprises polysilicon. 26. The semiconductor structure of claim 21, wherein the above 28 Γ 357112 The surrounding gate contains metal. 2 7. A semiconductor structure comprising a transistor array arranged in rows and columns, each transistor comprising: a crystal bite wafer * having a groove engraved therein to form a crystalline semiconductor fin from the wafer The fin has a cross-sectional dimension of a minimum feature size in a first direction and a cross-sectional dimension corresponding to the minimum feature size in a second direction perpendicular to the first direction; a first source a pole/drain region and a second source/drain region, the source/gitter and the polar region are formed in the bottom of the impurity in the crystallized wafer* the second source/pole region is formed| In the top of the fin, a vertical track region is defined between the first and second source/drain regions in the fin; a gate insulating layer is formed around the fin And a surrounding gate formed around the fin and isolated from the fin by the gate insulation, wherein a first column and a center-to-center spacing adjacent to the second column of the first column are The minimum feature size interval (NF) minus the thickness of the fin structures, and the second column Third column adjacent to the central row of one of the second minimum feature size of the pitch spacing (NF) plus those of the fin-like structures that. 2 8. The semiconductor structure according to claim 27, wherein the upper array is slightly thicker than the central layer of the material layer 29 1357112 The gate insulating layer contains hafnium oxide. 2. The semiconductor structure of claim 28, wherein the upper oxidized gate insulating layer is an oxidizing dream of thermal growth. 30. The semiconductor structure of claim 27, wherein the upper surrounding gate comprises a polycrystalline spine surrounding the gate. The semiconductor structure of claim 27, wherein the upper surrounding gate comprises a metal surrounding gate. A semiconductor structure comprising at least: an array of transistors arranged in rows and columns, each transistor comprising a first source/drain region, one above the first source/drain region a second source/drain region, and a vertical channel region between the first and second source/drain regions, the channel region being formed in a crystalline half-body fin, the crystalline semiconductor fin The profile has a profile thickness less than a minimum feature, the fin being formed from a crystalline wafer by etching the trench to define the fin, each transistor further comprising a gate layer and a surround a gate electrode, the gate insulating layer is formed around the fin, the surrounding gate is formed around the fin and is isolated from the fin by the gate insulating layer, wherein a first column is adjacent to the first One of the columns, the second column, the center-to-center spacing, the minimum feature size interval (NF) minus the fins The first guide ruler edge » the shape of the 30 Γ 357112 thickness of the object structure, and the second column and the center-to-center spacing adjacent to the third column of the second column are the minimum feature size interval (NF ) plus the The thickness of the fin structure. 33. The structure of claim 32, further comprising at least one gate line in contact with the surrounding gate along the fins. The structure of claim 33, wherein the fin has a rectangular cross section, the rectangular cross section having a long side and a short side, and the at least one gate line contacts the long side The surround gate. 35. The structure of claim 33, wherein the fin has a rectangular cross section, the rectangular cross section including a long side and a short side ' and the at least one gate line contacts the short side The surround gate. 3. The structure of claim 3, wherein the at least one of the gate lines comprises two gate lines on opposite sides of the fins. 31 Γ357112 Figure 6H 6\6 Figure 6J