CN105702568B - Method for manufacturing static random access memory and method for manufacturing semiconductor device - Google Patents

Method for manufacturing static random access memory and method for manufacturing semiconductor device Download PDF

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CN105702568B
CN105702568B CN201610072794.1A CN201610072794A CN105702568B CN 105702568 B CN105702568 B CN 105702568B CN 201610072794 A CN201610072794 A CN 201610072794A CN 105702568 B CN105702568 B CN 105702568B
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fin
gate electrode
forming
dummy pattern
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CN105702568A (en
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廖忠志
张长昀
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66409—Unipolar field-effect transistors
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    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
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Abstract

The invention provides a manufacturing method of a static random access memory and a semiconductor device, wherein the manufacturing method of the static random access memory comprises the steps of providing a substrate; forming a first dummy pattern on the substrate; forming a first spacer along at least one sidewall of the first dummy pattern; removing the first dummy pattern; and forming a first fin of the static random access memory by removing a part of the substrate which is not covered by the first gap wall. The invention has the advantage that the size of the structure can be reduced without being limited by the inherent limit of the photoetching process.

Description

Method for manufacturing static random access memory and method for manufacturing semiconductor device
The present application is a divisional application of an invention patent application entitled "method for manufacturing a static random access memory and method for manufacturing a semiconductor device" with application number 201010206632.5 filed on 13/06/2010.
Technical Field
The present invention relates generally to semiconductor device systems and methods, and more particularly to Static Random Access Memory (SRAMs) systems and methods.
Background
As the size of semiconductor devices, such as static random access memories, has been reduced to below 32 nm, fin field effect transistors (FinFETs) using multiple channel regions formed using "fins" have become more popular than standard planar transistors (planar transistors). Finfet devices provide a greater channel width through the top surface and sidewalls of the fin. By using finfet designs, one can suppress or reduce the short channel effects that are disturbing, such as threshold variation or excessive drain leakage, in order to obtain more efficient devices.
However, some problems have been encountered with the use of fin field effect transistors (FinFETs). The standard photolithographic technique (1ithographic techniques) conventionally used to form fins and gate electrodes overlying the fins has become a major process technology not used for fin field effect transistors (FinFETs). As the size of finfets becomes smaller and smaller, fundamental limitations associated with photolithography processes limit their usefulness in forming fins and gate electrodes. In other words, the photolithography process is self-limiting and cannot be scaled down as the size of the finfet to be manufactured becomes smaller.
Therefore, a new process is needed to meet the requirement of further shrinking the size of the finfet transistor in the future.
Disclosure of Invention
Accordingly, the present invention provides a layout for fabricating sram cells using dummy layers and spacers to solve the above-mentioned problems.
The invention provides a manufacturing method of a static random access memory, which comprises the steps of providing a substrate; forming a first dummy pattern on the substrate; forming a first spacer along at least one sidewall of the first dummy pattern; removing the first dummy pattern; and forming a first fin of the static random access memory by removing a part of the substrate which is not covered by the first gap wall.
The invention provides a method for manufacturing a semiconductor device, which comprises providing a fin; forming a gate dielectric layer and a gate electrode layer on the fin; forming a first dummy pattern on the gate electrode layer; forming a plurality of first spacers along sidewalls of the first dummy pattern; reserving the first spacer and removing the first dummy pattern; and patterning the gate dielectric layer and the gate electrode layer using the first spacer as a photomask.
The invention also provides a method for manufacturing a semiconductor device, comprising providing a substrate; patterning the substrate to form a plurality of fins; forming a gate electrode layer on the fin; and patterning the gate electrode layer to form a plurality of gate electrodes. The step of patterning the substrate comprises forming a first dummy pattern on the substrate; forming a plurality of first spacers along sidewalls of the first dummy pattern; removing the first dummy pattern; and removing the exposed portion of the substrate. The step of patterning the gate electrode layer includes forming a second dummy pattern on the gate electrode layer; forming a plurality of second spacers along sidewalls of the second dummy pattern; removing the second dummy pattern; and removing the exposed portion of the substrate.
The invention has the advantage that the size of the structure can be reduced without being limited by the inherent limit of the photoetching process.
Drawings
The invention can be understood in terms of embodiments to which the accompanying drawings pertain, which also form a part hereof. Those skilled in the art will recognize that the scope of the present invention is to be broadly construed, to include embodiments of the invention and variations thereof, wherein:
FIG. 1 is a diagram of one embodiment of a memory device according to the present invention;
figures 2A-2I are a flow chart of steps for forming one embodiment of a fin.
Fig. 3A-3M are a flow chart of steps for forming one embodiment of a semiconductor device.
Figure 4 is an embodiment of forming fins using three dummy patterns.
Fig. 5A to 5C are a circuit diagram of a single-port sram, a top view of a dummy layer, and a wiring diagram, respectively.
Fig. 6A to 6C are a circuit diagram, a top view and an array diagram of a dummy layer of an even port sram, respectively.
A series of process profiles and variations of embodiments of the present invention are discussed below. Like numerals will be used to indicate like elements between the several embodiments.
Wherein the reference numerals are as follows:
100: a memory device; 101: a first pass gate transistor (pass transistor);
105: a first pull-up transistor; 109: a first pull-down transistor;
107: a second pull-up transistor; 111: a second pull-down transistor;
115: a second pass-gate transistor; 202: a substrate;
207: a first virtual layer; 209: a second virtual layer;
211: a first spacer; 213: a storage unit;
215. 217: a fin; 219. 601, a step of: a discontinuous portion;
301: a gate dielectric layer; 303: a gate electrode layer;
305: a third virtual layer; 307: a second spacer;
309: a gate electrode; 311: a gate dielectric layer;
313. 315, 317, 319, 321, 323, 325, 327, 329, 331, 333, 335, 603, 605, 607: a plug;
401: a fourth dummy pattern; 403: a fifth dummy pattern;
405: a sixth dummy pattern; 501: a third pass gate transistor;
503: a fourth pass-gate transistor; 505: a third pull-down transistor;
507: a fourth pull-down transistor; 500: a read port;
505: reading a bit line; 511: a fifth pull-down transistor;
513: a fourth pass-gate transistor; vcc: a power supply lead;
WL: a word line; BL; a bit line;
RBL: a complementary bit line; vss: a ground lead;
w 1: a first width; w 2: a second width;
w 3: a third width; w 4: a fourth width;
d 1: a first distance; d 2: a second distance;
l 2: a second length; l 3: a third length;
l 4: a fourth length; l 5: a fifth length;
l 6: a sixth length; h 1: a first height.
Detailed Description
The making and using of the preferred embodiments are discussed in the following specification. Regardless, the concepts provided by the present invention are susceptible to being inventive and applied to and can be implemented in a wide variety of specific environments. The discussion of the embodiments is intended to be merely illustrative of the practice and use of the invention, and is not intended to limit the scope of the invention.
The embodiments of the present invention are described in terms of the layout of the memory cells of the sram, but the embodiments of the present invention can also be applied to the layout of other devices.
Referring to FIG. 1, FIG. 1 is a diagram illustrating a memory device 100 according to an embodiment of the invention. A first pull-up transistor 105, a first pull-down transistor 109, a second pull-up transistor 107 and a second pull-down transistor 111 are electrically connected to form two cross-coupled inverters. The drains of the first pull-down transistor 109 and the first pull-up transistor 105 are electrically connected to the gates of the second pull-down transistor 111 and the second pull-up transistor 107, and the drains of the second pull-down transistor 111 and the second pull-up transistor 107 are electrically connected to the gates of the first pull-down transistor 109 and the first pull-up transistor 105.
The memory device 100 also includes a first pass-gate transistor 101 and a second pass-gate transistor 115. In one embodiment, the gate length of the pass-gate transistors (e.g., the first pass-gate transistor 101 and the second pass-gate transistor 115) is longer than the pull-down devices (e.g., the first pull-down transistor 109 or the first pull-down transistor 111). The gate of the pass-gate transistor is connected to a word line WL that controls the access operation of the memory device 100 to read or write the memory cell (these functions will be described later). The first pass-gate transistor 101 is connected to a bitline BL and the second pass-gate transistor 115 is connected to a complementary bitline RBL. The first pass-gate transistor 101, the first pull-up transistor 105 and the first pull-down transistor 109 are connected to a common node, and the second pass-gate transistor 115, the second pull-up transistor 107 and the second pull-down transistor 111 are connected to a common node.
In the embodiment shown in fig. 1, the memory device 100 performs writing when a high voltage is applied to the word line WL to turn on the first pass-gate transistor 101 and the second pass-gate transistor 115. Since the first and second pass-gate transistors 101 and 115 are turned on, the bit line BL and the complementary bit line RBL can write into the memory device 100.
The memory device 100 of this embodiment can also be read when a high voltage is applied to the word line WL to turn on the first pass-gate transistor 101 and the second pass-gate transistor 115. Since the first and second pass-gate transistors 101 and 115 are turned on, the bit line BL and the complementary bit line RBL can also read the memory device 100.
Fig. 2A is a cross-sectional view of a semiconductor substrate 202. The substrate 202 may be an active layer of a bulk silicon (bulk silicon) substrate, doped or undoped substrate, or silicon-on-insulator (SOI) substrate. Generally, a silicon-on-insulator (SOI) substrate is a layer of semiconductor material, such as silicon, germanium (germanium), silicon germanium (sige), silicon-on-insulator (SOI), silicon germanium-on-insulator (SGOI), or a combination thereof. The substrate 202 may also be other substrates, such as multi-layered substrates (multi-layered substrates), gradient substrates (gradient substrates), or hybrid orientation substrates (hybrid orientation substrates).
Fig. 2B and 2C are a cross-sectional view and a top view of the first dummy layer (dummy layer)207, the second dummy layer 209 and the first spacer 211, respectively. First dummy layer 207 and second dummy layer 209 are formed to define the dimensions of fin 215 (to be illustrated in figure 2F) to be formed later. The first dummy layer 207 and the second dummy layer 209 are perpendicular to each other and have the same first width w1, the first width w1 being between 0.02 μm and 0.2 μm, for example 0.8 μm. In addition, the first dummy layer 207 is separated from the second dummy layer 209 by a first distance d1, and the first distance d1 is between 0.05 μm and 1 μm, for example, 0.1 μm. In the present embodiment, the first dummy layer 207 and the second dummy layer 209 can be regarded as a first dummy pattern and a second dummy pattern, respectively, but not limited thereto.
The first dummy layer 207 and the second dummy layer 209 are formed by patterning a first initial dielectric layer (not shown) formed using an appropriate process, such as Chemical Vapor Deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), etc. The first preliminary dielectric layer may be comprised of a dielectric material (e.g., an oxide, nitride, silicon oxynitride, combinations thereof, etc.) and may have a thickness of about between, for example, after the first preliminary dielectric layer is formed, the first preliminary dielectric layer may be patterned to form the first dummy layer 207 and the second dummy layer 209. The patterning may be performed by appropriate masking and removal steps, such as, but not limited to, photolithography and etching, and any other suitable steps may be used.
The first spacers 211 are formed along sidewalls of the first dummy layer 207 and the second dummy layer 209. The first spacer 211 may be formed by blanket depositing (not shown) a spacer layer on the previously formed structure. The spacer layer may comprise silicon nitride, oxynitride, silicon carbide, oxynitride, oxide …, etc., and may be formed by conventional processes such as chemical vapor deposition, plasma-excited chemical vapor deposition, sputtering, or other known methods. The spacer layer may have a thickness of about one-half, for example, the first spacer 211 may be formed by anisotropically etching and removing the spacer layer on the horizontal surface of the structure.
Fig. 2C is a top view of a memory cell 213 in the memory device 100 to be fabricated. As shown, the memory unit 213 is indicated by a dotted line. However, it is noted that the boundary of the storage unit 213 is not to be interpreted as a final product. Rather, memory cell 213 is used to define only the basic building block of the designed memory array. Generally, a memory device has one or more memory arrays. The memory unit 213 can be repeatedly configured any number of times (e.g., thousands, hundred thousands, million, ten million, or more) to form a memory capable of storing different data amounts. The memory cell 213 has a second width w2, the second width w2 being between 0.05 μm and 0.3 μm, such as 0.2 μm, and the memory cell 213 has a second length l2, the second length l2 being between 0.1 μm and 1 μm, such as 0.5 μm.
Fig. 2D and fig. 2E are a cross-sectional view and a top view, respectively, after forming the first spacer 211 and removing the first dummy layer 207 and the second dummy layer 209. In this embodiment, the first dummy layer 207 and the second dummy layer 209 are removed using a wet etch, but other suitable etching techniques, such as a dry etch, may be used. For example, if the first dummy layer 207 and the second dummy layer 209 are formed of silicon oxide, an etching solution, such as hydrofluoric acid (HF), may be used to remove the first dummy layer 207 and the second dummy layer 209 without significantly removing the first spacer 211.
By forming the first spacers 211 in this shape, the first spacers 211 can be formed without using a photolithography process and its inherent limitations. Since the photolithography process of the first spacer 211 may be skipped, the first spacer 211 may not be limited to the limitation inherent to the photolithography process. The inherent limitation of not being limited to the photolithography process will allow the formation of the first spacers 211 of a smaller size than is allowed by the photolithography process.
Figures 2F and 2G are a cross-sectional view and a top view, respectively, of forming fin 215 on substrate 202 (shown in figure 2D). In this embodiment, the first spacers 211 defined by the first dummy layer 207 and the second dummy layer 209 are used as a photomask to form the fins 215 under each first spacer 211. Fin 215 is formed by protecting portions of substrate 202 that will become fin 215 while removing unprotected portions of substrate 202 using a dry etch (e.g., reactive ion etch; RIE). This removal step may be continued until fin 215 has a first height H1, H1, such as the cross-sectional and top-down views of removing first spacers 211 and etching two of fins 215 to form discontinuous fin 217, respectively, as shown in fig. 2H and 2I. The first spacers 211 may be removed using a wet etch that is selective to the spacers so that other exposed material is not significantly removed when the first spacers 211 are removed. For example, if the material of the first spacers 211 is silicon nitride, the first spacers 211 may be selectively removed by using nitric acid H3NO4 as an etching solution. However, the removal of the first spacers 211 may also be accomplished using other suitable removal processes, such as using additional photolithography steps to selectively remove the first spacers 211.
Further, figure 2I shows two of the fins 215 patterned into discontinuous fins 217 (the discontinuity of which is represented by dashed line 219). Discontinuous fin 217 is beneficial in forming memory device 100 in memory cell 213 so that continuous fin 215 is not present where it is not needed. In this flow, if scaling is not as important as forming fins 215, the patterning of fins 215 may be performed using a similar flow as described above, or using appropriate masking and removal steps, such as photolithography and etching. In one embodiment, the discontinuous fins 217 have a discontinuity of between about 0.02 μm and 1 μm, such as 0.5 μm.
Alternatively, the step of patterning the discontinuous fin 217 may be performed during the step of forming the fin 215 by removing the first spacer 211 on the fin 215 within the discontinuity 219 prior to forming the fin 215. Since first spacers 211 have been removed, when forming fin 215, fin 215 located within the discontinuity will be removed to form fin 215 and discontinuous fin 217 simultaneously.
A dielectric material (not shown), such as oxide, may optionally be disposed between fin 215 and discontinuous fin 217 to further isolate the fin-like structures from each other. In one embodiment, the dielectric material may be deposited using chemical vapor deposition and then polished to the height of fins 215 using Chemical Mechanical Polishing (CMP). After planarization is complete, portions of the dielectric material may be removed by a wet etch so that fins 215 and discontinuous fins 217 extend beyond the dielectric material for subsequent processing.
Fig. 3A and 3B are a cross-sectional view and a top view of forming a gate dielectric layer 301, a gate electrode layer 303 and a third dummy layer 305, respectively, wherein fig. 3A is a cross-sectional view and a top view along line a-a' in fig. 3B. The gate dielectric layer 301 may be formed by thermal oxidation (thermal oxidation), chemical vapor deposition (cvd), sputtering, or other known methods for forming gate dielectric materials. The thickness of gate dielectric layer 301 above fin 215 may be different than the thickness of the gate dielectric layer on the sidewalls of fin 215, depending on the technique used to form the gate dielectric layer. The gate dielectric layer 301 may be silicon oxide, silicon oxynitride, high-K dielectric (high-K dielectric), or a combination thereof, and may have a thickness in a range from about one to about one, for example, the gate dielectric layer 301 may also be a high-K dielectric (high-K) material, such as lanthanum oxide (La2O3), hafnium oxide (HfO2), hafnium oxynitride (HfON), zirconium oxide (ZrO2), or a combination thereof, and may have a thickness in a range from about one to about one, for example, less. In the present embodiment, the third dummy layer 305 can be regarded as a third dummy pattern.
A gate electrode layer 303 is formed over the gate dielectric layer 301. The gate electrode layer 303 comprises a conductive material selected from polysilicon, polysilicon germanium, metal nitrides, metal silicides, metal oxides, or metal materials. For example, the metal nitride includes tungsten nitride, molybdenum nitride, titanium nitride, and tantalum nitride. For example, metal silicides (metallic silicides) include tungsten silicide, titanium silicide, cobalt silicide, nickel silicide, platinum silicide, erbium silicide, or combinations thereof. For example, metal oxides (metalllics) include ruthenium oxide, indium tin oxide, or combinations thereof. For example, the metal material includes tungsten, titanium, aluminum, molybdenum, copper, nickel, platinum, and the like.
The gate electrode layer 303 may be formed by chemical vapor deposition, sputter deposition, or other known methods of forming deposited conductive materials. Gate electrode layer 303 is approximately as thick as between. The gate electrode layer 303 typically has an uneven upper surface and may be planarized prior to patterning the gate electrode layer 303 or prior to etching the gate electrode. Ions may or may not be generated at this stage at gate electrode layer 303. For example, ions may be generated in the gate electrode layer 303 by ion implantation techniques.
A third dummy layer 305 is formed on the gate electrode layer 303 to define a final desired gate electrode. Third dummy layer 305 has a plurality of edges covering a portion of each of fin 215 and discontinuous fin 217 in memory cell 213. For example, the memory cell 213 has a second width w2 of about 0.2 μm, and the third dummy layer 305 has a third width w3 between the first and second desired gate electrodes (further described in FIG. 3G and FIG. 3H), and the third width w3 is about 0.02 μm to about 0.3 μm, such as about 0.07 μm.
The third dummy layer 305 may be formed of a material similar to the first dummy layer 207 and the second dummy layer 209, and may be formed using a similar process. For example, the third dummy layer 305 may be formed by depositing an initial dielectric layer (not shown), which may be a single material or a combination of materials, and then patterning the initial dielectric layer using a photomask and etching process to obtain the desired pattern. However, these materials and process steps are illustrative and not intended to limit the present invention, and other suitable methods may be used to form the third dummy layer 305.
Fig. 3C is a cross-sectional view and fig. 3D is a top view of the second spacer 307 formed along the third dummy layer 305, wherein fig. 3C is a cross-sectional view and a top view along the line a-a' in fig. 3D, respectively. The second spacers 307 may be formed of a material similar to the first spacers 211 (as described in fig. 2B) and may be formed by a similar process. For example, the second spacers 307 may be formed by blanket depositing a spacer layer (not shown) using Chemical Vapor Deposition (CVD), and then anisotropically etching the spacer layer to form the second spacers 307, wherein the spacer layer may be made of silicon nitride, silicon dioxide, or the like.
Fig. 3E and fig. 3F are a cross-sectional view and a top view of the third dummy layer 305 between the second spacers 307, respectively, wherein fig. 3E is a cross-sectional view and a top view along the line a-a' in fig. 3F. Similar to the first dummy layer 207 and the second dummy layer 209, the third dummy layer 305 may be removed by wet etching, but may be removed by other suitable etching methods, such as dry etching. For example, but not limiting to the invention, if the third dummy layer 305 is made of silicon oxide, hydrofluoric acid (HF) may be used as an etching solution to remove the third dummy layer 305 without significantly removing the second spacer 307.
By forming the second spacers 307 in this shape (similar to the first spacers 211), a photolithography process may not be used. Since a photolithography process may not be used, the size of the second spacer 307 may not be limited by the photolithography process. Therefore, the second spacer 307 may have a smaller size than the size allowed by using the photolithography process.
Fig. 3G and 3H are a cross-sectional view and a top view of patterning the gate electrode layer 303 and the gate dielectric layer 301 (shown in fig. 3A to 3E) into the gate electrode 309 and the gate dielectric layer 311, respectively, wherein fig. 3G is a cross-sectional view and a top view along line a-a' in fig. 3H. The gate electrode layer 303 and the gate dielectric layer 301 are removed using the second spacer 307 as a photo mask, so that the width of the second spacer 307 is transferred to the gate electrode 309 and the gate dielectric layer 311 thereunder. The gate electrode 309 and the gate dielectric layer 311 have a fourth width w4, and the fourth width w4 is about 0.05 μm to 0.3 μm, such as 0.15 μm.
Fig. 3I and 3J are a cross-sectional view and a top view of the second spacer 307 removed from the gate electrode 309 and the gate dielectric layer 311, respectively, wherein fig. 3I is a cross-sectional view and a top view along line a-a' in fig. 3J. The second spacers 307 may be removed similarly to the first spacers 211 (as described in fig. 2H-2I), using a wet etch selective to the spacer material so that the otherwise exposed material is not significantly removed when the spacers are removed. For example, if the material of the second spacer 307 is silicon nitride, the second spacer 307 can be selectively removed by using nitric acid H3NO4 as an etching solution. However, the removal of the second spacers 307 may also be performed using other suitable removal processes, while the gate electrode 309 and the gate dielectric layer 311 may be retained.
Memory device 100 may also be completed by forming permanent (permanent) spacers (not shown), source/drain regions (not shown), and silicide contacts (not shown). Permanent spacer walls are formed on both sides (sides) of the gate electrode 309 and typically are blanket deposited to form a spacer layer (not shown) over the previously formed structure. The material of the permanent spacers includes silicon nitride, silicon oxynitride, silicon carbide (SiC), silicon oxynitride, oxide, etc., and may be formed by chemical vapor deposition, plasma-excited chemical vapor deposition, sputtering, or other known methods. The permanent spacers are then patterned, such as by anisotropically etching away the spacer layer on horizontal surfaces of the structure.
By supplementing (compensating) the impurities within fin 215 by implanting appropriate impurities (dopans), source/drain regions are formed in the exposed portions of fin 215. For example, P-type impurities, such as boron, gallium, indium, etc., are used to form PMOS devices, while N-type impurities, such as phosphorus, arsenic, antimony, etc., are used to form NMOS devices. The source/drain regions are implanted using the gate electrode 309 and permanent spacers as a photomask. It is noted that one of ordinary skill in the art will also recognize that various other processes and steps may be used to form these source/drain regions. For example, those skilled in the art will also appreciate that various implantation techniques may be performed using different spacers and signal lines to form source/drain regions having particular shapes or particular characteristics as may be appropriate for a particular purpose.
An optional silicidation process may also be performed after formation of the source/drain regions to form suicide contacts over the source/drain regions along one or more sidewalls and an upper surface of fin 215. The silicide contacts may include nickel, cobalt, platinum, or erbium to reduce the Schottky barrier height of the contacts (Schottky barrier rierheight). However, other common materials (e.g., titanium, palladium, etc.) may also be used. As is well known, silicidation (silicidation) is performed by blanket depositing an appropriate metal layer followed by an annealing step (annealing) in order to react the metal with the exposed silicon underneath. Then, an etching step is selectively performed to remove the unreacted metal layer. The silicide contact has a thickness of between about 5nm and about 50 nm.
Fig. 3K is a top view of the patterned gate electrode 309 and electrical contacts of the first pass-gate transistor 101, the second pass-gate transistor 115, the first pull-up transistor 105, the first pull-down transistor 109, the second pull-up transistor 107, and the second pull-down transistor 111. The gate electrode 309 is patterned to separate different transistors, for example, the second pass-gate transistor 115 and the first pull-up transistor 105. To separate gate electrode 309 and form the six transistors on fin 215 and discontinuous fin 217, gate electrode 309 may also be patterned using a photomask and removal step, such as a photolithographic photomask and etch.
As shown in fig. 3K, the source of the first pull-up transistor 105 is electrically connected to the power supply line Vcc via a plug 313, and the source of the second pull-up transistor 107 is electrically connected to the power supply line Vcc via a plug 315. The source of the first pull-down transistor 109 is electrically connected to the ground line Vss via the plug 317, and the drain of the first pull-down transistor 109 is electrically connected to the drain of the first pass-gate transistor 101 via the fin 215. The source of the second pull-down transistor 111 is electrically connected to the ground line Vss via the plug 319, and the drain of the second pull-down transistor 111 is electrically connected to the drain of the second pass-gate transistor 115 via the fin 215.
The source of the first pass-gate transistor 101 is electrically connected to the bit line BL (shown in fig. 1) via the plug 321, and the first pass-gate transistor 101 electrically couples the bit line BL to the drain of the first pull-down transistor 109 via the fin 215. The gate electrode 309 of the first pass-gate transistor 101 is electrically connected to the word line WL via the plug 321.
As shown in fig. 3K, the source of the second pass-gate transistor 115 is electrically coupled to the complementary bit line RBL (shown in fig. 1) by the plug 325, and the second pass-gate transistor 115 electrically couples the bit line RBL to the drain of the second pull-down transistor 111 by the fin 215. The gate electrode 309 of the second pass-gate transistor 115 is electrically connected to the word line WL via the plug 327.
The drain of the first pull-up transistor 105, the drain of the first pull-down transistor 109, the drain of the first pass-gate transistor 101, the gate electrode 309 of the second pull-up transistor 107 and the gate electrode 309 of the second pull-down transistor 111 are electrically coupled to the plugs 329 and 331 by means of an interconnect (not shown). Similarly, the drain of the second pull-up transistor 107, the drain of the second pull-down transistor 111, the drain of the second pass-gate transistor 115, the gate electrode 309 of the first pull-up transistor 105, and the gate electrode 309 of the first pull-down transistor 109 are electrically coupled to the plugs 333 and 335 via interconnects (not shown). The interconnect may be made of copper, but may also comprise tungsten, aluminum-tungsten alloy, aluminum, refractory metal, metal compounds, metal silicides, combinations thereof, and the like.
FIG. 3L shows an array of memory cells 213, each memory cell 213 including a single memory device 100. For clarity of illustration, fig. 3L shows only two rows and two columns of memory cells 213, however, the number of rows and columns can be any number, and typically a fully functional device will use more than two rows and two columns of memory cells. As shown, discontinuous fin 217 extends between two different memory cells 213, while fin 215 extends across more memory cells, e.g., 4 memory cells 213 or more.
Fig. 3M shows bit lines BL, word lines WL, ground conductive lines Vss and power conductive lines Vcc connected to the memory device 100. As shown, bit line BL, power supply conductor Vcc, fin 215, and discontinuous fin 217 are parallel to one another, while word line WL, ground conductor Vss, fin 215, and discontinuous fin 217 are perpendicular to one another, but word line WL is parallel to ground conductor Vss and gate electrode 209.
Figure 4 is another embodiment using a separate fourth dummy pattern 401 to form two discontinuous fins 217. In this embodiment, the sidewalls of the fourth dummy pattern 401 are formed with two discontinuous fins 217 along the sidewalls thereof for the first pull-up transistor 105 and the second pull-up transistor 107 using a process similar to that shown in fig. 2A-2I. In this embodiment, the fourth dummy pattern 401 has a second length l2 and a fourth width w4, the second length l2 is about 0.05 μm to 1 μm and about 0.1 μm, and the fourth width w4 is about 0.05 μm to 0.3 μm and about 0.2 μm.
In addition, a fifth dummy pattern 403 and a sixth dummy pattern 405 may be disposed on two opposite sides (sides) of the memory cell 213. In this embodiment, a portion of the fifth dummy pattern 403 is disposed in the memory cell 213, and another portion of the fifth dummy pattern 403 is outside the memory cell 213 (e.g., inside an adjacent memory cell 213). Similarly, the sixth dummy pattern 405 is partially disposed in the memory cell 213, and is partially disposed outside the memory cell 213 (e.g., within an adjacent memory cell 213). In this embodiment, the fifth dummy pattern 403 and the sixth dummy pattern 405 are used to form a single fin 215, one is the fin 215 generated using the fifth dummy pattern 403, one is the fin 215 generated using the sixth dummy pattern 405, and the single fin 215 is the sum of two discontinuous fins 217 generated using the fourth dummy pattern 401.
When the fifth dummy pattern 403 and the sixth dummy pattern 405 are used to form a single fin 215, the fifth dummy pattern 403 and the sixth dummy pattern 405 have a third length l3, the third length l3 is about 0.04 μm to about 0.6 μm, and about 0.12 μm. In addition, the fifth dummy pattern 403 and the sixth dummy pattern 405 are separated from the fourth dummy pattern 401 by a second distance d2, and the second distance d2 is about 0.05 μm to 1 μm, and about 0.1 μm. This spacing may allow the entire memory cell 213 to have a smaller gap.
Fig. 5A to 5C are a circuit diagram, a top view of a dummy layer and a wiring diagram of a single-port sram, wherein the single-port sram includes ten transistors. In this embodiment, the third pass-gate transistor 501 is connected in parallel with the first pass-gate transistor 101, the fourth pass-gate transistor 503 is connected in parallel with the second pass-gate transistor 115, the third pull-down transistor 505 is connected in parallel with the first pull-down transistor 109, and the fourth pull-down transistor 507 is connected in parallel with the second pull-down transistor 111.
In the embodiment shown in fig. 5B, the fifth dummy pattern 403 and the sixth dummy pattern 405 are used to form two fins 215 in a single memory cell 213 (instead of each of the fins shown in fig. 4) so that a total of four fins 215 and two discontinuous fins 217 are located within the memory cell 213. In this embodiment, the fifth dummy pattern 403 and the sixth dummy pattern 405 have a fourth length l4, and the fourth length l4 is between 0.01 μm and 0.2 μm, and is about 0.04 μm.
Fig. 5C illustrates the connection of multiple transistors in this embodiment. As shown, the third pass-gate transistor 501 shares the same gate electrode 309 as the first pass-gate transistor 101, and the fourth pass-gate transistor 504 shares the same gate electrode 309 as the second pass-gate transistor 115. In addition, the third pull-down transistor 505 shares the same gate electrode 309 with the first pull-down transistor 109, and the fourth pull-down transistor 507 shares the same gate electrode 309 with the second pull-down transistor 111.
Fig. 6A to 6C are a circuit diagram, a top view of a dummy layer, and a wiring diagram of an even-port sram, in which the even-port sram includes eight transistors. In FIG. 6A, the second pull-down transistor 111 is connected to a read port 500. the read port 500 includes a fifth pull-down transistor 511 and a fourth pass-gate transistor 513 connected in series between the ground line Vss and a read bit line 505. In this embodiment, the bit line BL and the complementary bit line RBL are used for writing to the memory device 100, and the read port 500 is used for reading from the memory device 100.
In the embodiment shown in fig. 6B, fifth dummy pattern 403 is used to form a single fin 215 in memory cell 213, and sixth dummy pattern 405 is used to form two fins 215 in memory cell 213 (instead of each of the fins shown in fig. 4), resulting in a total of five fins 215 within memory cell 213. In this embodiment, the fifth dummy pattern 403 has a fifth length l5, and the fifth length l5 is between 0.04 μm and 0.6 μm, and is about 0.12 μm. The sixth dummy pattern 405 has a sixth length l6, and the sixth length l6 is between 0.04 μm and 0.4 μm, and is about 0.1 μm.
Fig. 6C is a top view of the gate electrode 309 of a formed and patterned even-port sram comprising eight transistors. As shown, two discontinuities (shown by dashed lines 601 in fig. 6C) are located in the same gate electrode 309 to separate the fourth pass-gate transistor 513, the second pass-gate transistor 115 and the gate electrode 309 of the first pull-up transistor 105. In addition, the source of the fifth pull-down transistor 511 is electrically connected to the ground wire Vss, the fifth pull-down transistor 511 and the third pass-gate transistor 503 share the same drain via a plug 603, and the fourth pass-gate transistor 513 has a drain connected to the read bit line 505 via a plug 604. The gate electrode 309 of the fourth pass-gate transistor 513 is connected to the word line WL via a plug 607.
While the invention has been described with reference to the preferred embodiments, it is not intended to be limited thereto. Moreover, those skilled in the art will recognize that the scope of the present invention should be broadly construed to include all such embodiments and variations. For example, any number of dummy patterns may be used to form different fins, gate dielectric layers and gate electrodes, and the number of dummy patterns is not intended to limit the present invention.
Although the present invention has been described in terms of several preferred embodiments of processes, machines, manufacture, compositions of matter, means, methods, or steps, it will be apparent to those of ordinary skill in the art that variations and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.

Claims (16)

1. A method for manufacturing a semiconductor device, the method comprising:
providing continuous and discontinuous fins for a finfet;
forming a common gate dielectric layer and gate electrode layer over a first of the contiguous fins and a first of the discontinuous fins;
forming a first dummy pattern over the gate electrode layer;
forming a first spacer along a sidewall of the first dummy pattern;
removing the first dummy pattern while leaving the first spacer; and
simultaneously patterning the gate electrode layer in contact with the first spacer and the gate dielectric layer in contact with the gate electrode layer using the first spacer as a mask to form a common gate structure of an SRAM cell, wherein the gate dielectric layer and the gate electrode layer are part of the SRAM cell,
wherein providing the continuous fins and the discontinuous fins further comprises:
providing a substrate;
forming a second dummy pattern over the substrate;
forming a second spacer along sidewalls of the second dummy pattern;
removing the second dummy pattern while leaving the second spacer;
cutting at least one second clearance wall of the reserved second clearance walls; and
patterning the substrate using only portions of the second spacer over the substrate that were not subjected to the truncation process and the second spacer remaining after the truncation process as masks to form the continuous fin and the discontinuous fin,
wherein, in the patterning process, the mask is a topmost mask located above the substrate,
wherein a second discontinuous fin adjacent to the first discontinuous fin has an end proximate to the common gate structure, the end being spaced apart from the common gate structure.
2. The method of claim 1, wherein the fin includes a first major axis and each of the first spacers includes a second major axis perpendicular to the first major axis.
3. The method of claim 1, wherein the gate electrode layer is patterned to form four separate conductive regions within the memory cell.
4. The method of claim 3 wherein each of the four separate conductive regions overlaps at least two fins within the memory cell.
5. The method of claim 1, wherein the gate electrode layer is patterned to form five separate conductive regions within the memory cell.
6. A method for manufacturing a semiconductor device, the method comprising:
providing a substrate;
patterning the substrate to form a plurality of continuous fins and a plurality of discontinuous fins for a fin field effect transistor, the patterning the substrate further comprising:
forming a first dummy pattern over the substrate;
forming a first spacer along a sidewall of the first dummy pattern;
removing the first dummy pattern;
cutting at least one first clearance wall of the reserved first clearance walls; and
removing exposed portions of the substrate using only the first spacers that were not subjected to the truncation process and portions of the first spacers remaining after the truncation process as a mask to form the plurality of continuous fins and the plurality of discontinuous fins, wherein the mask is a topmost mask over the substrate;
forming a common gate dielectric layer and gate electrode layer over a first continuous fin of the plurality of continuous fins and a first discontinuous fin of the plurality of discontinuous fins that are adjacent; and
patterning the gate electrode layer to form a gate electrode of an SRAM cell, the patterning the gate electrode layer further comprising:
forming a second dummy pattern over the gate electrode layer;
forming a second spacer along sidewalls of the second dummy pattern;
removing the second dummy pattern; and
simultaneously removing the gate electrode layer in contact with the second spacer and a portion of the gate dielectric layer in contact with the gate electrode layer exposed by the second spacer to form a common gate structure of an SRAM cell.
7. The method of claim 6, wherein a second discontinuous fin adjacent to the first discontinuous fin has an end proximate to the common gate structure, the end being spaced apart from the common gate structure,
the patterning the gate electrode layer further comprises:
forming a first conductive region overlapping two of the plurality of fins; and
forming a second conductive region overlying a separate one of the plurality of fins.
8. The method of claim 6, wherein the patterning the gate electrode layer further comprises:
forming a first conductive region and a second conductive region, each of the first conductive region and the second conductive region overlapping at least three of the plurality of fins; and
forming a third conductive region and a fourth conductive region, each of the third conductive region and the fourth conductive region overlapping only two of the plurality of fins.
9. The method of claim 6, wherein the patterning the gate electrode layer further comprises:
forming a first conductive region overlapping at least three of the plurality of fins; and
forming a second conductive region that overlaps only a single one of the plurality of fins.
10. The method of claim 6, wherein the fin and gate electrode are part of a memory cell of an SRAM array.
11. A method of fabricating a semiconductor device, the method comprising:
forming a first dummy pattern over the semiconductor layer of the substrate;
forming a second dummy pattern over the semiconductor layer of the substrate;
forming a first spacer adjacent to the first dummy pattern and a second spacer adjacent to the second dummy pattern;
removing a portion of the second spacer to leave a remaining portion of the second spacer;
removing the first dummy pattern and the second dummy pattern;
patterning the semiconductor layer to form first and second fins for a finfet using the remaining portions of the first and second spacers as a mask, wherein the first and second spacers are a topmost mask over the substrate during the patterning, and the second fin is formed using only the remaining portions of the second spacer;
forming one or more gate electrodes over the first fin and the second fin, comprising:
forming a gate dielectric layer and a gate electrode layer over the first fin and the second fin;
forming a third dummy pattern over the gate electrode layer;
forming a third spacer along a sidewall of the third dummy pattern;
removing the third dummy pattern while leaving the third spacer; and
simultaneously patterning the gate electrode layer in contact with the third spacer and the gate dielectric layer in contact with the gate electrode layer using the third spacer as a mask; and
forming a first SRAM cell using the first fin and the second fin.
12. The method of claim 11, wherein the first fin extends continuously across the first SRAM cell and the second fin does not extend continuously across the first SRAM cell, an end of the second fin being proximate to and spaced apart from one of the one or more gate electrodes.
13. The method of claim 12, wherein the first fin extends continuously across the second SRAM cell.
14. The method of claim 11, wherein the patterning of the gate electrode layer forms four separate conductive regions within the first SRAM cell.
15. The method of claim 14, wherein each of the four separate conductive regions overlaps at least two fins within the first SRAM cell.
16. The method of claim 11, wherein said patterning of said gate electrode layer forms five separate conductive regions within a memory cell.
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