TW200933763A - Integrated circuit package system with offset stacking - Google Patents

Integrated circuit package system with offset stacking Download PDF

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Publication number
TW200933763A
TW200933763A TW097142598A TW97142598A TW200933763A TW 200933763 A TW200933763 A TW 200933763A TW 097142598 A TW097142598 A TW 097142598A TW 97142598 A TW97142598 A TW 97142598A TW 200933763 A TW200933763 A TW 200933763A
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TW
Taiwan
Prior art keywords
integrated circuit
carrier
insert
interposer
package system
Prior art date
Application number
TW097142598A
Other languages
English (en)
Other versions
TWI397134B (zh
Inventor
Seng Guan Chow
Linda Pei Ee Chua
Heap Hoe Kuan
Original Assignee
Stats Chippac Ltd
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Publication of TW200933763A publication Critical patent/TW200933763A/zh
Application granted granted Critical
Publication of TWI397134B publication Critical patent/TWI397134B/zh

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    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
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    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H—ELECTRICITY
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    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
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    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19102—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device
    • H01L2924/19104—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device on the semiconductor or solid-state device, i.e. passive-on-chip
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    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
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    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
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Description

200933763 六、發明說明： • [相關申請秦之交互參考] 本申請案係包含同時由Heap Hoe Kuan、Seng Guan Chow、Linda Pei Ee Chua、與 Dioscoro A. Meri lo 所申/ 請之（案名為“具有可安裝的積體電路晶粒之可安裝的積 體電路封裝件系統（Mountable Integrated Circuit Package System with Mountable Integrated Circuit Die)”）的美國專利申請案的内容。該相關申請案係讓渡予 ¥ 史特斯晶片封裝公司（STATS ChipPAC Ltd. )並識別為編號 27-449 ° 本申請案亦包含同時由Heap Hoe Kuan、Seng Guan Chow、Linda Pei Ee Chua、與 Dioscoro A. Meri lo 所申 請之（案名為（具有互連鎖之積體電路封裝件系統
Integrated Circuit Package System with Interconnect Lock)’’）的美國專利申請案的内容。該相關申請案係讓渡 ❹予史特斯晶片封裝公司並識別為編號27_45〇。 本申凊案進一步包含同時由Seng Guan Chow、Heap Hoe Kuan、與Linda Pei Ee Chua所申請之（案名為具有偏移堆 疊與抗溢料結構的積體電路封裝件系統（“ Integrated Circuit Package System with Offset Stacking and
Anti~Flash Structure)，，）的美國專利申請案的内容。該 相關申請案係讓渡予史特斯晶片封裝公司並識別為編號 27-492 ° 【發明所屬之技術領域】 94512 200933763 < 本發明大體上係關於積體電路封裝件系統，且詳言 之，係關於具有囊封體（encapsulation)的積體電路封裝件 系統。 【先前技術】 為了使積體電路具有用以與其他電路系統溝通之介 面，通常將該積體電路安裝於引線框架（lead frame)或基 板（substrate)上。每一個積體電路均具有利用非常細微的 金或紹導線或導電球（conductive ball)(例如錫球）分別 連接至該基板接點（contact)或終端墊（terminal pad)的 接合墊（bonding pad)。接著’該等組件藉由個別囊封 (encapsulate)於模製塑膠（m〇ided plastic)或陶究體而 封裝以產生積體電路封裝件。 已往看見積體電路封裝技術單一電路板或基底上所安 裝的積體電路數目的增加。新的封裝設計在外形要素上 (如.封裝之積點電路的實體尺寸與形狀）更為小巧，並在 ❹整體積體電路密度上有顯著的增加。 然而’積體電路密度持續受到可用以分別於基板上安 裝積體電路^ “地l(real es她）’，所限制。即使是較大 外形要素的系統（例如個人電腦⑽、計算飼服器、與儲存 祠服器)也需要更多積體電路在相同或更小的“地產中”。 尤其激烈的是，對於可攜式個人電子產品（如：行動電話、 數位相機、音樂撥放器、.個人私 ^ 」 個人數位助理（pM)以及定位裝置 (1〇CatlQn-baSeddeviee))的需求進—步 於增 積體電路密度的需求。 β ^ 94512 200933763 增加的積體電路密度已導致可封裝超過一個積體電路 之多晶片（multi-chip)封裝件的發展。每一個封裝件均提供 個別積體電路之機械支持以及使該等積體電路能夠與周圍 電路系統電氣連接之一個或多個層之互連線（interc〇nnect line) ° 目前的多晶片封裝件（通常也被稱為多晶片模組）傳統 上由直接附接一組獨立的積體電路元件的印刷電路板（pCB〉
Ο 基板所構成。此類多晶片封裝件已被發現並用於增加積體 電路密度與微型化、改善信號傳遞速度、降低整體積體電 路尺寸與重量、改善效能、並且降低成本，這些都是電腦 產業之主要目標。 不論是垂直或水平排列之多晶片封裝件都可能造成問 題’因為其通常必須在該積體電路與舰電料接能夠被 測試之前被預先組合（pre_assembleh因此，當積體電路 被安裝和賴至多晶片模㈣，㈣的㈣電路與連接無 法被個酬試，且在結合絲大電路之前無賴別為已知 良品（kn.g00d-die，KGD)。因此，傳統的多晶片封裝件 Ϊ致組合製程的㈣問題。造翁（未則_射 罪度較低且較易產生組合缺陷（defect)。 此外 得統夕曰曰片封裝件中垂直堆叠的積體電路所道 成的問題超過水平排列的積體電路封裝件所造成者，進一 =使裝^^程更加複雜。更加難明試與決定該等個別彩 體電路的實際故障模式（actualfailuremc)de)。此外，翁 基板與㈣f路經常於組合麵試_受損喊製造㈣ 94512 5 200933763 . 更加複雜且成本更高。- 對於垂直與水平多晶片鉍肤μ 合必須具有在該等多 迕成、、亏执rL_ 匕封裒之積體電路的該囊封.製程可能 接=;Γ)或渗漏(b1，妨礙形 積體料姑件純中具有凹槽的 β係用以形成凹槽，:檨舍=槽(咖恤㈣舶心咖〉 :本於在囊封體中'需要的凹槽所設計特定之模製槽的製造 入二對於能夠提供低製造成本、改善的良率、改善 的叮讀、以及較大彈性以提供較多功能性與較少印刷電 路板^用面積的積體電路封裝件祕的需 0 求仍W維持不變。有鏗於對於節省成本與改善效率的需求 不斷增加，找出這些問題的解答是愈來愈關鍵。 上述該些問題的解決方案已為人們所長期尋找，但先 前的發展並未教示或建議任何解決方案，所以，這些問題 的解決方案已長期因惑熟悉本領域之技藝人士。 【發明内容】 ' .· 本發明提供一種積體電路封裝方法，包含··設置具有 接合墊與接觸墊的内插器（interp〇ser);於載體（carrier) 之上的偏移位置安裝該内插器，該載體具有與該載體之邊 94512 6 200933763 緣共平面的該内插器曝露侧（exposed side);在接令墊與 該載體之間建立電氣互連（electrical interconnect);以 及，在該載體與該電氣互連之上形成封裝件封囊封體，並 維持該接觸墊與該内插器的曝露側不被覆蓋。 本發明之一些實施例具有除了以上所述之外或替代以 上所ii的其他態樣。藉由閱讀下列之詳細描述並參考附 圖，熟悉本領域之技藝人士將明瞭該等態樣。 赢【實施方式】 © 以下實施例係充分詳細描述以使熟悉本領域之技藝人 士可製造及使用本發明。要了解基於此揭露内容可明瞭其 他實施例，而且’其系統、製程或機構上的改變可在不饽 離本發明之範疇下進行。 / - . 以下說明將提供許多明確的細節，使能充分了解本發 明。然而，很顯然地，本發明可於無該些明確細節下施行。 為了避免模糊本發明，一些習知的電路、系統組構與製程 © 步驟未詳細揭露。同樣地，用來顧示本系統實施例的附圖 係為局部示意圖而非按比例繪製，特別是某些圖式中的尺 寸是為清晰呈現而特別放大。一般而言，本發明可操作於 任何定向（orientation)。 此外，揭露及描述在多個實施例中的某些共同特徵， 為μ楚及容易說明、描述及理解，彼此相似及相同的特徵 通常將以相同的元件符號來描述。為便於描述，.實施例是 以第一實施例、第二實施例等予以編號，並非用以呈現其 他意義或用以限定本發明。 94512 7 200933763 為說明的目的’在此使用的用語“水平(h〇r 土 ζ〇ηta i)，， 係定義為與積體電路平行之表面或平面的平面，而無關於其 定向。用語“垂直（vertical)，，意指與剛剛定義之水平垂直 的方向。其他用語’諸如“以上”、“以下”、“、 “頂部，’、“側（如“侧壁，，），，、“較高，，、“較低，，、“上 面的（upper)”、“之上（over)”、以及“之下（under)”是 相對於談水平平面而定義。用語“在…之上（〇n)”係指在 Ο
元件間有直接接觸。在此使用的用語“處理 (processing)”，包含：材料的沉積、圖案化、曝光、顯影、 蝕刻、清理、模製以及/或是材料的移除或形成所描述結構 所需者。而在此使甩的用語系統（system)’’是依照使用該 用語之上下文而意指本發明的方法與設備。 現在參閱第1圖，顯示本發明第一實施例的積體電路 封裝件糸統100的上視圖。該上視圖描述不具有蓋子 (cover)的積體電路封裝件系統1〇〇。該上視调描述内插器 (interp〇Ser)102(如：基板）於栽體108(如：基板）之上具 有接觸墊104與接合墊106。該等接合墊1〇6可鄰近該内 插器102的未曝露侧no，其中’該未曝露侧11〇係位於 該載體108的内部之上。該内插器1〇2的曝露側112係與 該載體108的邊緣114共平面。該内插器102顯示於該載 體108之上的偏移位置’而不是位於該載體1〇8之上的中 央位置。該内插器1〇2係位於該載體丨〇8的右上角。 如圖所示’該接觸墊104並未被鄰近該未曝露側11〇 的周邊區域之上的防溢料結構116(諸如：非導電環氧樹 94512 8 200933763 月曰、选封劑、聚合材料、導線鎖樹脂（wire i〇ck resin) 材料、或可穿透薄膜黏著劑）所覆蓋。該等接合塾1 〇6與該 載體108之間可建立電氣互連118(如：接合線或帶狀接合 線（ribbon bond wire))。該防溢料結構116覆蓋該等電氣 互連118連接至該等接合墊1〇6處的該些端點（end) ^該防 溢料結構116係可選擇性使用的。 第一積體電路裝置120(如：積體電路晶片、已封裝的 ❹積體電路或内插器）安裝於該載體108之上。被動裝置 122(如：離散電阻器或電容器）安裝於該載體1〇8之上。雖 然要了解該等被動裝置122可互為不同，但為了說明的目 的，該等被動裝置122係以相同的元件類形顯示。舉例而 言，該等被動裝置122可包含不同的電阻器、電容器、電 感器或三者的結合。， 現在參閱第2圖，顯示該積體電路封裝件系統1〇〇沿 著第1圖之線2 — 2的剖面圖。該剖面圖描述該等被動裝置 ❹122被安裝於該載體1〇8之上。第二積體電路裝置224(如： 已封裝的積體電路裝）藉由黏著劑（adhesive)226安裝於談 載體108之上。. 該第二積體電路裝置224包含該内插器102為其基 板。如圖所示’該第二積體電路裝置224係位於該載體1〇8 <上的偏移位置β該内插器ι〇2的該等曝露侧m也是該 第積體電路裝置224的該等曝露侧。該第二積體電路裝 置224的該等曝露側112與該載體1〇8的該等邊緣114共 平面。該等電氣互連118可連接該内插器工⑽的該等接合 9 94512 200933763 墊106以及該载體108。舉例而言，如圖所示，該第二積 ，體電路裝置似為上下顛倒之組構並於遠離該載體1〇8的 一側具有内插器1〇2。 該防溢料結構116係位於該内插器1〇2的周邊區域之 上，而一部份該電氣互連118係位於該内插器1〇2之上。 該防溢料結構116與該第二積體電路裝置224可決定位於 該載體108之上的封裝件囊雜230的囊封體高度228。 ❹該防溢料結構116係可選擇性使用的，且如果存在該防溢 料結構116’可曝露出該内插器1〇2的該等接觸墊1〇4。如 果該防溢料結構116不存在，則該封襄件囊封體23〇係位 於該連接於該等接合墊106之電氣互連118之上且可曝露 出該等接觸墊104。 位於讓載體108之上的該封裝件囊封體23〇係覆蓋第 1圖之該第一積體電路裝置120、該等被動裝置122、該第 二積體電路裝置224、以及該等電氣互連ι18。該封裝件囊 © 封體230可在鄰近該防溢料結構116的區域形成將該内插 器102的該等接觸墊1〇4曝露出來的開口 232 ^外部互連 (external interconnect)234(如：錫球）可附接於該載體 108的底部。 安裝裝置2 3:6 (如：積體電路或被動元件）可選擇性地 安裝於該積體電路封裝件系銑100之上形成積體電路層疊 式封裝件系統(package-on-package system) °該安裝裝置 236以虛線描述。該安裝裝置236'可安裳於該内插器1〇2 之上以及該開口 232之内。 94512 10 200933763 ，要了解該實施例中所示的第1圖之該第-積體電路裝 置120、該第二積體電路裝置⑽、以及該安裝裝置236 ^ 為說明之目的。該第一積體電路裝置120、該第二積體電 路裝置224、以及該安裝裝置236可為晶.圓級晶片尺寸封 裝件（wafer level chip scaie package WLCSp)、線路重 佈（redistributed line，RDL)晶粒、陣列封裝件、無引腳 封裝件、具引腳封裝件、系統級封裝件（sy stem- i n-package ❹ SiP)、堆疊式晶粒封裝件、封裝件内封裝件 (package-in-package’ Pip)、嵌入式晶粒基板或散熱增益 封裝件、電磁干擾(EMI)防護封裝件。 現在參閱第3圖’顯示本發明第二實施例的積體電路 封裝件系統300的上視圖。該上視圖描述不具有蓋子的積 體電路封裝件系統300。該積體電路封裝件系統3〇〇可在 結構上類似於第丨圖之該積體電路封裝件系統ι〇〇或者可 相同於逆時針旋轉90度的該積體電路封裝件系統ι〇〇。 G 該上視圖描述内插器302(如：基板）於載體3{)8(如： 基板）之上具有接觸墊304與接合墊3〇6。該等接合墊3〇6 可鄰近該内插器302的未曝露侧310 ,其中，該未曝露侧 310係位於該賴3〇8的内部之上。該内插器3〇2的曝露 側312係與該載體308的邊緣314共平面。該内插器3〇2 顯示於該載體308之上的偏移位置，而不是位於該載體罵 之上的中央位置。該内插器3〇2係位於該載體3〇8的左上 角。 如圓所示，該接觸墊304並未被鄰近該未曝露侧31〇 94512 11 200933763 的周邊區域之上的㈣料結構316(諸如：料電環氧樹 脂、密封劑、聚合材料、導線鎖樹脂材料、或可穿透薄膜 黏著劑Μ覆蓋。該等接合墊306與該载體3〇8之間可建立 電氣互連318(如：接合線或帶狀接合線）。該防溢料結構 316覆蓋該等電氣互連318連接至該等接合墊識的該些 端點。該防溢料結構316係可選擇性使用的。
Ο 第-積體電路裝置32G(如：積體電路晶片、已封裝的 積體電路或内插器）安裝於該載體308之上。被動裝置 322(如：離散的電阻器或電容器）安裝於該载體·之 現在參閱第4圖，顯示該積體電路封裝件系統300沿 著第3圖之線4-4的剖面圖。該剖面圖描述第二積體電路 裝置424(如：已封震的積體電路）藉由黎著劑概安裝於 該載體308之上。㈣二積體電路裝置似包含該内插器 302為其基板。如圖所示，該第二積體電路褒置424係位 於該載體308之上的偏移位置。該内插器3()2的該等曝露 側312也是該第二積體電路裝置424的該等曝露側。該第 二積體電路裝置424的該等曝露侧312與該載體的該 等邊緣314，、平面。該等電氣互連318可連接該内插器观 的該等接合塾306 u及該載體3〇8。舉例而言，如圖所示， 該第二積體電路|置424為上下顛倒之組構並於遠離該載 體308的一侧具有内插器go?。 該防溢料結構316徐位於該内插器302的周邊區域之 上，而一部份該電氣互連318係位於諒内插器302之上。 該防溢料結構316與該第二積體電路裝置424可決定位於 94512 12 200933763 :該載體308之上的封裝件囊封體43〇的囊封體高度桃。 .=^Γ316係可選’且如果有在該防溢 枓…構316’可曝露出該内插器302的該等接觸墊3〇4。如 果該防溢料結構316不存在’則該封襄件囊封體430係位 於該連接於該等接合墊306之電氣互連318 出該等接觸塾編。 ^上且可曝露 ❹ /於該载體·之上的該㈣件囊封體崩係覆蓋第 :之該第—積體電路裝置32〇、第3圖 I【 =、該第二積㈣路裝置.W料電氣互連^置 件囊封體傷可在鄰近該防溢料結構316的區 =該内插器302的該等接觸墊3G4曝露出來的開口物。 ^連434(如：錫球）可附接於該載體3〇8的底部。 安(如積體電路或被動元件）可選擇性地 於該積體電路封裝件系統㈣之 : ❹ 二封裝件系統。該安裝裝置436以虛線描述積 挪可安裝於該内插請之上以及該開口 432之文内裝裝置 封= 5圖，顯示本發明第三實施例姆體電路 二的上視圖。該上視圖描述不具有蓋子的積 板）於恭辨、糸、500。該上視圖描述内插器502(如：基 ，Ωβ ； 5〇8(如·基板）之上具有接觸墊5〇4盥接人二 其令。該等接合墊5〇6可鄰近該内插器502的未曝露側二， =，該未曝綠51G係位於該賴__部之上。= μ内插g 502顧示於該载體508之上的偏移位置，而 94512 13 200933763 不是位於該載體508之上的中央位置。該内插器5〇2係位 - 於該載體508的右侧邊緣。 • 如圖所示，該接觸墊5〇4並未被鄰近該未曝露侧51〇 的周邊區域之上的防溢料結構516(諸如:非導電環氧樹 脂、密封劑、聚合材料、導線鎖樹脂材料、或可穿透薄膜 黏著劑）所覆蓋。該等接合墊506與該载體5〇8之間可建立 電氣互連518(如·接合線或帶狀接合線）。該防溢料結構 ❹516覆蓋該等電氣互連518連接至該等接合塾咖的該些 端點。該防溢料結構516係可選擇性使用的。 第一積體電路裝置520(如：積體電路晶片、已封裝的 積體電路或内插器）安裝於該載體5〇8之上。被動裝置 522(如：離散的電阻器或電容器）安裝於該載體5〇8之上。 雖然要了解該等被動裝置522可互為刊，但為了說明的 目的，該等被動裝置522係以相同的元件類形顯示。舉例 而。該荨被動裝置522可包含不同的電阻器、電容器、 ❹ 電感器或三者的結合。 . . ... —現在參閱第6圖，顯示該積體電路封裝件系統5〇〇沿 著第5圓之線6-6的剖面圖。該剖面圖描述該等被動裝置 522被女裝於該載體5〇8之上。第二積體電路裝置624(如： 已封裝的積體電路）藉由黏著劑626安裝於該載體5〇8之 上。' 該第二積體電路裝置624包含該内插器502為其基 板。如圖所示，該第二積體電路裝置624係位於該載體5〇8 之上的偏移位置。該内插器202的該等曝i：侧512也是該 14 94512 200933763 第二積體電路裝置624的該等曝露側。該第二積體電路裝 置624的該等曝露侧512與該載體508的該等邊緣514共 平面。該等電氣互連518可連接該内插器5〇2的該等接合 墊506以及該載體508。舉例而言，如圖所示，該第二二 體電路裝S 624為上下顛倒之組構並於遠離該載體5〇8的 一側具有内插器502 〇 該防溢料結構516係位於該内插器5〇2的周邊區域之 ❹ ❹ 上’帀一部伤該電氣互連518係位於該内插器5〇2之上。 該防溢料結構516與該第二積體電路裝置624可決定位於 該載體508之上的封裝件囊封體63〇㈣封體高度娜。 該防溢料結構516係可選擇性使用的，且如果存在該防溢 料結構516，可曝露出該内插器5Q2的該等接觸墊5〇4。如 果該防溢料結構516不存在，則該封|件囊封體63〇係位 於該連接於該等接合塾5Q6之電氣互連518之上且可曝露 出該等接觸墊504。 位於該載體5G8之上的該封裝件囊封體630係覆蓋第 _圖之該第㈣電路I置㈣、該等被動裝置娜、該第 =體電路裝置624、以及料電氣互連⑽。該封裝件囊 $ 3°可在鄰近該防溢料結構516的區域形成將該内插 RW 2的該等接觸塾5G4曝露出來的開口 632。外部互達 :护：球)可附接於該载體508的底部。 .女裝裝置 _壯## ▲ 如.積體電路或被動元件）可選擇性地 體電路封裝件系統棚之上形成積體電路層邊 工、’、統。該安襄裝置636以虛線描述。該安裝裝童 15 94512 200933763 636可安裝於該内插器502之上以及該開口 632之内。 • 現在參閱第7圖，顯示本發明第四實施例的積體電路 封裝件系統700的上視圖。該上視圖描述不具有蓋子的積 體電路封裝件系統700。該積體電路封裝件系統7〇〇可在 結構上類似於第5圖之該積體電路封裝件系統5〇〇或者相 同於旋轉180度的該積體電路封裝件系統5〇〇。 該上視圖描述内插器702(如：基板）於栽體7〇8(如： ❹基板）之上具有接觸墊704與接合墊706。該等接合墊 可鄰近該内插器702的未曝露侧710，其中，該未曝露侧 710係位於該載體708的内部之上。該内插器7〇2的曝露 側712係與該載體708的邊緣714共平面。該内插器702 顯不於該截體708之上的偏移位置，而不是位於該載體7〇8 之上的中央位置。該内插器7〇2係位於該载體7〇8的左側 邊緣。 如圖所示，該接觸墊7〇4並未被鄰近該未曝露侧71〇 ❹的周邊區域之上的防溢料結構716(諸如：非導電環氧樹 月曰费封劑、聚合材料、導線鎖樹脂材料、或可穿透薄膜 _著劑）所覆蓋。該等接合墊7〇6與該载體7〇8之間可建立 電氣互連718(如：接合線或帶狀接合線）。雜溢料結構 二 16覆蓋該等電氣互連718連接至該等接合塾·的該些 鳊點。該防溢料結構716係可選擇性使用的。 第一積體電路裝置720(如:積體電路晶4、已封裝的 積體電路或内插器）安裝於該载體7〇8之上。被動裝置 722(如：離散的電阻器或電容器）安裝於該載體7〇8之上。 94512 16 200933763 現在參閱第8圖，顳示該積體電路封裝件系統7〇〇沿 , 著第7圖之線8一 8的剖面圖。該剖®圖描述該等被動裝置 < 722被安裝於該載體708之上。第二積體電路裝置824(如： 已封裝的積體電路裝）藉由黏著劑826安裴於該載體7〇8之 上。 該第二積體電路裝置824包含該内插器702為其基 板。如圖所不，該第二積體電路裝置824係位於該載體7〇8 ❹，上的偏移位置。該内插器702的該等曝露側712也是該 第-積體電路裝置824的該等曝露侧。該第二積體電路裝 置824的該等曝露側712與該載體7〇8的該等邊緣HA共 平面。該等電氣互連718 T連接該内插器7〇2的該等接合 墊以及該載體7〇8。舉例而言，如圖所示，該第二積 電路裝置824為上下顛倒之組構並於遠離該載體雇的 一側具有内插器γ〇2〇 該防溢料結構716係位於該内插器702的周邊區域j 兮、耗該電氣互連718得、位於該内插器702之上£ 該載體：構716與該第二積體電路裝置824可決定位方 該防溢料姓^上的封裝件囊封體830 _封體高度828。 料結構311，可=出1 選擇性使用的，且如果存在_ 果該# 716^^器7G2的該等接觸塾704。女 於該連接於該等接合塾二體 出該等接觸塾7G4。 互連718之上且可曝1 V5載體708之上的該封裝件囊封體83〇係覆蓋第 94512 17 200933763 積體電路裝置720、該等被動裝置722、該第 二積體電路裝期衣 # n i «24、以及該等電氣互連718。該封裝件囊 封體830可在鄰讲吟 外近該防溢料結構716的區域形成將該内插 ^ 等接鵠墊704曝露出來的開口 832。外部互連 834(如··錫球）可 拉恶壯 附接於該載體708的底部。 接置震置, ^ (如.積體電路或被動元件）可選擇性地
$、於’/積體電路封裝件系統700之上形成積體電路層疊 ^封裝^統°該安裝裝置836以虛線描述。該安裝裝置 836 於該内插器7〇2之上以及該開口 832之内。 現在參閱第9圖’顯示本發明第五實施例的積體電路 封裝件錢_的上視圖。該上視圖描料具有蓋子的積 體電路封裝件系統_。該積體電路封裝件系統9〇〇可在 ^構上類似於第7圖之該積體電路封裝件系統_或者相
同於該積體f路縣件系統7⑽。舉—個特例來説，該積 體電路封裝件系統_可為兩個並列的該積體電路封裝件 系統700。 該積體電路封裝件系統9〇〇可包含多個覆蓋於載體 908之上的内插器9〇2。每—個内插器9〇2可包含與該載體 908的邊緣914共平面的曝露侧912。 現在參閱第10圖，顯示該積體電路封裝件系統9〇〇沿 著第9圖之線10—10的剖面圖。該剖面圖描述該積體電路 封裝件系統900可為兩個第7圖之積體電路封裝件系統 700 ’該等系統非彼此分離或彼此分割（singulate)。 安裝袭置1036(如：積體電路或被動元件）可選擇性地 18 94512 200933763 安裝於該積體電路封裝件系統900之上形成積體電路層疊 ' 式封裝件系統。該安裝裝置1036以虛線描述。該安裳裳置 1036可安裝於該内插器902之上以及該積體電路封裝件系 統900的開口 1032之内。 雖然要了解該積體電路封裝件系統900可包含不同的 積體電路封裝件系統，但為說明的目的，所示的該積體電 路封裝件系統900係具有兩個該積體電路封裝件系統 ❹ 70〇。舉例而言，該積體電路封裝件系統900可包含該積體 電路封裝件系統700與第5圖之該積體電路封装件系統 500，其中，該積體電路封裝件系統7〇〇不同於該積體電路 封裝件系統500。 現在參閱第11圖，顯示本發明實施例的第一中間 (intermediate)積體電路封裝件系統1100的上視圖。該上 視圖描述不具蓋子的第一中間積體電路封裝件系統11〇〇。 該第一中間積體電路封裝件系統1100包含位於複合载體 ❹ （comP〇site carrier)1108之上的複合内插器11〇2。該複 合内插器1102位於該複合載體1108的中央部分。 該複合内插器1102的接合墊11〇6與該複合載體11〇8 之間係建立電氣互連1118(如：接合線或帶狀接合線環 狀的防溢料結構1116可形成於該複合内插器110.2的周邊 區域以及連接至該等接合墊11〇6的該等電氣互連1118的 端點之上。多個被動裝置1122與多個第一積體電路裝置 1120安裴於該複合載體11〇8之上。 該第一中間積體電路封裝件系統u〇〇可分成四等份 19 94512 200933763 被描述。X轴方向與y軸方向的虛線將該第一中間積體電 路封裝件系統1100分成四等份。該等虛線也可代表用以分 割該第一中間積體電路封裝件系統1100的分割線un。 左下角的該四份之一部份可包含第丨圖之該積體電路 封裝件系統100。右下角的該四份之一部份可包含第3圖 之該積體電路封裝件系統300。右上角與左上角的該等四 分之一部份也都可包含進一步的積體電路封裝件系統 ❹1104 ,其中，該進一步的積體電路封裝件系統1104可類似 於或相同於該積體電路封裝件系統100或該積體電路封裝 件系統300。 現在參閱第12圖’顯示本發明實施例的第二中間積體 電路封裝件系統1200的上視圖。該上視圖描述不具蓋子的 第二中間積體電路封裝件系統1200。該第二中間積體電路 封裝件系統1200包含位於複合載體12〇8之上的複合内插 器1202。該複合内插器1202位於該複合載體12〇8之上半 ❹ 部與下半部的中央部分。 該複合内插器1202的接合墊1206與該複合載體1208 之間係建立電氣互連1218(如：接合線或帶狀接合線）。環 狀的防溢料結構1216可形成於各該複合内插器12〇2的周 邊區域以及連接至該等接合墊1206的該等電氣互連1218 的端點之上。多個被動裝置1222與多個第一積體電路裝置 1220安裝於該複合載體1208之上。 該第二中間積體電路封裝件系統12〇〇可分成四等份 被描述。X軸方向與y軸方向的虛線將該第二中間積體電 20 94512 200933763 路封裝件系統1200分成四等份。該等虛線也可代表用以分 , 割該第二中間積體電路封裝件系統1200的分割線1211。 左下角的該四份之一部份可包含第5圖之該積體電路 封裝件系統500。右下角的該四份之一部份可包含第7圖 之該積體電路封裝件系統700。右上角與左上角的該等四 分之一部份也都可包含進一步的積體電路封裝件系統 12〇4,其中，該進一步的積體電路封裝件系統12〇4可類似 Ο 於或相同於該積體電路封裝件系統500或該積體電路封裝 件系統700。 現在參閱第13圖，顯示第11圖在形成囊封體13〇2的 步驟中之結構。模製槽1304(如：平面或平坦的模製槽）可 ，於該防溢料結構1216之上。該模製槽13〇4也可位於模 製終止器（mold stop)1306(諸如：非導電環氧樹脂、密封 劑、聚合材料、導線鎖樹脂材科、或可.穿透薄膜黏著劑之 、、；止裔）之上。該模製終止器13〇6係可選擇性使用的。該 防溢料結構1216、該模製終止器13〇6、或者兩者的轉合能 夠緩和來自該模製槽1304的力量以避免損害該複合内插 器1102。該防溢料結構1116與該模製終止器13〇6均包含 彈丨生以補償該積體電路封裝件系統1〇〇在組合製程中的傾 斜(tilting)所導致的共面誤差（c〇planarity err〇r)。 該囊封體1302形成於載體帶（carrier s计丨口）13〇8之 上覆蓋第11圖之該等第一積體電路裝置112〇、該等被動 裝置1122以及該等包含複合内插器11〇2的複合第二積體 電路裝置131〇。該防溢料結構1116緩和或消除該複合内 94512 21 200933763 插器1102的該等接觸墊104之上的模製溢料。 復舉例而言’該模製槽1304可選擇性使用的。該模製 終止器1306可在模製製程中作為壩體（dam)(如：壩體填充 方法（dam-and-fill method))，其中，液態囊封體製程 ? (liquid encapsulation process)可被應用於該載體帶 1308之上以覆蓋該筹被動裝置1122、,該複合第二積體電路 裝置結構1310、以及該電氣互連1118〇該防溢料結構1116 ❹ 也可在該用以曝露該複合内插器1102的該等接觸墊丨〇4的 模製製程中作為壩體。 該防溢料結構1116也可選擇性使用的。如果該模製終 止器1306與該防溢料結構1116均不存在，則該模製槽1304 包含由虚線表示的延伸部份1314。該延伸部份1314避免 該囊封體1302形成於該複合内插器11〇2的該等接觸墊1〇4 之上。 該囊封結構1302可被虛線1316所分割’並形成例如 © 第2圖之該積體電路封裝件系統100與第4圖乏該積體電 路封裝件系統300。 現在參閱第14圖，顯示本發明實施例中用以製造該積 體電路封裝件系綠100的積體電路封裝方法14〇〇之流程 圖。該方法1400包含：於步驟1402，設置具有接合墊與 接觸墊的内插器；於步驟14〇4，在載體之上的偏移位置安 裝該内插器’該載體具有與該載體之邊緣共平面的該内插 盗曝露侧；於步驟>406，在接合墊與該載體之間建立電氣 互連；以及，於步驟1408，在該載體與該電氣互連之上形 22 94512 200933763 器的曝露倒不 成封裝件囊封體’並維持該接觸塾與該内.插 被覆蓋。 本發明之另一重要態樣係有用地支持並月 本、簡化系統、以及增進效能的歷史潮流。 降低成 本發明的這些以及其他有用的態樣因而促 態至至少下一層次。 連該技術狀 .因此，已發現本發明之該積體電路封骏件 ^ ❹ Ο 以改善良率、增加可靠度、以及降低電路系統的提供用 要與在此之前未知且無法取得的解決方案、萨力成本之耋 態樣。所產生之製程與組構係直接、具成本‘能 非常多功能、準確、靈敏、以及有效率的 曰’ 改進已知元件實現快速、有效且具經=4;:夠:: 以及利用的目的。 ^應用 心儘管本剌仙結合特定的最佳財㈣ 要了 ^有鏗於上述說明，許多的替代、修改與變化對孰悉本領 ^藝人士而言，將變得顯而易見。因此，並係傾向包 ^在本中請專利範圍内的所有此_代、修改、與 ^此提出或顯示於附圖中的内容係用於解釋本發明，而沖 用於限制本發明。 【圖式簡單說明】 目第1圖係本發明第，施例的積體電路封裝件系統的 上視圖； 第2圖係該積體電路封裝件系統沿著第、圖之 2的剖面圖； 94512 23 9 200933763 第3圖係本發明第二實施例的積體電路封裝件系統 的上視圖； 第4圖係該積體電路封裝件系統沿著第3圖之線4一 4的剖面圖； 第5圖係本發明第三實施例的積體電路封裝件系統 的上視圖； 第6圖係該積體電咚封裝件系統沿著第5圖之線6 — 6的剖面圖； ❹' 第7圖係本發明第四實施例的積體電路封裝件系統的 上視圖； 第8圖係該積體電路封裝件系統沿著第7圖之線8 —8 的剖面圖； 第9圖係係本發明第五實施例的積體電路封裝件系統 的上視圖； 第10圖係該積體電路封裝件系統沿著第9圖之線1〇 © ~ 10的剖面圖； /第11圖係本發明實施例的第一中間積體電路封裝件 系統的上視圖； 第12圖係本發明實施例的第二中間積體電路封裝件 系統的上視圖； 第13圖係第u圖在形成囊封體的步驟中之結構；以 及 第14圖係本發明實施例中用以製造該積體電路封裝 件系統的積體電路封裝方法之流程圖。 24 94512 200933763 【主要元件符號說明】 • 100、300、500、700、900、1100、1104、1200、1204、1400 , 積體電路封裝件系統 102、302、502、702、902 内插器 104、304、404、504、704 接觸墊 106、306、506、706、1106、1206 接合墊 108、308、508、708、908 載體 110、310、510、710 未曝露侧 ® 112、312、512、712、912 曝露侧 114、314、415、714、914 邊緣 116、316、516、716 防溢料結構 118、318、518、718、1118、1218 電氣互連 120、320、520、720、1220 第一積體電路裝置 122、322、522、722、1122 被動裝置 224、424、824 第二積體電路裝置 φ 226、626、826 黏著劑 228、428、628、828 囊封體高度 230、430、630、830 封裝件囊封體 232、432、832 開口 234、434、634、834 外部互連 436、636、836、1036 安裝裝置 1032 開口 1102' 1202 複合内插器 1108 複合載體 1111、1211 分割線 1116、1216 防溢料結構1302 囊封體 1304 模製槽 1306 模製終止器 25 94512 200933763 1308 載體帶 1310 複合第二積體電路裝置 1314 延伸部份 1316 虛線 1402、 1404 、 1406 、 1408 步驟 〇 26 94512

Claims (1)

  1. 200933763 七、申請專利範圍： • 1. 一種積體電路封裝方法，包括： ' 設置具有連結墊和接觸墊的插入件； 於載體上方的偏移位置安裝該插入件，且該載體的 邊緣與該插入件的曝露侧共平面； 於連結墊與該載體之間連接電性互連；以及 於該載體與該電性互連上方形成封裝件包覆體，且 該接觸墊和該插人件的該曝露側皆未被覆蓋。 ❹ 2.如申請專利範圍第1項之方法，其中，安裝該插入件包 含安裝具有該插入件的積體電路裝置。 3. 如申請專利範圍第1項之方法，其中： 設置該插入件包含： 設置具有該插入件的複合插入件；以及 於該載體上方的偏移位置安裝該插入件包含： 於具有該載體的複合載體上方安裝具有該插 Q 入件的該複合插入件。 4. 如申請專利範圍第1項之方法，復包括於該連結墊上方 的該電性互連的一部份上方形成防溢料結構。 5. 如申請專利範圍第1項之方法，復包括於該載體上方安 裝第一積體電路裝置。 6. —種積體電路封裝件系統，包括： 載體；; 插入件，係具有連結墊和接觸墊，且於該載體上方 的偏移位置，該載體的邊緣與該插入件的曝露侧共平 27 94512 200933763 面； _ 電性互連，係於連結墊與該載體之間；以及 封裝件包覆體，係於該載體和該電性互連上方，且 該接觸墊和該插入件的曝露侧皆未被覆蓋。 7. 如申請專利範圍第6項之系統，其中，該插入件係包含 於積體電路裝置中。 8. 如申請專利範圍第6項之系統，其中： 該插入件係包含於複合插入件中；以及 該載體係包含於具有該複合插入件安裝於其上方 的複合載體中。 9. 如申請專利範圍第6項之系統，復包括於該連結墊上方 的該電性互連的一部份上方的防溢料結構。 10. 如申請專利範圍第6項之系統，復包括於該載體上方的 第一積體電路裝置。 ❹ 28 94512
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US8084849B2 (en) 2011-12-27

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