TW200919595A - Method of manufacturing semiconductor device - Google Patents

Method of manufacturing semiconductor device Download PDF

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Publication number
TW200919595A
TW200919595A TW096140924A TW96140924A TW200919595A TW 200919595 A TW200919595 A TW 200919595A TW 096140924 A TW096140924 A TW 096140924A TW 96140924 A TW96140924 A TW 96140924A TW 200919595 A TW200919595 A TW 200919595A
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TW
Taiwan
Prior art keywords
semiconductor device
substrate
filler
opening
wafer
Prior art date
Application number
TW096140924A
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English (en)
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TWI350572B (zh
Inventor
Shiann-Tsong Tsai
Original Assignee
United Test Ct Inc
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Publication date
Application filed by United Test Ct Inc filed Critical United Test Ct Inc
Priority to TW096140924A priority Critical patent/TW200919595A/zh
Priority to US12/075,936 priority patent/US7772034B2/en
Priority to KR1020080023815A priority patent/KR101056944B1/ko
Publication of TW200919595A publication Critical patent/TW200919595A/zh
Application granted granted Critical
Publication of TWI350572B publication Critical patent/TWI350572B/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Description

200919595 九、發明說明： 【發明所屬之技術領域】 本發明係有關於-種半導體裝置之製法 係有關於一種覆晶式半導體裝置之製&。 … ， 【先前技術】 覆晶式（FnP Chip)封裝結構為—種先 ;技：，其與-般習知之打線式封裝結構最主Li 置於基板上，觸㈣數㈣⑽_)而銲結與電性^ 指基板上。由於覆晶式封裝結構中不需使用較佔空間之= 線（B0nding Wires)將半導體晶片電性連接至基板，; 可使整體封裝結構更為輕薄短小，同所 請參閱第U至跡係顯示傳統覆晶式電構 製法示意圖。 < 如第1A圖所示，首先係提供一基板！與一晶片2， 該基板1具有第一表面1〇，該第一表面1〇形成有複數電 性連接墊11，該晶片2具有主動面2〇與非主動面21，且 於該主動面20形成有複數凸塊22。 如第1B圖所示，以晶片倒置方式將該晶片2接合於 該基板1上，並使該凸塊22與該電性連接墊u相互電性 連接。 如第1C圖所示，進行底部填膠（Underfiiled)作業， 以將填充材料23填入該晶片2主動面20與該基板i第一 表面10間之凸塊間。 Π0551 5 200919595 如S Η)圖所示，復以封裝模壓製程㈤ 晶片2之非主動面21與該基板i之第 、忒 裝膠體24,以將該晶片2、凸堍==1°形成有封 面1〇包覆於其中。 凸塊22與該基们之第—表 如上所述，該m封裝結構主㈣使w 2 凸塊22直接電性連接至該基板！之電性連接塾⑴而^ =封裝結構具有較佳電性連接品f，但該製法中 ^ :部填膠的步㈣使得該覆晶切I結構之製法^ 化’進而影響其製程效率。 系複 /制蓉於前述問題，請參閱第2A至2C圖，係顯示 化衣耘之覆晶式封裝結構之製法示意圖。 如第2A圖所示，首先提供_基板3盘一 基板3具有第一表面3〇，該 /、 ’或 性連接塾31，並於該 二面30上形成有複數電 表面3 0貼附異方性導電接人暮 ^CAn1S〇tr〇picC〇nductlve Paste/Fllm；ACp；tc；； 3成接合層32,該接合層32中具有導電粒子切，且 4具有主動面4G與非主動面41，於該主動面40 上形成有複數凸塊4 2。 如弟2B,圖所不，以晶片倒置方式將該晶片*接合至 二土反3並使該Β曰片凸塊42係藉由該導電粒子321電 性連接至該基板電性連接墊31。 如第2C圖所不’復以封裝模壓製程（肋⑻叫)於該 日日片4之非主動面41盘古玄其起 谬膠體43,以將★亥曰片3〇形成有封 日日片4、凸塊42與該基板3之第一表 110551 6 200919595 面•覆於其中。 雖‘述之製法可利用該異方性導 部封膠的步驟， J包接合膏/膜省略底 丁/的戈驟，進而簡化該封裝結 導電接人喜/13“ AA你』A 再<衣狂，但該異方性 經濟效益。 s力衣私成本，而不符 另外，於使用該異方性導電接合暮 該晶片4盥嗲美叔ς#入 要口 朕軒，為了增強 一忑基板3之結合性，須於 —
進行粗糙化之牛砰,, 、、^基板弟一表面3G 瑣。之步驟’如此使得該封I结構之製程更加繁 封裝、基板之間電性連接關係、簡化 題。 衣_及降低$程成本’為當今料思考之課 【發明内容】 鐾^上所述習知技術之缺點，本發明之— k供—種可簡化製程之半導體裝置之製法。 、 旦本务^之又-目的為提供—種可使半導體褒置大 里產之半導體裝置之製法。 士發Θ之3 -目的為提供—種可降低 合經潸效益之半導體裝置之製法。 奉且付 =達上揭目的’本發明提供—種半導體裝置之製法， '丁、匕括.提供一基板盘— ^ ^ „ 楚士 /、日曰片，該基板具有第一表面，該 t表面形成有複數電性連接塾且覆蓋有一絕緣層，該絕 鉻出该電性連接墊，該晶片具有主動面與 面’於該主動面形成有&塊；於該基板第一表面上 11055] 7 200919595 -兄材，以及壓合該晶片與基板，且使該凸塊與該# 性連接墊相互電性連接，並使該填充材分佈於該晶片、= 板之間，以形成填充層。 土 w述製法中復可於該絕緣層的表面與該晶片的非主 動面形成有封裝膠體，以包覆該晶片及凸塊；該壓合 可為熱壓合與熱聲波壓合之其中一者；該填充材為可印: 的B階段底部填膠/晶月貼附材料⑻財齡b underf ill/dle attached material ) ^ T ^ £p 二t、旋塗等方式塗佈於基板第-表面上，並加熱形 成B階段（B-stage)之特性。 該填充材的印财包括於縣板料層上 楔板，該模板形成有至少— /珉有至一開孔以露出該絕緣層表面，該 二開別位於綱σ的兩侧，於該開孔中印刷有填充 移缝除該模板’俾使該絕緣層上形成有填充材，且 =絕緣層開口，再加溫棋烤該填充材為"皆段 ，朝向該開口突伸之二相二的一侧之卡央處形成有 方向流動。 …使該填充材能迅速朝向該開口 充材另一設置方式係於該基板絕緣層上設置-核板，该拉板形成有開孔以露 開口中之電性連接墊;於該開孔; 除該模板，以使該絕緣層上二充材，·以及移 加溫烘烤該填充材W階段厂開口中形成有填充材，並 如上述之製法，其較佳應用方式係使用於製造雙倍資 110551 8 200919595 1傳輪率動態隨機存取記憶體（D〇uble Data以悅 Dy細nic Random ACCess Mem〇ry ;醒 DRM )，特別是 DDRIII 以及 DDRIV。 另外，該填充材為可印刷的β階段底部填膠/晶片貼 附材料，而使其具有較佳之黏著性，故該晶片與該基板相 互…σ ，忒基板之第—表面無須特地粗糙化或平坦化， 該晶片與該基板之間可藉由該填充材，而具有較佳之結合 性。 〇 士糟由預先印刷該填充材，以於晶片與基板相互結合 時’該填充材係填滿該基板與該晶片之間的空隙，並凝固 成為填充層，而可省略底部填膠的步驟，並且該填充材較 異方性導電接合獏為便宜，如此可降低製作半導體裝 置之材料成本’並運用於量產半導體裝置，進而符合經声 效益。 η 【實施方式】 以下係藉由衫的具體實施例說明本發明之實施方 式’所屬技術領域中具有通常知識者可由本說明書所揭示 之内谷輕易地瞭解本發明之其他優點與功效。 μ爹閱» 3Α至3Η圖’係顯示本發明半導體裝置之勢 法之第一實施例之示意圖。 、 括提：第其3?:斤示，本發明之半導體裝置之製法，係包 ^ί、-基板5,該基板5具有第—表面5 5〇形成有複數電性連接塾51，且於該第一表 —絕緣層52，該絕緣層Μ形成有開口⑽以露出該^ 9 11055] 200919595 性連接墊51。 如第3B圖所示，於該絕緣層52上設置一模板53， 該模板53形成有至少二開孔530以露出該絕緣層52表 面，該二開孔5 3 0係分別位於該開口 5 2 0的兩侧。 如第3C圖所示，於該開孔530中印刷有填充材54， 該填充材54例如為可印刷的B階段底部填膠/晶片貼附材 料（Printable B-stage underfill/die attached material )° 如第3D、3E圖所示’移除該模板53，以於該絕緣層 52上形成有填充材54，且外露出該基板開口 52〇 ,並將 該填充材54加溫烘烤，以使該填充材54形成為 B Stage，其中該填充材54係分別位於該開口 52〇之兩 側’並且該填充材54相鄰該開口 520的一側之中央處形 成有朝向該開口 520突伸之尖端540。 如第3F圖所示，復提供一晶片6，該晶片6具有主 動面60與非主動面6卜於該主動面6()幼對於該基板 電性連接墊51位置處固設有凸塊62。 如第3G圖所示，將該晶片6與該基板5相互壓人， 式可為熱壓合(the一_ι〇η)或熱；波 凸以2rrs〇nic CGmpressiGn)之其中—者，並使該 到廢力㈣"151相互接合，料該填崎5 4受 突伸，二： 該尖端540係朝向該開口 52。 流體之毛充材54受到該尖端540的引導，並且受到 ’、、田現象與該晶片6之磨迫’該填充材54會大部 110551 10 200919595 « · 分朝向該開口 52〇士人 另位於該開口 520中之H動’並且填滿該開口52 〇 ’ π右搐▲ U 工氣b为別由該開口 520之相對未 二/= 54之方向排出，待該填充材54填滿該開口 布於該晶片6與基板5之間且凝固成型，以形成 一填充層55。 f 52的Γ圖所不’進行封裝模壓步驟，以於該絕緣層 5::表面與該晶片6的非主動面61形成有包覆晶“及 凸塊62之封裝膠體μ。 機存係可應用於製作雙倍資量傳輸率動態隨 機存取仏體（D〇uble Data Rate ―仏^⑽
Me瞻^DDR_)，特別是· ΠΙ以及讀⑴ :於該晶片6與該基板5之間係藉由該凸塊β2盘電 接連：：5"目互電性連接’而使二者具有較佳電性連 …二该晶片6與該基板5結合時，受到該晶片6 /基板5的壓迫的填歸54會填滿該W 6與該 之的空隙’並且凝固成型為填充層55,故可省略底邛 之、膠的步驟，以簡化半導體裝置的製程及降低成本。-σ 該填充材54係為續段底部填膠/晶片貝占附材料，贫 ^具有較佳的黏著性，因此不須額外對該基板5的第一 、面50進行粗糖化，並藉由具有較佳的黏著性之谊充材 5 4，而使該基板5與該晶片6具有較佳的結合性，另外， 该填充材5Μ目較於異方性導電接合#/職為便宜。 置之己合ΐ考第4"至41)圖’係顯示本發明半導體裝 置之衣法弟二貫施例之示意圖’於本實施例與前述實施大 110551 11 200919595 致才目同，主要差異係在填充材設置區域之不同。 如第4A圖所示’該基板5a之第一表面5〇a具有如第 具施例之電性連接墊51a與絕緣層52a，該絕緣層52a 形成有開口 520a以露出該些電性連接墊51a，並於該絕 緣=52a上設置一模板53a，該模板53a形成有開孔53〇a 以露出該絕緣層52a部分表面與位於該開口 52〇a中之該 些電性連接墊51 a。 如第4B圖所示’於該模板開孔53〇&中印刷有填充材 54a，以使該填充材54a分佈於該絕緣層52&之部分表面 上與该基板開口 520a中。 如第4C圖所示，移除該模板53a，並加溫烘烤（即 B-Stage烘烤）該填充材。 f第4D圖所示，將-主動面60a具有凸塊62a之晶 …亥基板5a相互壓合，並使該凸塊62&與電性連接塾 a曰相互接合，此時受壓、受熱之填充材…即會充佈於 μ曰曰片6a與該基板5a之間， 心:即可進行__(咖，為填充層 底/"V4 ’本發明係则預先塗佈之可印刷的B階段 :=二貼附材料為填充材54*_^ b4a Τ間化$知覆晶結構 須之繁複步驟，並且㈣的底錢，之步驟所 晶結構中所使用的里=生〜54、54a之價格亦較習知覆 相較於習知覆晶結構二接合膏/膜為便宜，因此， 經濟效益的製裎。 x明係可運用於大量量產且更具 110551 12 200919595 惟以上所述之具體實施例，僅係用以例釋本發明之特 點及功效，而非用以限定本發明之可實施範疇，在未脫離 本發明上揭之精神與技術範疇下，任何運用本發明所揭示 内容而完成之等效改變及修飾，均仍應為下述之申靖 範圍所涵蓋。 【圖式簡單說明】 .第1A至1D圖係顯示習知半導體裝置之製法之示意 意圖； 第2A至2C圖係顯示另一習知半導體裝置之製法之示 第3A至3H圖係顯示本發明之半導體裝 實施例之示意圖；以及 弟4 A至4 D圖係顯示本發明之半 實施例之示意圖。 【主要元件符號說明】 導體裝置之製法第二 !〇、30、50、50a 第一表面 U、31、51、51a電性連接墊 2 ' 4 ' 6、6a 晶片 2〇、40、60、60a 主動面 21、40、61 非主動面 22 ' 42、62、62a 凸塊 23 填充材料 32 接合層 110551 13 200919595 321 導電粒子 52 ' 52a 絕緣層 520 、 520a 開口 53 、 53a 模板 530 ' 530a 開孔 54 、 54a 填充材 55 、 55a 填充層 63 封裝膠體
14 110551

Claims (1)

  1. 200919595 ;申請專利範圍： -種半導體裝置之製法，係包括： 提供基板與晶片，該基板具有第—表面 表面具有複數電性連接墊 ^一 層形成有開口以露出該電性連接；心緣層，该絕緣 動面與非主動面1主墊，且該晶片具有主 主動面s又有複數凸塊； =該基板第—表面上形成填充材；以及
    2.
    壓合該晶片與基板，以電 連接墊，並使触絲八# 接該Λ塊與該電性 Γ 佈於該晶W基板之間而形 成填充層，以製得半導體裝置。 t申請專利範圍第1項所述之半導體裝置之製法，復 ^ ’於該絕緣層的表面與該晶片的非主動面形成有 I復該晶片及凸塊之封裝膠體。 如申明專利乾圍第i項所述之半導體裝置之製法，其 中，該填充材之形成方式係包括： /、 於4基板第-表面之絕緣層上設置一模板，該模 板形成有至少二開孔以露出該絕緣層表面，該二開孔 係分別位於該開口的兩側； 於該開孔中印刷有填充材；以及 移除該模板，以於該絕緣層上形成有填充材，且 露出該基板開口，再加溫供烤該填充材。 4. 如申4專利範圍第3項所述之半導體裝置之製法，其 中，該填充材經溫烘烤而為B階段（B_Stage )。 5. 如申凊專利範圍第3項所述之半導體裝置之製法，其 15 Π0551 200919595 Lit:::，該開口的-側之中央處形成有朝向 方向流動。*端，以使該填充材能迅速朝向該開口 6· t申請專利範圍第1項所述之半導體裝置之製法，並 中’该填充材之形成方式係包括： - 於該、，、巴緣層丨設置一模板，該模板 露出該基板％续® γ * Ί f L u 枚、，巴緣層之部分表面與位於該基板 之該電性連接墊； r 於該開孔中印刷有填充材；以及 、移除該模板，以於該絕緣層上與該基板開口中形 成有填充材，再加溫烘烤該填充材。 如申明專利範圍第5項所述之半導體裝置之製法，其 8. 中，邊填充材經溫烘烤而為B階段（Β-Stage)。 如申請專利範圍第丨項所述之半導體裝置之製法，其 1..., 中該壓合方式可為熱壓合與熱聲波壓合之其中一 者。 9. 如申请專利範圍第1項所述之半導體裝置之製法，其 中，該填充材為可印刷的β階段底部填膠/晶片貼附 材料（Printable B-stage underfill/die attached material )° 10‘如申請專利範圍第丨項所述之半導體裝置之製法其 中，該半導體裝置為雙倍資量傳輸率動態隨機存取記 憶體（Double Data Rate Dynamic Random Access Memory ； DDR DRAM )° 110551 16
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KR20090044963A (ko) 2009-05-07
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