TW200834767A - Method of packaging a semiconductor device and a prefabricated connector - Google Patents

Method of packaging a semiconductor device and a prefabricated connector Download PDF

Info

Publication number
TW200834767A
TW200834767A TW096138316A TW96138316A TW200834767A TW 200834767 A TW200834767 A TW 200834767A TW 096138316 A TW096138316 A TW 096138316A TW 96138316 A TW96138316 A TW 96138316A TW 200834767 A TW200834767 A TW 200834767A
Authority
TW
Taiwan
Prior art keywords
connector
layer
major surface
forming
dielectric layer
Prior art date
Application number
TW096138316A
Other languages
English (en)
Inventor
Marc A Mangrum
Kenneth R Burch
Original Assignee
Freescale Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Freescale Semiconductor Inc filed Critical Freescale Semiconductor Inc
Publication of TW200834767A publication Critical patent/TW200834767A/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/71—Means for bonding not being attached to, or not being formed on, the surface to be connected
    • H01L24/72—Detachable connecting means consisting of mechanical auxiliary parts connecting the device, e.g. pressure contacts using springs or clips
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81909—Post-treatment of the bump connector or bonding area
    • H01L2224/8192—Applying permanent coating, e.g. protective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/9202—Forming additional connectors after the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electroplating Methods And Accessories (AREA)

Description

200834767 九、發明說明： 【發明所屬之技術領域】 本發明大體係關於半導體裳置，且更特定言之 係關於將半導體裝置與預先製造連接器一同封裝。* 【先前技術】 通常地，將裝置封裝以在接竹卩目，τ 呆作期間受到保護。此等經封 裝之裝置被置放在一具有复仙驻恶 c 另，、他裝置之印刷電路板（PcB)
寸。在許多情況下’需要額外功能性同時亦提供連接之簡 易’生。舉例而§ ’可能需要提供一需要最少(若有的話)製 造之至半導體裝置的連接。因此，存在對於一種可提供連 上。具有裝置之PCB用於諸如電腦或蜂巢式電話之產品 中。因為期望減小諸如電腦及蜂巢式電話的產品之尺寸， 故需要在不損失功能性的情況下減小p c B及封裝裝置之尺 接之簡單性同時具有半導體封裝之至少某些其他利益之封 裝方法的需要。 【發明内容】 在一態樣中，一半導體裝置及一預先製造連接器共同形 成於一單一封裝中。一預先製造連接器之一插腳被鄰近於 一晶種層置放，且一隨後的電鍍步驟促使鍍層（plating)與 該插腳實體接觸及電接觸。鍍層亦與半導體裝置電接觸， 使得在該插腳與該半導體裝置之間形成電接觸。一隨後的 絕緣層沈積提供將連接器與半導體裝置固持在一起之實體 支撐。 【實施方式】 125146.doc 200834767
展示於，中的係一工件10，其包含一除頂面外全部由 二絕緣層Μ所圍繞的半導體裝置12 4由虛線咐示的係 一界定-分離區域的分離邊界。此展示工件1()將在何處與 可與工件10相同或不同的其他工件分開。圖1〇中之整體結 構係用於-自置放於—容器中的複數個分離晶粒逐步製: -封裝的製程。將具有觸點之側面貼膠帶以保護觸點。在 觸點朝下之組態中，使一材料在該複數個晶粒上流動。 在固化該材料之後，將由該材料固持在一起的作為一單元 之複數個晶粒自容器移除並且移除膠帶。㈣的絕緣層及 導電層之沈積步驟形成封裝積體電路。流動而形成絕緣層 14的材料在圖丨之實例中較佳係一聚合物，但也可使用諸 如環氧樹脂的另一材料。聚合物在此情況下係較佳的，因 為將形成穿過其之通道。若不穿過其形成通道，則環氧樹 脂或許係較佳的，因為其可能更具成本效益。對於此類型 之封裝而s ’聚合物對於具有通道之絕緣層通常為較佳 的’且環氧樹脂對於不具有通道之絕緣層通常為較佳的。 具有通道之層通常係約20微米。厚度亦可為多於或少於彼 i ’且尤其可視需要使其顯著更大。半導體裝置12具有暴 露在一個主表面（上表面）上之觸點18、20、22及24。另一 主表面（底表面）具有覆蓋其之絕緣層14。絕緣層14圍繞其 他侧面。 展示於圖2中的係當在半導體裝置12之上表面上沈積一 絕緣層26及形成穿過絕緣層之通道28、30、32及34以分別 暴露觸點18、20、22及24之後的工件1〇。 125146.doc 200834767 展示於圖3中的係當形成分別在通道28、3〇、32及34 中、在絕緣層26上且分別與觸點18、2〇、22及24接觸的晶 種層36、38、40及42之後的工件10。晶種層36、38、40及 42係以習知晶種層方式形成，即沈積一薄金屬層，該薄金 屬層隨後被使用習知的遮罩及蝕刻技術來選擇性地蝕刻。 通道可為約100微米，但其亦可顯著地不同於該量。 展示於圖4中的係當藉由電鍍執行金屬沈積之後的工件 1〇 ’電鍍促使在晶種層36、38、40及42分別存在之處形成 導電層44、46、48及50。 展示於圖5中的係當在半導體裝置12之上表面上形成（較 佳藉由沈積）一絕緣層52之後的工件1〇。絕緣層52在整個 分離區域、絕緣層26及導電層44、46、48及50上延伸。在 沈積絕緣層52之後，將工件1 〇翻過來，且形成穿過絕緣層 14及16的通道54及56，以分別暴露導電層44及50，如當面 朝半導體裝置12之底表面檢視時。 展示於圖6中的係當形成分別在通道54及56中、在絕緣 層14上且分別與導電層44及50接觸的晶種層58及60之後的 工件10。 展示於圖7中的係當在晶種層58及60存在之處形成導電 層62及64，在絕緣層14及導電層62及64上整個分離區域中 形成一絕緣層66，及穿過絕緣層66形成通道68及70以分別 暴露導電層62及64之後的工件10。可將通道68及70的形成 延遲到稍後在製程中進行。 展示於圖8中的係當在絕緣層66及通道68及70上施加膠 125146.doc 200834767 帶72以在隨後處理期間保護導電層62及64之後的工件ι〇。 隨後將工件_過來以用於在半導體裝置12之上表面上的 處理。 展不於圖9中的係當形成通道74及％以分別暴露導電層 46及48，及形成分別在通道74及76中、在絕緣層52上且分 別與導電層46及48接觸的晶種層78及8〇之後的工件1〇。 展示於圖1〇中的係具有一預先製造連接器82的工件10， 該預先製造連接器82具有分別與晶種層78及8〇接觸的插腳 84及86。在此實例中，晶種層78及8〇自通道”及％充分延 伸向插腳84及86以確保能夠被置放在導電層以及“上。若 能夠確保插腳84及86具有其位置之充分確定性，則一替代 方案疋將通道74及76製作得足夠大以用於收納插腳84及 86。在本文中一預先製造連接器意謂一能夠在連接器之兩 側面之間提供電連接的單元，在連接器中，至少一側面能 夠提供實體支撐以藉由摩擦力、壓力或某些其他易可逆之 手段來維持與另一連接器的電接觸。因而，不需要一焊接 技術（諸如使用焊料）來維持連接器間接觸。如圖1〇中所展 示’一保護盍8 8覆蓋亦具有實體支撐以維持電接觸之連接 器82之區域的電觸點。 展示於圖11中的係在執行一電鍍步驟之後的工件1〇，該 電鍍步驟具有在晶種層78及80及插腳84及86上沈積金屬以 分別在晶種層78及80上及分別在插腳84及86四周形成導電 層90及92之效應。作為一替代，鄰近於連接器82之一本體 部分的插腳84及86之一部分可以一絕緣體來塗佈，使得鍍 125146.doc -10· 200834767 。視連接器而定，將鍍層與連 層將不延伸至連接器之本體 接器之本體_對於可靠性目素*言可為有利的。 工件1〇。此保料電㈣及92且提供隸料制82固持 在適當位置中之實體支撐。 展不於圖12中的係當在絕緣層52及導電層列及％上整個 分離區域中且沿著連接器82之侧面沈積-絕緣層94之後的 展示於圖13中的车者兹… 糸田移除膠帶72，形成分別與導電層62
及64接觸之焊球96及98，執行分離，及移除㈣蓋88之後 的工件10。隨後工件10準備好安裝於一電子產品中。可將 ㈣蓋留在連接器82上。在電針，對於晶種與鍍層兩者 而言’較佳金屬係銅。在形成焊球的情況T，在形成諸如 焊球96及98之焊球前，在銅上提供一介入層，諸如鎳-金 (NiAu)或一犧牲保護塗層可為有益的。 展示於圖14中的係一工件1〇〇，《包含一除了一頂面外 全部由一絕緣層104所圍繞的半導體裝置1〇2，及一放在位 於半導體裝置102與分離線114之間之絕緣層1〇4之一部分 上的連接器116。舉例而f，連接器116藉由（例如）膠帶黏 附地固持至絕緣層104。又由虛線114展示的係界定一分離 區域的分離邊界。半導體裝置具有暴露於一上表面上的觸 點106、108、11〇及112。連接器116具有在絕緣層1〇4上方 自連接器本體橫向延伸的插腳118及12〇。插腳12()自絕緣 層1〇4之上表面的高度係高於插腳118。一保護蓋122覆苗 具有實體支撐以維持電接觸之連接器116之侧面上的電觸 125146.doc • 11 - 200834767 展示於圖15中的係當在半導體裝置1〇2之上表面上，在 絕緣層！04上’及在連接器124四周沈積—絕緣層124之後 的工件100絕緣層丨24為連接器116提供實體支撐。絕緣 層124的厚度係與插腳118高於絕緣層1〇4的高度一樣大。 在沈積製程中，絕緣層124之一薄層係有可能位於插腳ιΐ8 上。在此時，在沒有遮罩之情況下執行各向同性蝕刻以移 除位於插腳118上之絕緣層之部分可為有益的。此將減小 絕緣層124之厚度，但可選擇絕緣層124之初始厚度以考慮 到回餘。 展示於圖1 6中的係穿過絕緣層124形成通道i 28、13 0、 132及134以暴露觸點1〇6、log、及112之後的工件 1 00 °又’在通道形成期間，插腳1丨8之側面經暴露以確保 自彼等側面移除絕緣層124，使得可形成至插腳〗丨8的電接 觸。在此實例中，插腳12〇與插腳118對準使得移除插腳 118上之絕緣層124困難。一具有垂直偏移之插腳的連接器 將允許方便地自插腳124之頂面移除絕緣層124。為確保暴 露插腳124之側面，進行對絕緣層124之某種蝕刻，導致一 鄰近於插腳11 8之側面的洞126。此洞可延伸至絕緣層104 但僅僅到達絕緣層104。 展示於圖17中的係當形成分別在通道128、130、132及 134中，在絕緣層124上且分別與觸點106、108、110及112 接觸的晶種層136、138、140及142之後的工件100。晶種 層136延伸至插腳118(包括其側面）。 展示於圖18中的係當電鍍以在晶種層136、138、140及 125146.doc -12 - 200834767 142分別存在之處形成導電層M4、146、148及150之後的 工件1〇〇。此展示導電層U4係與插腳118接觸。 展示於圖19中的係當在導電層144、146、148及150上、 在絕緣層124上，及在連接器116四周形成一絕緣層152之 後的工件100。絕緣層152為連接器U6提供支撐。 展示於圖20中的係當形成分別與導電層146、148及15〇 接觸的導電層154、156及158之後的工件。此係如先前所 描述藉由形成通道及晶種層，接著電鍍來達成。在此實例 中，歸因於在暴露遮罩以選擇性移除晶種層之部分的微影 術期間自插腳120的屏蔽，亦有可能在插腳12〇之下形成一 導電層160。導電層160由絕緣物圍繞且不應對電效能具有 不利的影響。亦展示於圖20中的係當在絕緣層j52上，在 導電層154、156及158上，及在連接器116四周形成絕緣層 162之後的工件1 〇〇。絕緣層！ 62為連接器i i 6提供實體支 撐。此亦展示在插腳120上的絕緣層162之一部分。就插腳 118而言，此部分絕緣層162可藉由各向同性蝕刻來移除。 展示於圖2 1中的係當形成類似於與插腳1丨8接觸之導電 層144的與插腳120接觸之導電層164之後的工件1〇〇。亦展 示的係分別與導電層156及158接觸的導電層166及168。 展示於圖22中的係當在導電層164、166及168上，在絕 緣層162上，及在連接器116四周形成絕緣層17〇之後的工 件100。亦展示的係暴露導電層166及168之通道開口。 展示於圖23中的係當形成分別與導電層166及ι68接觸的 焊球172及174，在線114上分離，及移除保護蓋122之後的 125146.doc •13- 200834767 工件100。在此情況下，導電層166及168具有一可被當作 可焊觸點的暴露部分，且與連接器在相同的側面上。導電 層可以與圖1至圖13中所展示相同之方式來完成，使得具 有一嵌入一所得封裝積體電路中之連接器（如連接器116)的 可焊觸點可與連接器在相對面上。類似地，圖13中的工件 10可在與以圖14至圖23中所展示之方式形成的連接器相同 的側面上具有可焊觸點。又，連接器及可焊觸點可相對於
彼圖示而倒轉。因#，連接器116抑或連接器82可位於晶 粒之底面而非所展示之頂面。 因而，所展不的係可將一預先製造連接器嵌入一所得封 裝積體電路中’在該所得封裝積體電路巾，連接器經電連 接至半導體裝置；亦展㈣在工件之外部的可焊觸點連接 至半導體裝置。 在刚述說明書中，已參看特定實施例描述本發明。然 :-般技術者瞭解到，可在不脫離陳述於下文中請專利 耗圍中的本發明之範•的情況下作出各種修改及改變。舉 例而言，連接器經展示為具有直的邊緣，但連接器可具有 鋸W邊緣’或具有藉由絕緣層來提供額外固定的橫向延 、鱼:為3 f {列，連接器可為一預先製造多_點聚合物 查接器。因此’將以說明性而非限制性之意義來看待說明 田及圖，且意欲將所有此等修改包括在本發明之範轉内。 残將可促使任何益處、優點或解決方法出現或變得更 解盈處、優點、問題之解決方法及任何(多個)要素 解釋為巾請專利職之任—項或所有項中之關鍵的、必需 125I46.doc -14- 200834767 的或本質的特徵或要素。將文中所使用的術語，，一，，界定為 一個或一個以上，即使其他元件在申請專利範圍或說明書 ^被明確陳述為一個或多個亦然。將文中所使用的術 -複數個”界定為兩個或兩個以上。將文中所使用的術語 #個界&為至第二個或更多。將文中所使用的術語 ”編接”界定為連接，雖然不必為直接連接且不必為機械連 接此外’在描述及申請專利範圍中的術語”前面”、”後 Φ 面 頂、底”、”上方"、”下方"、，，側面”及其類似詞語 (右有的話）係用於描述性目的且不必要用於描述永久的相 對位置。應瞭解，如此使用之術語在適當情況下係可互換 的，使彳于本文所描述之本發明的實施例（例如）係能夠在除 本文中说明或描述之方位外的其他方位中操作。 【圖式簡單說明】 圖1為根據一實施例之在處理中一步驟處之具有半導體 裝置之工件的橫截面； • 圖2為在處理中一隨後步驟處之圖1之工件的橫截面； 圖3為在處理中一隨後步驟處之圖2之工件的橫截面； 圖4為在處理中一隨後步驟處之圖3之工件的橫截面； • 圖5為在處理中一隨後步驟處之圖4之工件的橫截面； - 圖6為在處理中一隨後步驟處之圖5之工件的橫截面，· 圖7為在處理中一隨後步驟處之圖6之工件的橫截面； 圖8為在處理中一隨後步驟處之圖7之工件的橫截面； 圖9為在處理中一隨後步驟處之圖8之工件的橫截面； 圖1〇為在處理中一隨後步驟處之圖9之工件的橫截面； 125146.doc -15· 200834767 圖11為在處理中一隨後步驟處之圖10之工件的橫截面； 圖12為在處理中一隨後步驟處之圖11之工件的橫截面； 圖13為在處理中一隨後步驟處之圖12之工件的橫截面· 圖14為根據另一實施例之在處理中一步驟處之具有半導 體裝置之工件的橫截面； 圖15為在處理中一隨後步驟處之圖14之工件的橫截面； 圖16為在處理中一隨後步驟處之圖15之工件的橫截面； 圖17為在處理中一隨後步驟處之圖16之工件的橫截面； 圖18為在處理中一隨後步驟處之圖17之工件的橫截面； 圖19為在處理中一隨後步驟處之圖丨8之工件的橫截面； 圖20為在處理中一隨後步驟處之圖19之工件的橫截面； 圖21為在處理中一隨後步驟處之圖20之工件的橫截面； 圖22為在處理中一隨後步驟處之圖21之工件的橫截面； 圖23為在處理中一隨後步驟處之圖15之工件的橫截面。 【主要元件符號說明】 10 工件 12 半導體裝置 14 絕緣層 16 虛線 18 觸點 20 觸點 22 觸點 24 觸點 26 絕緣層 125146.doc 200834767 通道 通道 通道 通道 晶種層 晶種層 晶種層 晶種層 導電層 導電層 導電層 導電層 絕緣層 通道 通道 晶種層 晶種層 導電層 導電層 絕緣層 通道 通道 膠帶 通道 125146.doc 200834767
76 通道 78 晶種層 80 晶種層 82 預先製造連接器 84 插腳 86 插腳 88 保護蓋 90 導電層 92 導電層 94 絕緣層 96 焊球 98 焊球 100 工件 102 半導體裝置 104 絕緣層 106 觸點 108 觸點 110 觸點 112 觸點 114 分離線/虛線 116 連接器 118 插腳 120 插腳 122 保護蓋 125146.doc -18- 200834767 絕緣層 洞 通道 通道 通道 通道 晶種層 晶種層 晶種層 晶種層 導電層 導電層 導電層 導電層 絕緣層 導電層 導電層 導電層 導電層 絕緣層 導電層 導電層 導電層 絕緣層 125146.doc •19- 200834767
172 174 焊球焊球 125146.doc -20-

Claims (1)

  1. 200834767 十、申請專利範圍：
    一種封裝一具有一第一主表面及一第二主表面之第 置之方法，其包含： 在該第一裝置之一第二主表面上且在該第—裝置之侧 面四周形成-第-層且使該第一裝置之該第—主表面暴 露’其中該第-層係選自由—密封劑及—聚合物組成之
    在該第一裝置之該第一主表面上形成一第—介電層； 在該第一介電層中形成一通道； 在該通道内且在該第一介電層之一部分上形成一曰 IS,. 日日1 里 層， 將一連接器實體耦接至該晶種層；及 在該晶種層上電鍍一導電材料以在該第一通道中且在 該第一介電層之一部分上形成一第一互連。 2·如請求項1之方法，其進一步包含： 在形成該第一介電層前在該第一裝置上形成—第二介 電層； — 在該第二介電層中形成一第二互連，其中該第二互連 耦接至該第一互連；及 在該第二介電層中形成一第三互連，其中該第三互連 耦接至一外部連接器。 3·如請求項2之方法，其中該外部連接包含焊球。 4·如請求項3之#法，其中該連接器包含一預先製造連接 器。 125146.doc 200834767 5·如請求項2之方法，其中該外部連接器在該第一裝置之 該第一主表面上形成，且該連接器在該第一裝置之該第 一主表面上形成。 6·如請求項2之方法，其中該外部連接器係在該第一裝置 之鑲第一主表面上，且該連接器在該第一裝置之該第一 主表面上形成。
    如睛求項1之方法，其中將一連接器實體耦接至該晶種 層包含將該連接器置放在該第一裝置之該第一主表面 上其中5亥第一裝置之該第一主表面包含觸點。 如明求項1之方法，其中將一連接器實體耦接至該晶種 層包含將該連接器置放在該第一裝置之該第二主表面 上其中該第一裝置之該第一主表面包含觸點。 如睛求項1之方法，其中將一連接器實體耦接至該晶種 層包含： 將該連接器置放在該第一層上，其中·· # 該第一層包含一鄰近於一第二部分之第一部分； 邊第一裝置係在該第一層之該第一部分中形成； 將該連接器置放在該第一層之該第二部分上； δ亥連接器包含一侧面觸點；及 - 該側面觸點耦接至該晶種層。 10·如咕求項9之方法，其中該側面觸點係選自由一母連接 器及一公連接器組成之群。 . 11·種封裝一具有一第一主表面及一第二主表面之第一裝 置之方法，其包含： 125146.doc -2- 200834767 在該第一裝置之該第一主 在該介雷、上形成一介電層； 亥，1電層中形成-第-通道. 在該介電層中形成-第二通道；’ 在該第一通道令形成-第-晶種層； ㈣第二通道中形成一第二晶種層； 將一弟一外部連接哭之$小 . 上，盆中咳形成兮—夕—部分置放在該介電層 …， 晶種層及該置放該第-外部連接 益之至少一部分將 丨運接 • 置； 外邛連接器耦接至該第一裝 電鍍該第-晶種層以形成_第—互連； 電鍍該第二晶種層以形成-第二互連；及 將該第二互連為技P ^ 連耦接至一弟二外部連接器。 12·如請求項11之方法，並 、 ，、T孩弟一外部連接器及該第二外 部連接器係不同類型之連接器。 13·如請求項12之方法’其中㈣—外部連接器包含-預先 • 製造連接15且該第二外部連接器包含-焊球。 14.如請求項13之方法，其中該第-外部連接器及該第二外 料接器均在該第—裝置之該第—主表面上形成，其中 . 該第一主表面包含觸點。 15·如請求項/4之方法，其中該第-外部連接器在該第一裝 置之-第-主表面上形成，其中該第一主表面包含觸 點，且該第二外部連接器在該第-裝置之該第二主表面 上形成’其中該第二主表面係與該第一主表面相對。 16.如請求項11之方法，其中該第一晶種層係在置放該第一 I25146.doc 200834767 外部連接器之至少一部分之該步驟後形成。 7如明求項11之方法，其中該第一晶種層係在置放該第一 外部連接器之至少一部分之該步驟前形成。 18·種封裝一具有一第一主表面及一第二主表面之第一裝 置之方法，其包含： 乂 在該第一裝置之一第二主表面上且在該第一裝置之側 面四周形成一第一層且使該第一裝置之該第一主表面暴 露，其中該第一層係選自由一密封劑及一聚合物组成丄 群； 在該第-裝置之該第一主表面上形成一第一介電層； 將一預先製造連接器嵌入至少該第一介電層中，^中 該連接器包含一插腳；及 形成一自該第一裝置之該筮_ 衣置之这弟主表面至該連接器之該 插腳之互連。 19·如請求項18之方法，其中嵌⑼預先製造連接器及形成 该互連包含： 在該第一介電層中形成一通道； 在該通道内且在該第一介電爲 _之一部分上形成一晶種 層； 將該預先製造連接器實體耦接 ^ p 供至該晶種層；及 在該晶種層上電鍍一導電材科。 20.如請求項19之方法，豆進一步 ^ ^ ’、 匕含切割該密封劑以分離 該弟一裝置與該預先製造連接器。 125146.doc -4 -
TW096138316A 2006-11-17 2007-10-12 Method of packaging a semiconductor device and a prefabricated connector TW200834767A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/561,063 US7588951B2 (en) 2006-11-17 2006-11-17 Method of packaging a semiconductor device and a prefabricated connector

Publications (1)

Publication Number Publication Date
TW200834767A true TW200834767A (en) 2008-08-16

Family

ID=39417422

Family Applications (1)

Application Number Title Priority Date Filing Date
TW096138316A TW200834767A (en) 2006-11-17 2007-10-12 Method of packaging a semiconductor device and a prefabricated connector

Country Status (7)

Country Link
US (2) US7588951B2 (zh)
EP (1) EP2084743A2 (zh)
JP (1) JP2010510663A (zh)
KR (1) KR101484494B1 (zh)
CN (1) CN101529586B (zh)
TW (1) TW200834767A (zh)
WO (1) WO2008063742A2 (zh)

Families Citing this family (48)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8217511B2 (en) * 2007-07-31 2012-07-10 Freescale Semiconductor, Inc. Redistributed chip packaging with thermal contact to device backside
TWI360207B (en) 2007-10-22 2012-03-11 Advanced Semiconductor Eng Chip package structure and method of manufacturing
US8035216B2 (en) * 2008-02-22 2011-10-11 Intel Corporation Integrated circuit package and method of manufacturing same
US8410584B2 (en) 2008-08-08 2013-04-02 Advanced Semiconductor Engineering, Inc. Semiconductor device packages with electromagnetic interference shielding
FR2938976A1 (fr) * 2008-11-24 2010-05-28 St Microelectronics Grenoble Dispositif semi-conducteur a composants empiles
TWI456715B (zh) * 2009-06-19 2014-10-11 Advanced Semiconductor Eng 晶片封裝結構及其製造方法
TWI466259B (zh) * 2009-07-21 2014-12-21 Advanced Semiconductor Eng 半導體封裝件、其製造方法及重佈晶片封膠體的製造方法
TWI405306B (zh) 2009-07-23 2013-08-11 Advanced Semiconductor Eng 半導體封裝件、其製造方法及重佈晶片封膠體
TWI528514B (zh) * 2009-08-20 2016-04-01 精材科技股份有限公司 晶片封裝體及其製造方法
US20110084372A1 (en) 2009-10-14 2011-04-14 Advanced Semiconductor Engineering, Inc. Package carrier, semiconductor package, and process for fabricating same
US20110108999A1 (en) * 2009-11-06 2011-05-12 Nalla Ravi K Microelectronic package and method of manufacturing same
US8378466B2 (en) 2009-11-19 2013-02-19 Advanced Semiconductor Engineering, Inc. Wafer-level semiconductor device packages with electromagnetic interference shielding
US8327532B2 (en) * 2009-11-23 2012-12-11 Freescale Semiconductor, Inc. Method for releasing a microelectronic assembly from a carrier substrate
TWI497679B (zh) * 2009-11-27 2015-08-21 Advanced Semiconductor Eng 半導體封裝件及其製造方法
US8937381B1 (en) * 2009-12-03 2015-01-20 Amkor Technology, Inc. Thin stackable package and method
US8742561B2 (en) 2009-12-29 2014-06-03 Intel Corporation Recessed and embedded die coreless package
US8901724B2 (en) 2009-12-29 2014-12-02 Intel Corporation Semiconductor package with embedded die and its methods of fabrication
US8569894B2 (en) 2010-01-13 2013-10-29 Advanced Semiconductor Engineering, Inc. Semiconductor package with single sided substrate design and manufacturing methods thereof
US8372689B2 (en) 2010-01-21 2013-02-12 Advanced Semiconductor Engineering, Inc. Wafer-level semiconductor device packages with three-dimensional fan-out and manufacturing methods thereof
US8320134B2 (en) 2010-02-05 2012-11-27 Advanced Semiconductor Engineering, Inc. Embedded component substrate and manufacturing methods thereof
TWI411075B (zh) 2010-03-22 2013-10-01 Advanced Semiconductor Eng 半導體封裝件及其製造方法
US8535989B2 (en) 2010-04-02 2013-09-17 Intel Corporation Embedded semiconductive chips in reconstituted wafers, and systems containing same
US8624374B2 (en) 2010-04-02 2014-01-07 Advanced Semiconductor Engineering, Inc. Semiconductor device packages with fan-out and with connecting elements for stacking and manufacturing methods thereof
US8278746B2 (en) 2010-04-02 2012-10-02 Advanced Semiconductor Engineering, Inc. Semiconductor device packages including connecting elements
US8319318B2 (en) 2010-04-06 2012-11-27 Intel Corporation Forming metal filled die back-side film for electromagnetic interference shielding with coreless packages
US8618652B2 (en) 2010-04-16 2013-12-31 Intel Corporation Forming functionalized carrier structures with coreless packages
US8939347B2 (en) 2010-04-28 2015-01-27 Intel Corporation Magnetic intermetallic compound interconnect
US9847308B2 (en) 2010-04-28 2017-12-19 Intel Corporation Magnetic intermetallic compound interconnect
US8434668B2 (en) 2010-05-12 2013-05-07 Intel Corporation Magnetic attachment structure
US8313958B2 (en) 2010-05-12 2012-11-20 Intel Corporation Magnetic microelectronic device attachment
US8609532B2 (en) 2010-05-26 2013-12-17 Intel Corporation Magnetically sintered conductive via
US20120001339A1 (en) 2010-06-30 2012-01-05 Pramod Malatkar Bumpless build-up layer package design with an interposer
US8372666B2 (en) 2010-07-06 2013-02-12 Intel Corporation Misalignment correction for embedded microelectronic die applications
US8238113B2 (en) * 2010-07-23 2012-08-07 Imbera Electronics Oy Electronic module with vertical connector between conductor patterns
US8216918B2 (en) 2010-07-23 2012-07-10 Freescale Semiconductor, Inc. Method of forming a packaged semiconductor device
US8754516B2 (en) 2010-08-26 2014-06-17 Intel Corporation Bumpless build-up layer package with pre-stacked microelectronic devices
US8304913B2 (en) 2010-09-24 2012-11-06 Intel Corporation Methods of forming fully embedded bumpless build-up layer packages and structures formed thereby
US8941222B2 (en) 2010-11-11 2015-01-27 Advanced Semiconductor Engineering Inc. Wafer level semiconductor package and manufacturing methods thereof
US9406658B2 (en) 2010-12-17 2016-08-02 Advanced Semiconductor Engineering, Inc. Embedded component device and manufacturing methods thereof
US8937382B2 (en) 2011-06-27 2015-01-20 Intel Corporation Secondary device integration into coreless microelectronic device packages
US8848380B2 (en) 2011-06-30 2014-09-30 Intel Corporation Bumpless build-up layer package warpage reduction
US9224674B2 (en) * 2011-12-15 2015-12-29 Intel Corporation Packaged semiconductor die with bumpless die-package interface for bumpless build-up layer (BBUL) packages
US9257368B2 (en) 2012-05-14 2016-02-09 Intel Corporation Microelectric package utilizing multiple bumpless build-up structures and through-silicon vias
KR101947722B1 (ko) * 2012-06-07 2019-04-25 삼성전자주식회사 적층 반도체 패키지 및 이의 제조방법
CN104321864B (zh) 2012-06-08 2017-06-20 英特尔公司 具有非共面的、包封的微电子器件和无焊内建层的微电子封装
US9806048B2 (en) * 2016-03-16 2017-10-31 Qualcomm Incorporated Planar fan-out wafer level packaging
US10034693B2 (en) 2016-07-07 2018-07-31 Mark S. Stern Spinous laminar clamp assembly
US10515921B2 (en) * 2017-07-27 2019-12-24 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package and method of fabricating semiconductor package

Family Cites Families (58)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4088546A (en) 1977-03-01 1978-05-09 Westinghouse Electric Corp. Method of electroplating interconnections
US5829128A (en) 1993-11-16 1998-11-03 Formfactor, Inc. Method of mounting resilient contact structures to semiconductor devices
US4866501A (en) 1985-12-16 1989-09-12 American Telephone And Telegraph Company At&T Bell Laboratories Wafer scale integration
US5354695A (en) 1992-04-08 1994-10-11 Leedy Glenn J Membrane dielectric isolation IC fabrication
US5948533A (en) * 1990-02-09 1999-09-07 Ormet Corporation Vertically interconnected electronic assemblies and compositions useful therefor
US5250843A (en) 1991-03-27 1993-10-05 Integrated System Assemblies Corp. Multichip integrated circuit modules
US5353498A (en) 1993-02-08 1994-10-11 General Electric Company Method for fabricating an integrated circuit module
US6400573B1 (en) * 1993-02-09 2002-06-04 Texas Instruments Incorporated Multi-chip integrated circuit module
US5438877A (en) 1994-06-13 1995-08-08 Motorola, Inc. Pressure sensor package for reducing stress-induced measurement error
US6254815B1 (en) 1994-07-29 2001-07-03 Motorola, Inc. Molded packaging method for a sensing die having a pressure sensing diaphragm
US6148673A (en) 1994-10-07 2000-11-21 Motorola, Inc. Differential pressure sensor and method thereof
US5967844A (en) * 1995-04-04 1999-10-19 Berg Technology, Inc. Electrically enhanced modular connector for printed wiring board
US5746307A (en) 1997-04-07 1998-05-05 Motorola, Inc. Switch assembly for a portable radio
US5977826A (en) 1998-03-13 1999-11-02 Behan; Scott T. Cascaded error correction in a feed forward amplifier
US6153929A (en) 1998-08-21 2000-11-28 Micron Technology, Inc. Low profile multi-IC package connector
GB9818840D0 (en) 1998-08-29 1998-10-21 Koninkl Philips Electronics Nv Personal communications apparatus
KR100300527B1 (ko) 1998-09-03 2001-10-27 윤덕용 밀봉형무선압력측정소자및그제조방법
US6346742B1 (en) 1998-11-12 2002-02-12 Maxim Integrated Products, Inc. Chip-scale packaged pressure sensor
US6869870B2 (en) 1998-12-21 2005-03-22 Megic Corporation High performance system-on-chip discrete components using post passivation process
KR20010002843A (ko) * 1999-06-18 2001-01-15 김영환 몰드형 웨이퍼 레벨 패키지
JP2001024312A (ja) 1999-07-13 2001-01-26 Taiyo Yuden Co Ltd 電子装置の製造方法及び電子装置並びに樹脂充填方法
AU6531600A (en) * 1999-08-27 2001-03-26 Lex Kosowsky Current carrying structure using voltage switchable dielectric material
KR100462980B1 (ko) 1999-09-13 2004-12-23 비쉐이 메저먼츠 그룹, 인코포레이티드 반도체장치용 칩 스케일 표면 장착 패키지 및 그 제조공정
US6271060B1 (en) 1999-09-13 2001-08-07 Vishay Intertechnology, Inc. Process of fabricating a chip scale surface mount package for semiconductor device
US6316287B1 (en) 1999-09-13 2001-11-13 Vishay Intertechnology, Inc. Chip scale surface mount packages for semiconductor device and process of fabricating the same
US6254515B1 (en) * 1999-10-20 2001-07-03 Cybex International, Inc. Apparatus for stabilizing a treadmill
US6350623B1 (en) 1999-10-29 2002-02-26 California Institute Of Technology Method of forming intermediate structures in porous substrates in which electrical and optical microdevices are fabricated and intermediate structures formed by the same
US6307282B1 (en) 1999-12-06 2001-10-23 Motorola, Inc. Smart switch
NL1014082C2 (nl) 2000-01-17 2001-07-18 Franciscus Antonius Maria Van Systeem voor het verbinden van elementen.
US6401545B1 (en) 2000-01-25 2002-06-11 Motorola, Inc. Micro electro-mechanical system sensor with selective encapsulation and method therefor
US6392257B1 (en) 2000-02-10 2002-05-21 Motorola Inc. Semiconductor structure, semiconductor device, communicating device, integrated circuit, and process for fabricating the same
US6586836B1 (en) 2000-03-01 2003-07-01 Intel Corporation Process for forming microelectronic packages and intermediate structures formed therewith
US6407929B1 (en) 2000-06-29 2002-06-18 Intel Corporation Electronic package having embedded capacitors and method of fabrication therefor
JP2002026187A (ja) * 2000-07-07 2002-01-25 Sony Corp 半導体パッケージ及び半導体パッケージの製造方法
EP1321980A4 (en) * 2000-09-25 2007-04-04 Ibiden Co Ltd SEMICONDUCTOR ELEMENT, METHOD FOR MANUFACTURING SEMICONDUCTOR ELEMENT, MULTILAYER PRINTED CIRCUIT BOARD, AND METHOD FOR MANUFACTURING MULTILAYER PRINTED CIRCUIT BOARD
US6890829B2 (en) 2000-10-24 2005-05-10 Intel Corporation Fabrication of on-package and on-chip structure using build-up layer process
US6441753B1 (en) 2000-10-25 2002-08-27 Motorola, Inc. Multi-function key assembly for an electronic device
GB2371436B (en) 2001-01-22 2004-09-08 Nokia Mobile Phones Ltd Portable telephone
US7498196B2 (en) * 2001-03-30 2009-03-03 Megica Corporation Structure and manufacturing method of chip scale package
US6825552B2 (en) 2001-05-09 2004-11-30 Tessera, Inc. Connection components with anisotropic conductive material interconnection
GB0115793D0 (en) * 2001-06-28 2001-08-22 Univ Cranfield A novel mediator for electrochemical detection
JP2004039897A (ja) 2002-07-04 2004-02-05 Toshiba Corp 電子デバイスの接続方法
WO2004034759A1 (ja) * 2002-10-08 2004-04-22 Dai Nippon Printing Co., Ltd. 部品内蔵配線板、部品内蔵配線板の製造方法
US6921860B2 (en) 2003-03-18 2005-07-26 Micron Technology, Inc. Microelectronic component assemblies having exposed contacts
US6764748B1 (en) * 2003-03-18 2004-07-20 International Business Machines Corporation Z-interconnections with liquid crystal polymer dielectric films
US6838776B2 (en) * 2003-04-18 2005-01-04 Freescale Semiconductor, Inc. Circuit device with at least partial packaging and method for forming
US6921975B2 (en) * 2003-04-18 2005-07-26 Freescale Semiconductor, Inc. Circuit device with at least partial packaging, exposed active surface and a voltage reference plane
US7053799B2 (en) 2003-08-28 2006-05-30 Motorola, Inc. Keypad with illumination structure
TWI251920B (en) * 2003-10-17 2006-03-21 Phoenix Prec Technology Corp Circuit barrier structure of semiconductor package substrate and method for fabricating the same
US7335972B2 (en) * 2003-11-13 2008-02-26 Sandia Corporation Heterogeneously integrated microsystem-on-a-chip
US7015075B2 (en) * 2004-02-09 2006-03-21 Freescale Semiconuctor, Inc. Die encapsulation using a porous carrier
US7345359B2 (en) 2004-03-05 2008-03-18 Intel Corporation Integrated circuit package with chip-side signal connections
US20050242425A1 (en) * 2004-04-30 2005-11-03 Leal George R Semiconductor device with a protected active die region and method therefor
US20060146027A1 (en) 2004-12-31 2006-07-06 Tracy James L Keypad and button mechanism having enhanced tactility
JP2006332094A (ja) * 2005-05-23 2006-12-07 Seiko Epson Corp 電子基板の製造方法及び半導体装置の製造方法並びに電子機器の製造方法
US7503799B2 (en) * 2006-08-28 2009-03-17 Commscope Inc. Communications plug with reverse cordage and anti-snag configuration
US20080085572A1 (en) 2006-10-05 2008-04-10 Advanced Chip Engineering Technology Inc. Semiconductor packaging method by using large panel size
US20080119004A1 (en) 2006-11-17 2008-05-22 Burch Kenneth R Method of packaging a device having a keypad switch point

Also Published As

Publication number Publication date
US20090286390A1 (en) 2009-11-19
US20080119015A1 (en) 2008-05-22
US7588951B2 (en) 2009-09-15
JP2010510663A (ja) 2010-04-02
KR20090080527A (ko) 2009-07-24
EP2084743A2 (en) 2009-08-05
WO2008063742A3 (en) 2008-07-17
WO2008063742A2 (en) 2008-05-29
US7655502B2 (en) 2010-02-02
CN101529586B (zh) 2012-04-25
KR101484494B1 (ko) 2015-01-20
CN101529586A (zh) 2009-09-09

Similar Documents

Publication Publication Date Title
TW200834767A (en) Method of packaging a semiconductor device and a prefabricated connector
KR100419352B1 (ko) 반도체장치용 패키지 및 그의 제조방법
TW499746B (en) Chip scale surface mount package for semiconductor device and process of fabricating the same
KR101715761B1 (ko) 반도체 패키지 및 그 제조방법
TWI278048B (en) Semiconductor device and its manufacturing method
TWI374532B (en) Semiconductor packages and method for fabricating semiconductor packages with discrete components
US8344499B2 (en) Chip-exposed semiconductor device
US8338924B2 (en) Substrate for integrated circuit package with selective exposure of bonding compound and method of making thereof
JP5615936B2 (ja) パネルベースのリードフレームパッケージング方法及び装置
TW200820410A (en) Semiconductor packaging structure
US7163841B2 (en) Method of manufacturing circuit device
JPH088283A (ja) 基板利用パッケージ封入電子デバイスおよびその製造方法
TW201036119A (en) Semiconductor die package and method for making the same
TW200828523A (en) Multi-component package with both top and bottom side connection pads for three-dimensional packaging
TW201250963A (en) Semiconductor device and method for manufacturing semiconductor device
US8017442B2 (en) Method of fabricating a package structure
TW200816437A (en) An electronics package with an integrated circuit device having post wafer fabrication integrated passive components
US20080174005A1 (en) Electronic device and method for manufacturing electronic device
TW201138043A (en) Circuit board structure, packaging structure and method for making the same
CN106663672A (zh) 批量封装低引脚计数嵌入式半导体芯片的结构及方法
US20080290514A1 (en) Semiconductor device package and method of fabricating the same
TW200930173A (en) Package substrate having embedded semiconductor element and fabrication method thereof
JP2004207278A (ja) 回路装置およびその製造方法
JP2004128042A (ja) 半導体装置の製造方法及び半導体装置
EP4227992A2 (en) Semiconductor package with exposed electrical contacts