TW200822249A - Brace for wire loop - Google Patents

Brace for wire loop Download PDF

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Publication number
TW200822249A
TW200822249A TW95141512A TW95141512A TW200822249A TW 200822249 A TW200822249 A TW 200822249A TW 95141512 A TW95141512 A TW 95141512A TW 95141512 A TW95141512 A TW 95141512A TW 200822249 A TW200822249 A TW 200822249A
Authority
TW
Taiwan
Prior art keywords
die
lead
pad
line
bond
Prior art date
Application number
TW95141512A
Other languages
English (en)
Inventor
Zhe Li
Original Assignee
Freescale Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Freescale Semiconductor Inc filed Critical Freescale Semiconductor Inc
Publication of TW200822249A publication Critical patent/TW200822249A/zh

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    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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Description

200822249 九、發明說明： 【發明所屬之技術領域】 本發明一般係與接線焊接有關，且更明確言之，係與一 種用於長接線迴路之撐臂有關。 【先前技術】 接線知接一般包括採用一焊接線將一積體電路（ic)晶粒 上之4墊連接至-引線框架之一引線指形物。參考圖 ('_卜顯示一已封裝半導體裝置1〇。該裝置ίο包括一積體電 路（1C)晶粒12，其係採用一黏合劑16而附著於一引線框架 槳狀物14。採用焊接線2〇與22將1(：：晶粒以上之焊墊電性連 接至引線框架指形物18。焊接線2〇係一典型焊接線，因為 其自位於1C晶粒12之一周邊上之一焊塾延伸至該等引線指 形物之-，而焊接線22係一長接線，因為其自位於1〇晶 粒12之-中心區域中之一焊塾延伸至該等引線指形物1 8之 -。因此’可以板内(即，遽離IC晶粒之周邊)方式或沿著 iC晶粒之周邊定位一焊墊。 將板内焊墊連接至引線框架引線指形物經常需要具有大 中田長度之烊接線（像焊接線22)。對應地，通常在板内焊墊 與引線框架引線指形物之間形成大幅長度之接線迴路。為 了防止接線至晶粒短路，必須在1€；晶粒之表面上方维持一 為焊接線直徑之至少兩⑺倍之高度餘隙。不過，遍及焊接 線之板内長度（即，焊接線在iC晶粒之表面上方之延伸長 度）產生一具有所需高度餘隙之接線迴路，通常會引發性 能問題’例如已降低穩定性與不—致性。在焊接線之板内 116222.doc 200822249 長度大於焊接線總 op 嚴重。 長度之大約60%的情 況下，此問題尤其 【發明内容】 雲於上述問韻， ^ 一有一種形成一穩定與一致的接線 ,，该接線迴路具有遍及其板 度餘隙以防止接線至晶粒短^ 【實施方式】
&以下結合附圖提出的詳細說明係希望作為本發明之目前 ㈣具體實施例之說明，而不希望其代表實施本發明的唯 以應瞭解’藉由希望包含在本發明之精神及範疇内 的不同具體實施例，可實現相同或等效功能。 本發明提供一種將一引線框架引線指形物連接至一積體 電路(1C)晶粒上之一焊墊之方法。該方法包括自該引線指 七物至-巾間點焊接_第—焊接線之—步驟。自該引線指 形物至該焊墊焊接一第二焊接線，使得該第一焊接線支撐 該第二焊接線。 本發明亦提供一種半導體封裝，其包括具有一晶粒支撐 區域及位於該晶粒支撐區域周圍之複數個引線指形物之一 引線框架。具有複數個焊墊之一積體電路（IC)晶粒係附著 於該晶粒支撐區域。採用個別焊接線將個別引線指形物連 接至個別焊墊：一第一焊接線將一第一引線指形物連接至 一中間點；及，一第二焊接線將該第一引線指形物連接至 一第一焊墊’使得該第一焊接線支撐該第二焊接線。 本發明進一步提供一種製造一半導體封裝之方法，其包 116222.doc - 6 - 200822249 括使具有複數個焊墊之一積體電路（IC)晶粒附著於一引線 框架之一晶粒支撐區域之步驟，該引線框架具有位於該晶 粒支撐區域周圍之複數個引線指形物。採用個別焊接線將 個別引線指形物連接至個別焊墊：一第一焊接線將一第一 引線指形物連接至一中間點；及，一第二焊接線將該第一 引線指形物連接至一第一焊墊，使得該第一焊接線支撐該 第二焊接線。採用一模製化合物囊封該引線框架、該ic晶 / 粒及該等焊接線。 現在參考圖2，其顯示附著於一引線框架32之一積體電 路（1C)晶粒30之放大俯視平面圖。該IC晶粒3〇可為一處理 器（例如，數位信號處理器（DSP))、一特殊功能電路（例 如，記憶體位址產生器）或一執行任何其他類型功能之電 路。1C晶粒30不受限於一特定技術（例如，CM〇s)或自任 何特定晶圓技術衍生而成。此外，熟習此項技術者應明 白，本發明可提供各種晶粒尺寸。一典型範例係尺寸為大 約15 mmxl5 mm之一記憶體晶粒。引線框架32包括一晶粒 支撐區域34及位於該晶粒支撐區域34周圍之複數個引線指 形物36。1C晶粒30係附著於引線框架32之晶粒支撐區^ 34。可採用熟習此項技術者所熟知的各種方式（例如，採 用放置於1C晶粒30之背面上之膠水或—黏合劑材料，或採 用一膠帶）使1C晶粒30附著於晶粒支撐區域34。 1C晶粒30包括複數個焊塾38,其中的每一個係藉由複數 個焊接線4G中的個別焊接線而連接至該等引線指形物36中 的個別引線指形物。雖然典型情況係將_引線指形物連接 H6222.doc 200822249 至一焊墊（如可看到之情況），但有時將一引線指形物連接 至多個焊墊。沿著1C晶粒30之一周邊定位該等焊墊38中的 若干焊墊。不過，如圖2所示，焊墊38中的某些係位於1(： 晶粒30之一中心區域中。因此，需要各種長度的焊接線 40 ’因為自引線指形物3 6至焊墊3 8之距離不一致。的確， 焊接線40中的某些焊接線必須非常長，以自一引線指形物 36延伸至1C晶粒30之一中心區域中之一焊墊38。 焊接線40可由金（Au)、銅（Cu)、鋁（A1)或此項技術中所 熟知且可以市售方式獲得之其他導電材料製成。圖2中焊 墊38在1C晶粒30上之佈局及焊接線4〇之配置僅為範例性； 熟習此項技術者應明白，本發明不受限於焊墊38之佈局或 焊接線40之配置。 再次參考圖2，一長接線42自一引線指形物44延伸以將 引線指形物44連接至一位於中心之焊墊46。為了防止長接 線42下垂且可能與IC晶粒3〇之一表面接觸，一較短接線48 自引線指形物44延伸至一中間點50。較長接線42係擱置在 較短接線48上或與其接觸，因此，較短接線48用作較長接 線42之一支撐物且防止較長接線42下彎或下垂且與ic晶粒 30接觸。 現在參考圖3，其顯示圖2之1(：晶粒3〇、引線框架32及焊 接線40之放大斷面圖。藉由一模製化合物52來囊封ic晶粒 3〇、焊接線40以及引線框架32之至少一頂部部分，以形成 一半導體封裝54。可使用一模製操作（例如，一喷射模製 程序）來執行該囊封。模製化合物52可包含廣為人知的市 116222.doc 200822249 售极il材# m塑膠或環氧樹脂。半導體封裝5何為任 何類型的接線焊接式封I，例如BGA、qfn、qfp、 PLCC、CUEBGA、TBGA及 TS〇p。 如圖3所示，*焊接線42之長度比短焊接線48之長度 長較短、更穩定的焊接線48用作長焊接線42之一撐臂， 為長焊接線42提供支撐且防止長谭接線42接觸ic晶粒取 -表面56。短焊接線48之板内長度认，而長焊接線仏之 f
板内長度為L2。 藉由短焊接線48所提供之支撐’長焊接線42具有一移定 與一致之接線迴路，其具有遍及其板内長度的一恰當高 度餘隙C以防止接線至晶粒短路。在此特定具體實施例 中，短焊接線48之板内長度Li(即，短焊接線料㈣晶粒 3〇之表面56上方之延伸長度)係小於短焊接線料之總長度 LT】之大約55%’而長焊接線42之板内長度L2(即，長焊接 線42在IC晶粒3〇之表面56上方之延伸長度）係大於長焊接 線42之總長度Lt2之大約65%。 在-具體實施例中，每_長與短焊接線仏與料之直种皆 為大約1.3密耳，長度Lt]與Lt2分別為大約63·7盘大⑽$ 密耳’且迴路高度分別為大約6·5至7_5密耳與大約 8.5至9.5密耳。儘管本文中說明長與短焊接線ο與判之特 定及相對尺寸，但熟習此項技術者應明白’本限 於所述尺寸。 長與短焊接線42與48之第— 中心之焊墊46以及中間點5 〇， 端58與60係分別焊接至位於 而長與短焊接線42與48之第 116222.doc 200822249 二端59與61係焊接至彳丨線指形物44。如可看到之情況，此 特疋具體貫施例中的焊接線4〇係藉由球焊接而焊接至W晶 粒30之焊墊38以及引線指形物^。不過，熟習此項技術者 應月白’本發明不党限於任何單一接線焊接技術。在所述 具體實施例中，中間點5〇係—焊塾。不過，應明白，本發 明不受限於將短焊接線48之第—㈣焊接至—焊塾。此 在此料具體實施例中，長與短焊接線42與48之個別 Γ 帛二端59與61係焊接至引線指形物44上的鄰近點；在—替 代具體實施例中，長與短焊接線42與48之個別第二端㈣ 61係知接至引線指形物44上的相同點。亦可將長與短谭接 線4 2與4 8焊接至引線指形物4 4中的不同引線指形物。 自以上論述可明白，本發明揭示一種藉由提供一撐臂 (其採用一較短且I質上更穩定之接線迴路之形式以支撐 較長接線迴路）來形成一穩定與一致的接線迴路之方法。牙 較短接線迴路亦防止較長接線迴路與以粒之表面接觸。 雖然已解說並說明本發明之較佳具體實施例，但是應明 白本發明不僅受限於缺笠且辨 瓦此寺具體貫施例。熟習此項技術者應 即瞭解各種修改、變更、變化、替代及等效物，而不㈣ 離申請專利範圍所說明的本發明之精神及範疇。 【圖式簡單說明】 當結合附圖閱讀時，將更佳瞭解以上本發明之若干較佳 具體實施例的詳細說明。本發明已藉由範例予以闡明二 本發明並未限定在附圖内，其中相同的參考數字代表相: 的元件。應瞭解的係，該等圖式並未依照比例而繪製，且 116222.doc 200822249 已加以簡化以方便瞭解本發明。 圖1係一習知積體電路（IC)裝置之一放大斷面圖； 圖2係依據本發明一具體實施例之一附著於引線框架之 積體電路（1C)晶粒之一放大俯視平面圖；及 圖3係藉由一模製化合物加以囊封的圖2之1(：晶粒、引線 框架及焊接線之一放大斷面圖。 【主要元件符號說明】 10 積體電路晶粒/已封裝半導體裝置 12 引線框架/積體電路晶粒 14 引線框架槳狀物 16 黏合劑 16a、18、36、44 引線指形物 1 8a、38、46 焊墊 20、4〇 焊接線 20a 第一焊接線 20b 第二焊接線 22 中間點/焊接線 30 積體電路晶粒 32 引線框架 34 晶粒支撐區域 42 長接線 48 短接線 50 中間點 52 模製化合物 116222.doc 200822249 54 半導體封裝 56 積體電路晶粒表面 58 ^ 60 第一端 59 ^ 61 第二端 C 高度餘隙 Hi、H2 迴路高度 Li > L2 板内長度 LtI ' Lt2 總長度 116222.doc -12-

Claims (1)

  1. 200822249 十、申請專利範圍： 1 · 一種將一引線框架引線指形物連接至一積體電路（IC)晶 粒上之一焊墊之方法，其包含： 自該引線指形物至一中間點焊接一第一焊接線；及 自该引線指形物至該焊墊焊接一第二焊接線，其中該 第一焊接線支撐該第二焊接線。 2.如請求項1之將一引線框架引線指形物連接至一 1C晶粒 f 上之一焊墊之方法，其中該第一焊接線防止該第二焊接 線接觸該1C晶粒之一表面。 3·如請求項1之將一引線框架引線指形物連接至一 1C晶粒 上之一焊墊之方法，其中該中間點係一第二焊墊。 4·如請求項3之將一引線框架引線指形物連接至一 IC晶粒 上之一焊墊之方法，其中沿著該IC晶粒之一周邊定位該 第二焊塾。 5·如請求項1之將一引線框架引線指形物連接至一 IC晶粒 、 上之一焊墊之方法，其中該第二焊接線之一板内長度大 於該第二焊接線之一總長度之大約65%。 6·如請求項5之將一引線框架引線指形物連接至一 IC晶粒 上之一烊塾之方法，其中該第一焊接線之一板内長度小 於該第一焊接線之一總長度之大約55%。 7·如請求項1之將一引線框架引線指形物連接至一 IC晶粒 上之一焊墊之方法，其中該第二焊接線之迴路高度為大 約8.5至9·5密耳。 8·如清求項7之將一引線框架引線指形物連接至一 IC晶粒 116222.doc 200822249 上之一焊墊之方法， 約6 · 5至7 · 5密耳。 其中該第一焊接線之迴路高度為大 9·如凊求項1之將一引線框架引線指形物連接至一 ic晶粒 上之—焊墊之方法，其中該第二焊接線之長度大於大約 80密耳。 上之一焊墊之方法， f 60密耳。 1〇·如凊求項9之將一引線框架引線指形物連接至_IC晶粒 其中該第一焊接線之長度小於大約 Π· 一種製造一半導體封裝之方法，其包含： 使具有複數個焊墊之一積體電路（lC)晶粒附著於一弓| 線框架之-晶粒支撐區域，該引線框架具有位於該晶粒 支撐區域周圍之複數個引線指形物； 才木用個別焊接線將個別引線指形物連接至個別焊墊， 其中一第一焊接線將一第一引線指形物連接至一中間點 且一第二焊接線將該第一引線指形物連接至一第一焊 墊，而且，其中該第一焊接線支撐該第二焊接線，·及 採用-模製化合物囊封該lC晶粒、該等焊接線以及該
    13· —種半導體封裝，其包含·· 引線框架’其具有一晶粒支撐區域及位於該晶粒支 撐區域周圍之複數個引線指形物；
    一積體電路（1C)晶粒 116222.doc 200822249 晶粒係附著於該引線框架晶粒支撐區域；及 個別焊接線，其將個別引線指形物連接至個別焊墊， 其中一第一焊接線將一第一引線指形物連接至一中間點 且一第二焊接線將該第一引線指形物連接至一第一焊 塾，而且，其中該第一焊接線支撐該第二焊接線。 14.如請求項13之半導體封裝，其中該第一焊接線防止該第 二焊接線接觸該1C晶粒之一表面。 15·如請求項14之半導體封裝，其中該第二焊接線之一板内 長度大於該第二焊接線之一總長度之大約65%。 16.如清求項13之半導體封裝，纟中該帛一焊接線之—板内 長度小於該第一悍接線之一總長度之大約55%。 1 7·如’求項13之半導體封裝，其中該第二焊接線之迴路高 度為大約8.5至9.5密耳。 网 士明求項17之半導體封裝，其中該第—焊接線之趣路言 度為大約6.5至7.5密耳。 间 116222.doc
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US7741720B2 (en) * 2007-09-25 2010-06-22 Silverbrook Research Pty Ltd Electronic device with wire bonds adhered between integrated circuits dies and printed circuit boards
US7659141B2 (en) * 2007-09-25 2010-02-09 Silverbrook Research Pty Ltd Wire bond encapsulant application control
US8025204B2 (en) * 2007-09-25 2011-09-27 Silverbrook Research Pty Ltd Method of wire bond encapsulation profiling
US8063318B2 (en) * 2007-09-25 2011-11-22 Silverbrook Research Pty Ltd Electronic component with wire bonds in low modulus fill encapsulant
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US8680660B1 (en) 2013-03-12 2014-03-25 Freescale Semiconductor, Inc. Brace for bond wire
US11011483B2 (en) * 2018-02-21 2021-05-18 Texas Instruments Incorporated Nickel alloy for semiconductor packaging
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