TW200741480A - Processor architecture - Google Patents

Processor architecture

Info

Publication number
TW200741480A
TW200741480A TW095147276A TW95147276A TW200741480A TW 200741480 A TW200741480 A TW 200741480A TW 095147276 A TW095147276 A TW 095147276A TW 95147276 A TW95147276 A TW 95147276A TW 200741480 A TW200741480 A TW 200741480A
Authority
TW
Taiwan
Prior art keywords
data
communication buses
data communication
memory module
hardware acceleration
Prior art date
Application number
TW095147276A
Other languages
English (en)
Other versions
TWI514165B (zh
Inventor
Sehat Sutardja
Original Assignee
Marvell World Trade Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Marvell World Trade Ltd filed Critical Marvell World Trade Ltd
Publication of TW200741480A publication Critical patent/TW200741480A/zh
Application granted granted Critical
Publication of TWI514165B publication Critical patent/TWI514165B/zh

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Image Processing (AREA)
  • Advance Control (AREA)
TW095147276A 2006-01-18 2006-12-15 資料處理系統 TWI514165B (zh)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US75986806P 2006-01-18 2006-01-18
US79856906P 2006-05-08 2006-05-08
US82087106P 2006-07-31 2006-07-31
US82232006P 2006-08-14 2006-08-14
US11/504,962 US7600081B2 (en) 2006-01-18 2006-08-16 Processor architecture having multi-ported memory

Publications (2)

Publication Number Publication Date
TW200741480A true TW200741480A (en) 2007-11-01
TWI514165B TWI514165B (zh) 2015-12-21

Family

ID=37989043

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095147276A TWI514165B (zh) 2006-01-18 2006-12-15 資料處理系統

Country Status (7)

Country Link
US (2) US7600081B2 (zh)
EP (1) EP1811398B1 (zh)
JP (1) JP5302507B2 (zh)
CN (1) CN101004674B (zh)
DE (1) DE602006021129D1 (zh)
SG (1) SG134211A1 (zh)
TW (1) TWI514165B (zh)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
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US8036061B2 (en) * 2009-02-13 2011-10-11 Apple Inc. Integrated circuit with multiported memory supercell and data path switching circuitry
JP4970579B2 (ja) 2010-08-26 2012-07-11 株式会社東芝 テレビジョン装置
US9336008B2 (en) 2011-12-28 2016-05-10 Intel Corporation Shared function multi-ported ROM apparatus and method
US9167296B2 (en) 2012-02-28 2015-10-20 Qualcomm Incorporated Customized playback at sink device in wireless display system
JP5712390B2 (ja) * 2013-04-01 2015-05-07 株式会社アクセル 通信システム
KR102396435B1 (ko) 2015-08-11 2022-05-11 삼성전자주식회사 불휘발성 메모리 장치, 버퍼 메모리 및 컨트롤러를 포함하는 스토리지 장치를 포함하는 컴퓨팅 장치의 동작 방법
US11397694B2 (en) * 2019-09-17 2022-07-26 Micron Technology, Inc. Memory chip connecting a system on a chip and an accelerator chip
US11409681B2 (en) * 2020-09-04 2022-08-09 Paypal, Inc. Computer system communication via sideband processor

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Publication number Priority date Publication date Assignee Title
JPS6347856A (ja) * 1986-08-15 1988-02-29 Toshiba Corp メモリシステム
CN1008018B (zh) * 1986-09-27 1990-05-16 徐肇昌 一种具有合作能力的同构型多计算机系统及其合作方法
JPH01177672A (ja) * 1988-01-08 1989-07-13 Yuuseishiyou Tsushin Sogo Kenkyusho ディジタル信号処理装置
JPH01280860A (ja) * 1988-05-06 1989-11-13 Hitachi Ltd マルチポートキヤツシユメモリを有するマルチプロセツサシステム
JPH0371364A (ja) * 1989-08-11 1991-03-27 Toyo Commun Equip Co Ltd プロセッサ
JP2965043B2 (ja) * 1990-04-10 1999-10-18 三菱電機株式会社 デュアルポートメモリ
JPH04257048A (ja) * 1991-02-12 1992-09-11 Mitsubishi Electric Corp デュアルポートメモリ
US5361370A (en) 1991-10-24 1994-11-01 Intel Corporation Single-instruction multiple-data processor having dual-ported local memory architecture for simultaneous data transmission on local memory ports and global port
JPH08129508A (ja) * 1994-10-31 1996-05-21 Toshiba Corp コンピュータシステム及びその共有メモリ制御方法
US5639094A (en) * 1995-03-29 1997-06-17 Manchester; Vance Word game
US6029242A (en) * 1995-08-16 2000-02-22 Sharp Electronics Corporation Data processing system using a shared register bank and a plurality of processors
US6067595A (en) * 1997-09-23 2000-05-23 Icore Technologies, Inc. Method and apparatus for enabling high-performance intelligent I/O subsystems using multi-port memories
US6480927B1 (en) * 1997-12-31 2002-11-12 Unisys Corporation High-performance modular memory system with crossbar connections
US6292862B1 (en) * 1998-07-28 2001-09-18 Siemens Aktiengesellschaft Bridge module
US6938253B2 (en) * 2001-05-02 2005-08-30 Portalplayer, Inc. Multiprocessor communication system and method
US6816889B1 (en) * 2001-07-03 2004-11-09 Advanced Micro Devices, Inc. Assignment of dual port memory banks for a CPU and a host channel adapter in an InfiniBand computing node
JP2004522235A (ja) * 2001-07-18 2004-07-22 コーニンクレッカ　フィリップス　エレクトロニクス　エヌ　ヴィ 多重プロセッサデバイスにおける不揮発性メモリ装置と方法
JP2003114797A (ja) * 2001-10-04 2003-04-18 Matsushita Electric Ind Co Ltd データ処理装置
GB0204144D0 (en) * 2002-02-22 2002-04-10 Koninkl Philips Electronics Nv Transferring data between differently clocked busses
US7571287B2 (en) * 2003-03-13 2009-08-04 Marvell World Trade Ltd. Multiport memory architecture, devices and systems including the same, and methods of using the same
US7236525B2 (en) 2003-05-22 2007-06-26 Lsi Corporation Reconfigurable computing based multi-standard video codec
US20050094729A1 (en) 2003-08-08 2005-05-05 Visionflow, Inc. Software and hardware partitioning for multi-standard video compression and decompression
JP4498848B2 (ja) * 2004-07-28 2010-07-07 三菱電機株式会社 画像処理装置

Also Published As

Publication number Publication date
DE602006021129D1 (de) 2011-05-19
EP1811398B1 (en) 2011-04-06
US20070168622A1 (en) 2007-07-19
EP1811398A1 (en) 2007-07-25
US20100023705A1 (en) 2010-01-28
SG134211A1 (en) 2007-08-29
US7600081B2 (en) 2009-10-06
CN101004674A (zh) 2007-07-25
JP5302507B2 (ja) 2013-10-02
JP2007220085A (ja) 2007-08-30
US7761668B2 (en) 2010-07-20
CN101004674B (zh) 2012-05-30
TWI514165B (zh) 2015-12-21

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Legal Events

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MM4A Annulment or lapse of patent due to non-payment of fees