TW200733272A - Methods of packaging a semiconductor die and die package formed by the methods - Google Patents
Methods of packaging a semiconductor die and die package formed by the methodsInfo
- Publication number
- TW200733272A TW200733272A TW095139928A TW95139928A TW200733272A TW 200733272 A TW200733272 A TW 200733272A TW 095139928 A TW095139928 A TW 095139928A TW 95139928 A TW95139928 A TW 95139928A TW 200733272 A TW200733272 A TW 200733272A
- Authority
- TW
- Taiwan
- Prior art keywords
- methods
- die
- semiconductor die
- packaging
- package formed
- Prior art date
Links
Classifications
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
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- H01L2224/8485—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
- H01L2224/84855—Hardening the adhesive by curing, i.e. thermosetting
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- H01L24/02—Bonding areas ; Manufacturing methods related thereto
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- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
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- H01L2924/013—Alloys
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- H01L2924/01327—Intermediate phases, i.e. intermetallics compounds
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- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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US73268305P | 2005-11-01 | 2005-11-01 |
Publications (1)
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TW200733272A true TW200733272A (en) | 2007-09-01 |
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ID=37808225
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW095139928A TW200733272A (en) | 2005-11-01 | 2006-10-27 | Methods of packaging a semiconductor die and die package formed by the methods |
Country Status (6)
Country | Link |
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US (1) | US8183682B2 (zh) |
EP (1) | EP1946364A1 (zh) |
JP (1) | JP2009514242A (zh) |
CN (1) | CN101356633B (zh) |
TW (1) | TW200733272A (zh) |
WO (1) | WO2007052199A1 (zh) |
Cited By (1)
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TWI509747B (zh) * | 2010-01-13 | 2015-11-21 | Fairchild Semiconductor | 包含多數晶粒及引線定向的晶粒封裝體 |
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KR20040098069A (ko) * | 2002-04-11 | 2004-11-18 | 코닌클리즈케 필립스 일렉트로닉스 엔.브이. | 전자 장치 및 전자 장치 제조 방법 |
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CN101073151B (zh) * | 2004-12-20 | 2010-05-12 | 半导体元件工业有限责任公司 | 具有增强散热性的半导体封装结构 |
US7588999B2 (en) * | 2005-10-28 | 2009-09-15 | Semiconductor Components Industries, Llc | Method of forming a leaded molded array package |
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- 2006-10-27 EP EP06821208A patent/EP1946364A1/en not_active Withdrawn
- 2006-10-27 CN CN2006800406288A patent/CN101356633B/zh not_active Expired - Fee Related
- 2006-10-27 WO PCT/IB2006/053964 patent/WO2007052199A1/en active Application Filing
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- 2006-10-27 JP JP2008538471A patent/JP2009514242A/ja not_active Withdrawn
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI509747B (zh) * | 2010-01-13 | 2015-11-21 | Fairchild Semiconductor | 包含多數晶粒及引線定向的晶粒封裝體 |
Also Published As
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JP2009514242A (ja) | 2009-04-02 |
CN101356633B (zh) | 2011-03-23 |
EP1946364A1 (en) | 2008-07-23 |
US8183682B2 (en) | 2012-05-22 |
WO2007052199A1 (en) | 2007-05-10 |
CN101356633A (zh) | 2009-01-28 |
US20080277772A1 (en) | 2008-11-13 |
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