TW200729368A - Method of manufacturing electronic circuit device - Google Patents

Method of manufacturing electronic circuit device

Info

Publication number
TW200729368A
TW200729368A TW095136536A TW95136536A TW200729368A TW 200729368 A TW200729368 A TW 200729368A TW 095136536 A TW095136536 A TW 095136536A TW 95136536 A TW95136536 A TW 95136536A TW 200729368 A TW200729368 A TW 200729368A
Authority
TW
Taiwan
Prior art keywords
interconnect
electronic circuit
electrode pad
circuit device
manufacturing electronic
Prior art date
Application number
TW095136536A
Other languages
English (en)
Other versions
TWI329346B (en
Inventor
Yoichiro Kurita
Koji Soejima
Masaya Kawano
Original Assignee
Nec Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nec Electronics Corp filed Critical Nec Electronics Corp
Publication of TW200729368A publication Critical patent/TW200729368A/zh
Application granted granted Critical
Publication of TWI329346B publication Critical patent/TWI329346B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
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TW095136536A 2005-10-07 2006-10-02 Method of manufacturing electronic circuit device TWI329346B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005294713A JP2007103840A (ja) 2005-10-07 2005-10-07 電子回路装置の製造方法

Publications (2)

Publication Number Publication Date
TW200729368A true TW200729368A (en) 2007-08-01
TWI329346B TWI329346B (en) 2010-08-21

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
TW095136536A TWI329346B (en) 2005-10-07 2006-10-02 Method of manufacturing electronic circuit device

Country Status (5)

Country Link
US (1) US7538022B2 (zh)
JP (1) JP2007103840A (zh)
KR (1) KR100770417B1 (zh)
CN (1) CN100527374C (zh)
TW (1) TWI329346B (zh)

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KR100979818B1 (ko) * 2007-12-13 2010-09-06 삼성전기주식회사 인쇄회로기판 제조방법
KR101022873B1 (ko) * 2009-09-14 2011-03-16 삼성전기주식회사 인쇄회로기판의 제조방법
JP2011222675A (ja) * 2010-04-07 2011-11-04 Mitsubishi Electric Corp 半導体装置及びその製造方法
TW201248745A (en) * 2011-05-20 2012-12-01 Subtron Technology Co Ltd Package structure and manufacturing method thereof
WO2013048473A1 (en) * 2011-09-30 2013-04-04 Intel Corporation Fluxing-encapsulant material for microelectronic packages assembled via thermal compression bonding process
JP7421877B2 (ja) 2019-06-27 2024-01-25 ローム株式会社 半導体装置
CN113659053B (zh) * 2021-09-07 2024-02-27 中山市木林森电子有限公司 一种csp灯珠封装结构及其制作工艺

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JPS61125066A (ja) * 1984-11-22 1986-06-12 Hitachi Ltd 半導体装置
JPS62142849A (ja) * 1985-12-17 1987-06-26 Japan Electronic Control Syst Co Ltd 車載電子制御装置の自己診断装置
JPH04196392A (ja) * 1990-11-28 1992-07-16 Hitachi Ltd 薄膜配線回路用はんだ付け電極
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JPH05144816A (ja) 1991-11-15 1993-06-11 Casio Comput Co Ltd フエイスダウンボンデイング方法
JPH0828562B2 (ja) * 1993-07-14 1996-03-21 日本電気株式会社 薄膜回路基板
US6222212B1 (en) * 1994-01-27 2001-04-24 Integrated Device Technology, Inc. Semiconductor device having programmable interconnect layers
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JP2007103840A (ja) 2007-04-19
US20070020804A1 (en) 2007-01-25
US7538022B2 (en) 2009-05-26
TWI329346B (en) 2010-08-21
CN100527374C (zh) 2009-08-12
KR100770417B1 (ko) 2007-10-26
CN1945806A (zh) 2007-04-11
KR20070039400A (ko) 2007-04-11

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