TW200723293A - Ram control device and memory device using the same - Google Patents
Ram control device and memory device using the sameInfo
- Publication number
- TW200723293A TW200723293A TW095128910A TW95128910A TW200723293A TW 200723293 A TW200723293 A TW 200723293A TW 095128910 A TW095128910 A TW 095128910A TW 95128910 A TW95128910 A TW 95128910A TW 200723293 A TW200723293 A TW 200723293A
- Authority
- TW
- Taiwan
- Prior art keywords
- access
- ram3
- control device
- same
- ram control
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Static Random-Access Memory (AREA)
- Bus Control (AREA)
- Multi Processors (AREA)
- Dram (AREA)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005227756 | 2005-08-05 | ||
JP2006144790 | 2006-05-25 | ||
JP2006147550 | 2006-05-29 |
Publications (1)
Publication Number | Publication Date |
---|---|
TW200723293A true TW200723293A (en) | 2007-06-16 |
Family
ID=37727232
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW095128910A TW200723293A (en) | 2005-08-05 | 2006-08-07 | Ram control device and memory device using the same |
Country Status (5)
Country | Link |
---|---|
US (1) | US7843762B2 (zh) |
JP (1) | JP5000514B2 (zh) |
CN (1) | CN101160566B (zh) |
TW (1) | TW200723293A (zh) |
WO (1) | WO2007018043A1 (zh) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8966416B2 (en) | 2013-03-07 | 2015-02-24 | Cadence Design Systems, Inc. | Finite-state machine encoding during design synthesis |
KR20190134037A (ko) * | 2018-05-24 | 2019-12-04 | 에스케이하이닉스 주식회사 | 도메인 크로싱 기능을 갖는 반도체 장치 |
US20230129868A1 (en) * | 2021-10-21 | 2023-04-27 | Stmicroelectronics S.R.L. | Systems and methods for asynchronous finite machines |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4240138A (en) * | 1978-10-03 | 1980-12-16 | Texas Instruments Incorporated | System for direct access to a memory associated with a microprocessor |
JPS573155A (en) * | 1980-06-05 | 1982-01-08 | Ricoh Co Ltd | Input and output control circuit for memory device |
JPS615363A (ja) * | 1984-06-19 | 1986-01-11 | Matsushita Electric Ind Co Ltd | 共有メモリの制御装置 |
JP2587229B2 (ja) * | 1987-03-11 | 1997-03-05 | 日本テキサス・インスツルメンツ株式会社 | アービタ回路 |
JPH06161870A (ja) | 1992-11-26 | 1994-06-10 | Nec Corp | デュアルポートram回路 |
JP4102455B2 (ja) * | 1996-09-26 | 2008-06-18 | セイコーエプソン株式会社 | 表示駆動制御回路及び画像表示装置並びにそれを備えた電子機器 |
US6172935B1 (en) * | 1997-04-25 | 2001-01-09 | Micron Technology, Inc. | Synchronous dynamic random access memory device |
JP3602004B2 (ja) | 1999-05-27 | 2004-12-15 | 日本電気エンジニアリング株式会社 | 装置内クロック非同期におけるシステム制御装置 |
JP3807593B2 (ja) | 2000-07-24 | 2006-08-09 | 株式会社ルネサステクノロジ | クロック生成回路および制御方法並びに半導体記憶装置 |
US6895522B2 (en) * | 2001-03-15 | 2005-05-17 | Micron Technology, Inc. | Method and apparatus for compensating duty cycle distortion in a data output signal from a memory device by delaying and distorting a reference clock |
TW594743B (en) * | 2001-11-07 | 2004-06-21 | Fujitsu Ltd | Memory device and internal control method therefor |
US7184359B1 (en) * | 2003-12-23 | 2007-02-27 | Cypress Semiconductor Corp. | System and method for staging concurrent accesses to a memory address location via a single port using a high speed sampling clock |
US7542365B2 (en) * | 2007-09-27 | 2009-06-02 | Freescale Semiconductor, Inc. | Apparatus and method for accessing a synchronous serial memory having unknown address bit field size |
-
2006
- 2006-07-27 JP JP2007529481A patent/JP5000514B2/ja active Active
- 2006-07-27 US US11/997,361 patent/US7843762B2/en active Active
- 2006-07-27 CN CN2006800127383A patent/CN101160566B/zh not_active Expired - Fee Related
- 2006-07-27 WO PCT/JP2006/314860 patent/WO2007018043A1/ja active Application Filing
- 2006-08-07 TW TW095128910A patent/TW200723293A/zh unknown
Also Published As
Publication number | Publication date |
---|---|
US7843762B2 (en) | 2010-11-30 |
WO2007018043A1 (ja) | 2007-02-15 |
CN101160566B (zh) | 2012-03-07 |
JP5000514B2 (ja) | 2012-08-15 |
US20100095056A1 (en) | 2010-04-15 |
JPWO2007018043A1 (ja) | 2009-02-19 |
CN101160566A (zh) | 2008-04-09 |
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