TW200717239A - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

Info

Publication number
TW200717239A
TW200717239A TW095133647A TW95133647A TW200717239A TW 200717239 A TW200717239 A TW 200717239A TW 095133647 A TW095133647 A TW 095133647A TW 95133647 A TW95133647 A TW 95133647A TW 200717239 A TW200717239 A TW 200717239A
Authority
TW
Taiwan
Prior art keywords
circuit
delay time
input
strobe signal
data strobe
Prior art date
Application number
TW095133647A
Other languages
English (en)
Inventor
Shigezumi Matsui
Original Assignee
Renesas Tech Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Tech Corp filed Critical Renesas Tech Corp
Publication of TW200717239A publication Critical patent/TW200717239A/zh

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/022—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in I/O circuitry
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C29/50012—Marginal testing, e.g. race, voltage or current testing of timing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1066—Output synchronization
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
TW095133647A 2005-09-13 2006-09-12 Semiconductor integrated circuit device TW200717239A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2005265819 2005-09-13
JP2006169485A JP5013394B2 (ja) 2005-09-13 2006-06-20 半導体集積回路装置

Publications (1)

Publication Number Publication Date
TW200717239A true TW200717239A (en) 2007-05-01

Family

ID=37854938

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095133647A TW200717239A (en) 2005-09-13 2006-09-12 Semiconductor integrated circuit device

Country Status (3)

Country Link
US (1) US7321525B2 (zh)
JP (1) JP5013394B2 (zh)
TW (1) TW200717239A (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI631574B (zh) * 2013-08-30 2018-08-01 愛思開海力士有限公司 包括測試焊墊的半導體積體電路

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JP4878215B2 (ja) * 2006-05-26 2012-02-15 ルネサスエレクトロニクス株式会社 インタフェース回路及びメモリ制御装置
JP5056070B2 (ja) * 2007-02-28 2012-10-24 富士通セミコンダクター株式会社 Ｄｄｒ−ｓｄｒａｍインターフェース回路
US8207976B2 (en) * 2007-03-15 2012-06-26 Qimonda Ag Circuit
JP5006723B2 (ja) * 2007-07-09 2012-08-22 ルネサスエレクトロニクス株式会社 半導体集積回路装置とそのテスト方法
JP2009043342A (ja) * 2007-08-09 2009-02-26 Panasonic Corp 半導体記憶装置
JP5160856B2 (ja) * 2007-10-24 2013-03-13 ルネサスエレクトロニクス株式会社 Ｄｄｒメモリコントローラ及び半導体装置
KR101455253B1 (ko) * 2007-11-15 2014-10-28 삼성전자주식회사 메모리 컨트롤러
WO2009082502A1 (en) 2007-12-21 2009-07-02 Rambus Inc. Method and apparatus for calibrating write timing in a memory system
US7929361B2 (en) * 2008-03-31 2011-04-19 Advanced Micro Devices, Inc. Circuit using a shared delay locked loop (DLL) and method therefor
US7872937B2 (en) * 2008-03-31 2011-01-18 Globalfoundries Inc. Data driver circuit for a dynamic random access memory (DRAM) controller or the like and method therefor
US7924637B2 (en) * 2008-03-31 2011-04-12 Advanced Micro Devices, Inc. Method for training dynamic random access memory (DRAM) controller timing delays
US7869287B2 (en) * 2008-03-31 2011-01-11 Advanced Micro Devices, Inc. Circuit for locking a delay locked loop (DLL) and method therefor
US7961533B2 (en) * 2008-05-27 2011-06-14 Advanced Micro Devices, Inc. Method and apparatus for implementing write levelization in memory subsystems
US8797811B2 (en) * 2008-11-18 2014-08-05 Qimonda Ag Method and apparatus to reduce power consumption by transferring functionality from memory components to a memory interface
JP2010122842A (ja) * 2008-11-19 2010-06-03 Nec Electronics Corp 遅延調整装置、半導体装置及び遅延調整方法
US7893741B2 (en) * 2009-06-12 2011-02-22 Freescale Semiconductor, Inc. Multiple-stage, signal edge alignment apparatus and methods
US7872494B2 (en) * 2009-06-12 2011-01-18 Freescale Semiconductor, Inc. Memory controller calibration
JP2011081732A (ja) * 2009-10-09 2011-04-21 Elpida Memory Inc 半導体装置及びその調整方法並びにデータ処理システム
JP5655555B2 (ja) * 2010-12-27 2015-01-21 富士通セミコンダクター株式会社 メモリインターフェース回路、メモリインターフェース方法、および電子機器
JP5433593B2 (ja) * 2011-01-21 2014-03-05 株式会社東芝 メモリインターフェイスのタイミング調整回路および方法
JP2012203515A (ja) 2011-03-24 2012-10-22 Toshiba Corp 半導体装置
US8897084B2 (en) * 2011-09-08 2014-11-25 Apple Inc. Dynamic data strobe detection
US9843315B2 (en) * 2011-11-01 2017-12-12 Rambus Inc. Data transmission using delayed timing signals
KR20140026180A (ko) * 2012-08-24 2014-03-05 에스케이하이닉스 주식회사 온 다이 터미네이션 회로
KR101998287B1 (ko) * 2012-11-07 2019-07-10 에스케이하이닉스 주식회사 반도체 장치의 리프레쉬 제어 회로
KR102006243B1 (ko) * 2012-12-24 2019-08-01 에스케이하이닉스 주식회사 반도체 장치의 데이터 라이트 회로
CN105339917A (zh) * 2013-05-30 2016-02-17 惠普发展公司，有限责任合伙企业 访问存储器中数据的分离的存储器控制器
CN103325422B (zh) * 2013-07-17 2016-03-23 苏州兆芯半导体科技有限公司 Sram时序测试电路及测试方法
TWI521508B (zh) * 2013-08-13 2016-02-11 瑞昱半導體股份有限公司 記憶體控制電路與控制記憶體模組之資料讀取程序之方法
KR102235521B1 (ko) 2015-02-13 2021-04-05 삼성전자주식회사 특정 패턴을 갖는 저장 장치 및 그것의 동작 방법
KR102451996B1 (ko) * 2016-03-31 2022-10-07 삼성전자주식회사 기준 전압의 셀프 트레이닝을 수행하는 수신 인터페이스 회로 및 이를 포함하는 메모리 시스템
KR102365110B1 (ko) * 2017-09-13 2022-02-18 삼성전자주식회사 복수의 메모리 장치들에 대한 트레이닝 동작을 지원하는 버퍼 장치를 포함하는 메모리 모듈 및 이를 포함하는 메모리 시스템
KR102447499B1 (ko) 2017-10-19 2022-09-26 삼성전자주식회사 스토리지 장치 및 스토리지 장치의 동작 방법
KR20190068301A (ko) * 2017-12-08 2019-06-18 삼성전자주식회사 지연 고정 루프를 포함하는 메모리 장치 및 메모리 장치의 동작 방법
JP2019153909A (ja) * 2018-03-02 2019-09-12 株式会社リコー 半導体集積回路およびクロック供給方法
KR102648186B1 (ko) * 2018-12-24 2024-03-18 에스케이하이닉스 주식회사 트래이닝 기능을 갖는 반도체 시스템
KR20200078982A (ko) 2018-12-24 2020-07-02 에스케이하이닉스 주식회사 트래이닝 기능을 갖는 반도체 장치 및 반도체 시스템

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JP3522126B2 (ja) * 1998-11-17 2004-04-26 沖電気工業株式会社 同期検出方法及び装置、並びに位相同期方法及び装置
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JP4450586B2 (ja) * 2003-09-03 2010-04-14 株式会社ルネサステクノロジ 半導体集積回路
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US7292500B2 (en) * 2005-07-29 2007-11-06 Agere Systems Inc. Reducing read data strobe latency in a memory system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI631574B (zh) * 2013-08-30 2018-08-01 愛思開海力士有限公司 包括測試焊墊的半導體積體電路

Also Published As

Publication number Publication date
JP2007109203A (ja) 2007-04-26
JP5013394B2 (ja) 2012-08-29
US7321525B2 (en) 2008-01-22
US20070058479A1 (en) 2007-03-15

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