ATE507563T1 - Rekonstruktion des signal-timing in integrierten schaltungen - Google Patents

Rekonstruktion des signal-timing in integrierten schaltungen

Info

Publication number
ATE507563T1
ATE507563T1 AT05731392T AT05731392T ATE507563T1 AT E507563 T1 ATE507563 T1 AT E507563T1 AT 05731392 T AT05731392 T AT 05731392T AT 05731392 T AT05731392 T AT 05731392T AT E507563 T1 ATE507563 T1 AT E507563T1
Authority
AT
Austria
Prior art keywords
signal timing
reconstruction
integrated circuits
communication
input
Prior art date
Application number
AT05731392T
Other languages
English (en)
Inventor
Ivan I Ivanov
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Priority claimed from PCT/US2005/010643 external-priority patent/WO2005098862A2/en
Application granted granted Critical
Publication of ATE507563T1 publication Critical patent/ATE507563T1/de

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/32—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2254—Calibration

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Memory System (AREA)
  • Information Transfer Systems (AREA)
  • Dram (AREA)
  • Read Only Memory (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Logic Circuits (AREA)
AT05731392T 2004-03-31 2005-03-31 Rekonstruktion des signal-timing in integrierten schaltungen ATE507563T1 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE102004015868A DE102004015868A1 (de) 2004-03-31 2004-03-31 Rekonstruktion der Signalzeitgebung in integrierten Schaltungen
US10/921,435 US7289378B2 (en) 2004-03-31 2004-08-19 Reconstruction of signal timing in integrated circuits
PCT/US2005/010643 WO2005098862A2 (en) 2004-03-31 2005-03-31 Reconstruction of signal timing in integrated circuits

Publications (1)

Publication Number Publication Date
ATE507563T1 true ATE507563T1 (de) 2011-05-15

Family

ID=35054111

Family Applications (1)

Application Number Title Priority Date Filing Date
AT05731392T ATE507563T1 (de) 2004-03-31 2005-03-31 Rekonstruktion des signal-timing in integrierten schaltungen

Country Status (4)

Country Link
US (1) US7289378B2 (de)
CN (1) CN1969337B (de)
AT (1) ATE507563T1 (de)
DE (2) DE102004015868A1 (de)

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WO2008082591A2 (en) * 2007-01-02 2008-07-10 Marvell World Trade Ltd. High speed interface for multi-level memory
US7873857B2 (en) 2007-01-18 2011-01-18 Qimonda Ag Multi-component module fly-by output alignment arrangement and method
KR100921003B1 (ko) 2007-12-14 2009-10-09 한국전자통신연구원 신호 전송 장치 및 신호 전송 방법
JP4519923B2 (ja) * 2008-02-29 2010-08-04 株式会社東芝 メモリシステム
US8510598B2 (en) * 2010-03-29 2013-08-13 Dot Hill Systems Corporation Buffer management method and apparatus for power reduction during flush operation
JP4861497B2 (ja) 2010-05-31 2012-01-25 株式会社東芝 データ記憶装置及びメモリ調整方法
US10069487B1 (en) * 2017-03-20 2018-09-04 Xilinx, Inc. Delay chain having Schmitt triggers
KR102563185B1 (ko) * 2018-04-26 2023-08-04 에스케이하이닉스 주식회사 컨트롤러 및 그의 동작 방법
US11361111B2 (en) * 2018-07-09 2022-06-14 Arm Limited Repetitive side channel attack countermeasures
WO2020024149A1 (en) * 2018-08-01 2020-02-06 Micron Technology, Inc. Semiconductor device, delay circuit, and related method
CN111010181B (zh) * 2019-12-19 2023-11-10 深圳市联洲国际技术有限公司 一种ddr信号时序校准方法和装置
TWI749888B (zh) * 2020-11-20 2021-12-11 智原科技股份有限公司 雙倍資料率記憶體系統及相關的閘信號控制電路

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Also Published As

Publication number Publication date
CN1969337A (zh) 2007-05-23
US7289378B2 (en) 2007-10-30
DE102004015868A1 (de) 2005-10-27
CN1969337B (zh) 2010-09-22
US20050219919A1 (en) 2005-10-06
DE602005027678D1 (de) 2011-06-09

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