TW200712259A - A method for etching high dielectric constant materials - Google Patents

A method for etching high dielectric constant materials

Info

Publication number
TW200712259A
TW200712259A TW095130163A TW95130163A TW200712259A TW 200712259 A TW200712259 A TW 200712259A TW 095130163 A TW095130163 A TW 095130163A TW 95130163 A TW95130163 A TW 95130163A TW 200712259 A TW200712259 A TW 200712259A
Authority
TW
Taiwan
Prior art keywords
etching
dielectric constant
high dielectric
dielectric material
gas
Prior art date
Application number
TW095130163A
Other languages
English (en)
Inventor
Xi-Kun Wang
Wei Liu
Yan Du
Mei-Hua Shen
Original Assignee
Applied Materials Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Applied Materials Inc filed Critical Applied Materials Inc
Publication of TW200712259A publication Critical patent/TW200712259A/zh

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31105Etching inorganic layers
    • H01L21/31111Etching inorganic layers by chemical means
    • H01L21/31116Etching inorganic layers by chemical means by dry-etching
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B41/00Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B69/00Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Chemical & Material Sciences (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Inorganic Chemistry (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
TW095130163A 2005-08-22 2006-08-16 A method for etching high dielectric constant materials TW200712259A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/208,573 US7964512B2 (en) 2005-08-22 2005-08-22 Method for etching high dielectric constant materials

Publications (1)

Publication Number Publication Date
TW200712259A true TW200712259A (en) 2007-04-01

Family

ID=37767836

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095130163A TW200712259A (en) 2005-08-22 2006-08-16 A method for etching high dielectric constant materials

Country Status (4)

Country Link
US (1) US7964512B2 (zh)
JP (1) JP2007073952A (zh)
CN (1) CN1921072B (zh)
TW (1) TW200712259A (zh)

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TWI562210B (en) * 2008-08-22 2016-12-11 Taiwan Semiconductor Mfg Co Ltd Method of forming gate structures or semiconductor devices

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US7645710B2 (en) * 2006-03-09 2010-01-12 Applied Materials, Inc. Method and apparatus for fabricating a high dielectric constant transistor gate using a low energy plasma system
US7678710B2 (en) * 2006-03-09 2010-03-16 Applied Materials, Inc. Method and apparatus for fabricating a high dielectric constant transistor gate using a low energy plasma system
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US8183161B2 (en) 2006-09-12 2012-05-22 Tokyo Electron Limited Method and system for dry etching a hafnium containing material
TWI435376B (zh) * 2006-09-26 2014-04-21 Applied Materials Inc 用於缺陷鈍化之高k閘極堆疊的氟電漿處理
JP2009021584A (ja) * 2007-06-27 2009-01-29 Applied Materials Inc 高k材料ゲート構造の高温エッチング方法
US20100003828A1 (en) * 2007-11-28 2010-01-07 Guowen Ding Methods for adjusting critical dimension uniformity in an etch process with a highly concentrated unsaturated hydrocarbon gas
US20090197421A1 (en) * 2008-01-31 2009-08-06 Micron Technology, Inc. Chemistry and compositions for manufacturing integrated circuits
US7782600B2 (en) * 2008-01-31 2010-08-24 Ncr Corporation Access self-service terminal
KR20090103049A (ko) * 2008-03-27 2009-10-01 주식회사 하이닉스반도체 반도체 소자의 제조 방법
US20120244693A1 (en) * 2011-03-22 2012-09-27 Tokyo Electron Limited Method for patterning a full metal gate structure
CN102427036A (zh) * 2011-07-22 2012-04-25 上海华力微电子有限公司 对HfO2薄膜的高选择性干法刻蚀方法
US8808562B2 (en) 2011-09-12 2014-08-19 Tokyo Electron Limited Dry metal etching method
US20150357200A1 (en) * 2012-12-27 2015-12-10 Zeon Corporation Dry etching method
CN106548936B (zh) * 2015-09-23 2022-04-22 北京北方华创微电子装备有限公司 一种金属层的刻蚀方法
US11631680B2 (en) 2018-10-18 2023-04-18 Applied Materials, Inc. Methods and apparatus for smoothing dynamic random access memory bit line metal
US10700072B2 (en) * 2018-10-18 2020-06-30 Applied Materials, Inc. Cap layer for bit line resistance reduction

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI562210B (en) * 2008-08-22 2016-12-11 Taiwan Semiconductor Mfg Co Ltd Method of forming gate structures or semiconductor devices

Also Published As

Publication number Publication date
CN1921072B (zh) 2012-10-03
US7964512B2 (en) 2011-06-21
CN1921072A (zh) 2007-02-28
US20070042601A1 (en) 2007-02-22
JP2007073952A (ja) 2007-03-22

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