TW200702993A - Cache memory system and control method thereof - Google Patents

Cache memory system and control method thereof

Info

Publication number
TW200702993A
TW200702993A TW095105065A TW95105065A TW200702993A TW 200702993 A TW200702993 A TW 200702993A TW 095105065 A TW095105065 A TW 095105065A TW 95105065 A TW95105065 A TW 95105065A TW 200702993 A TW200702993 A TW 200702993A
Authority
TW
Taiwan
Prior art keywords
cache memory
memory system
control method
tac
processor
Prior art date
Application number
TW095105065A
Other languages
English (en)
Inventor
Hazuki Okabayashi
Tetsuya Tanaka
Ryuta Nakanishi
Masaitsu Nakajima
Keisuke Kaneko
Original Assignee
Matsushita Electric Ind Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Ind Co Ltd filed Critical Matsushita Electric Ind Co Ltd
Publication of TW200702993A publication Critical patent/TW200702993A/zh

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
TW095105065A 2005-04-08 2006-02-15 Cache memory system and control method thereof TW200702993A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005112839 2005-04-08

Publications (1)

Publication Number Publication Date
TW200702993A true TW200702993A (en) 2007-01-16

Family

ID=37114853

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095105065A TW200702993A (en) 2005-04-08 2006-02-15 Cache memory system and control method thereof

Country Status (8)

Country Link
US (1) US7953935B2 (zh)
EP (1) EP1868101B1 (zh)
JP (1) JP4090497B2 (zh)
KR (1) KR20070093452A (zh)
CN (1) CN101151600B (zh)
DE (1) DE602006011292D1 (zh)
TW (1) TW200702993A (zh)
WO (1) WO2006112111A1 (zh)

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KR100818920B1 (ko) * 2006-02-10 2008-04-04 삼성전자주식회사 그래픽 객체의 처리 시 발생된 키 이벤트를 제어하는 장치및 그 방법
US8296123B2 (en) 2006-02-17 2012-10-23 Google Inc. Encoding and adaptive, scalable accessing of distributed models
TW201015319A (en) * 2008-09-17 2010-04-16 Panasonic Corp Cache memory, memory system, data copying method and data rewriting method
KR100985517B1 (ko) * 2008-12-04 2010-10-05 주식회사 에이디칩스 캐시메모리 제어방법
JP4768054B2 (ja) 2009-06-23 2011-09-07 インターナショナル・ビジネス・マシーンズ・コーポレーション キャッシュ制御方法
US8214598B2 (en) * 2009-12-22 2012-07-03 Intel Corporation System, method, and apparatus for a cache flush of a range of pages and TLB invalidation of a range of entries
KR101502827B1 (ko) * 2014-03-20 2015-03-17 주식회사 에이디칩스 컴퓨터 시스템에서의 캐시 무효화 방법
KR102128475B1 (ko) * 2014-03-27 2020-07-01 에스케이하이닉스 주식회사 반도체 메모리 장치
US9779025B2 (en) 2014-06-02 2017-10-03 Micron Technology, Inc. Cache architecture for comparing data
CN105243685B (zh) * 2015-11-17 2018-01-02 上海兆芯集成电路有限公司 数据单元的关联性检查方法以及使用该方法的装置
CN105427368B (zh) * 2015-11-17 2018-03-20 上海兆芯集成电路有限公司 数据单元的关联性检查方法以及使用该方法的装置
US10101925B2 (en) * 2015-12-23 2018-10-16 Toshiba Memory Corporation Data invalidation acceleration through approximation of valid data counts
KR102649657B1 (ko) * 2018-07-17 2024-03-21 에스케이하이닉스 주식회사 데이터 저장 장치 및 동작 방법, 이를 포함하는 스토리지 시스템
US11281585B2 (en) 2018-08-30 2022-03-22 Micron Technology, Inc. Forward caching memory systems and methods
EP3893119B1 (en) * 2019-02-21 2023-07-26 Huawei Technologies Co., Ltd. System on chip, routing method for access command and terminal
US11086791B2 (en) * 2019-08-29 2021-08-10 Micron Technology, Inc. Methods for supporting mismatched transaction granularities

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JPS5119453A (en) 1974-08-08 1976-02-16 Fujitsu Ltd Patsufua memoriseigyohoshiki
JPS6045855A (ja) 1983-08-22 1985-03-12 Fujitsu Ltd 磁気ディスク装置の順次アクセス検出方法
US5375216A (en) 1992-02-28 1994-12-20 Motorola, Inc. Apparatus and method for optimizing performance of a cache memory in a data processing system
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JPH0784879A (ja) 1993-09-09 1995-03-31 Toshiba Corp キャッシュメモリ装置
JPH07295882A (ja) 1994-04-22 1995-11-10 Hitachi Ltd 情報処理装置、及び、情報処理システム
US5860110A (en) * 1995-08-22 1999-01-12 Canon Kabushiki Kaisha Conference maintenance method for cache memories in multi-processor system triggered by a predetermined synchronization point and a predetermined condition
JP3175675B2 (ja) 1997-12-04 2001-06-11 日本電気株式会社 プリフェッチ制御装置
JPH11272551A (ja) 1998-03-19 1999-10-08 Hitachi Ltd キャッシュメモリのフラッシュ制御方式およびキャッシュメモリ
EP1182566B1 (en) 2000-08-21 2013-05-15 Texas Instruments France Cache operation based on range of addresses
JP2003223360A (ja) * 2002-01-29 2003-08-08 Hitachi Ltd キャッシュメモリシステムおよびマイクロプロセッサ
JP4067887B2 (ja) 2002-06-28 2008-03-26 富士通株式会社 プリフェッチを行う演算処理装置、情報処理装置及びそれらの制御方法
JP2004118305A (ja) 2002-09-24 2004-04-15 Sharp Corp キャッシュメモリ制御装置
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US20070028055A1 (en) 2003-09-19 2007-02-01 Matsushita Electric Industrial Co., Ltd Cache memory and cache memory control method
US7502887B2 (en) 2003-11-12 2009-03-10 Panasonic Corporation N-way set associative cache memory and control method thereof
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US7984243B2 (en) 2003-11-18 2011-07-19 Panasonic Corporation Cache memory and method for cache entry replacement based on modified access order
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JP4521206B2 (ja) * 2004-03-01 2010-08-11 株式会社日立製作所 ネットワークストレージシステム、コマンドコントローラ、及びネットワークストレージシステムにおけるコマンド制御方法
WO2005091146A1 (ja) 2004-03-24 2005-09-29 Matsushita Electric Industrial Co., Ltd. キャッシュメモリ及びその制御方法

Also Published As

Publication number Publication date
WO2006112111A1 (ja) 2006-10-26
KR20070093452A (ko) 2007-09-18
EP1868101B1 (en) 2009-12-23
JP4090497B2 (ja) 2008-05-28
US7953935B2 (en) 2011-05-31
US20090100231A1 (en) 2009-04-16
CN101151600B (zh) 2012-02-22
EP1868101A4 (en) 2009-01-21
CN101151600A (zh) 2008-03-26
EP1868101A1 (en) 2007-12-19
DE602006011292D1 (de) 2010-02-04
JPWO2006112111A1 (ja) 2008-11-27

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