TW200629026A - Die-level traceability mechanism for semiconductor assembly and test facility - Google Patents

Die-level traceability mechanism for semiconductor assembly and test facility

Info

Publication number
TW200629026A
TW200629026A TW094136036A TW94136036A TW200629026A TW 200629026 A TW200629026 A TW 200629026A TW 094136036 A TW094136036 A TW 094136036A TW 94136036 A TW94136036 A TW 94136036A TW 200629026 A TW200629026 A TW 200629026A
Authority
TW
Taiwan
Prior art keywords
die
lot
dies
index string
test facility
Prior art date
Application number
TW094136036A
Other languages
English (en)
Chinese (zh)
Inventor
Horne Loong Koh
Original Assignee
Applied Materials Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Applied Materials Inc filed Critical Applied Materials Inc
Publication of TW200629026A publication Critical patent/TW200629026A/zh

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06QINFORMATION AND COMMUNICATION TECHNOLOGY [ICT] SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES; SYSTEMS OR METHODS SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES, NOT OTHERWISE PROVIDED FOR
    • G06Q10/00Administration; Management
    • G06Q10/06Resources, workflows, human or project management; Enterprise or organisation planning; Enterprise or organisation modelling
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304Mechanical treatment, e.g. grinding, polishing, cutting
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06QINFORMATION AND COMMUNICATION TECHNOLOGY [ICT] SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES; SYSTEMS OR METHODS SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES, NOT OTHERWISE PROVIDED FOR
    • G06Q10/00Administration; Management
    • G06Q10/08Logistics, e.g. warehousing, loading or distribution; Inventory or stock management
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof

Landscapes

  • Engineering & Computer Science (AREA)
  • Business, Economics & Management (AREA)
  • Economics (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Strategic Management (AREA)
  • Human Resources & Organizations (AREA)
  • Entrepreneurship & Innovation (AREA)
  • General Business, Economics & Management (AREA)
  • Quality & Reliability (AREA)
  • Theoretical Computer Science (AREA)
  • Tourism & Hospitality (AREA)
  • Development Economics (AREA)
  • Marketing (AREA)
  • Operations Research (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Educational Administration (AREA)
  • Game Theory and Decision Science (AREA)
  • General Factory Administration (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
TW094136036A 2004-10-15 2005-10-14 Die-level traceability mechanism for semiconductor assembly and test facility TW200629026A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US61880504P 2004-10-15 2004-10-15

Publications (1)

Publication Number Publication Date
TW200629026A true TW200629026A (en) 2006-08-16

Family

ID=35754092

Family Applications (1)

Application Number Title Priority Date Filing Date
TW094136036A TW200629026A (en) 2004-10-15 2005-10-14 Die-level traceability mechanism for semiconductor assembly and test facility

Country Status (7)

Country Link
US (2) US7343214B2 (enExample)
EP (1) EP1810326A1 (enExample)
JP (1) JP2008517465A (enExample)
KR (1) KR20070085369A (enExample)
CN (1) CN101040290A (enExample)
TW (1) TW200629026A (enExample)
WO (1) WO2006044399A1 (enExample)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI451218B (zh) * 2008-01-07 2014-09-01 美特拉斯有限公司 統計程序控制之方法

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CN102640253B (zh) 2010-10-04 2014-06-18 晟碟半导体(上海)有限公司 分立组件后向可追溯性和半导体装置前向可追溯性
US9559113B2 (en) 2014-05-01 2017-01-31 Macronix International Co., Ltd. SSL/GSL gate oxide in 3D vertical channel NAND
KR20160018227A (ko) * 2014-08-08 2016-02-17 에스케이하이닉스 주식회사 웨이퍼 처리 시스템 및 이를 이용한 웨이퍼 처리 방법
US10419410B2 (en) * 2016-12-15 2019-09-17 Seagate Technology Llc Automatic generation of unique identifiers for distributed directory management users
KR102653937B1 (ko) 2018-07-17 2024-04-02 삼성전자주식회사 반도체 장치의 테스트 방법및 반도체 장치의 테스트 시스템
US11063000B2 (en) * 2019-01-29 2021-07-13 Infineon Technologies Ag Semiconductor package authentication feature
US11450616B2 (en) 2020-07-29 2022-09-20 Nxp Usa, Inc. Using a backside mask layer for forming a unique die mark identifier pattern

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI451218B (zh) * 2008-01-07 2014-09-01 美特拉斯有限公司 統計程序控制之方法

Also Published As

Publication number Publication date
US20080071413A1 (en) 2008-03-20
US20060085089A1 (en) 2006-04-20
CN101040290A (zh) 2007-09-19
US7343214B2 (en) 2008-03-11
WO2006044399A1 (en) 2006-04-27
KR20070085369A (ko) 2007-08-27
EP1810326A1 (en) 2007-07-25
JP2008517465A (ja) 2008-05-22

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