TW200625327A - Self refresh circuit of PSRAM for real access time measurement and operating method for the same - Google Patents

Self refresh circuit of PSRAM for real access time measurement and operating method for the same

Info

Publication number
TW200625327A
TW200625327A TW094138533A TW94138533A TW200625327A TW 200625327 A TW200625327 A TW 200625327A TW 094138533 A TW094138533 A TW 094138533A TW 94138533 A TW94138533 A TW 94138533A TW 200625327 A TW200625327 A TW 200625327A
Authority
TW
Taiwan
Prior art keywords
refresh
command
access time
refresh circuit
mrs
Prior art date
Application number
TW094138533A
Other languages
English (en)
Other versions
TWI320184B (en
Inventor
Soo-Young Kim
Hyun-Seok Lee
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of TW200625327A publication Critical patent/TW200625327A/zh
Application granted granted Critical
Publication of TWI320184B publication Critical patent/TWI320184B/zh

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40611—External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40615—Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1045—Read-write mode select circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/401—Indexing scheme relating to cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C2211/406—Refreshing of dynamic cells
    • G11C2211/4061—Calibration or ate or cycle tuning

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Dram (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
TW094138533A 2004-11-03 2005-11-03 Self refresh circuit of psram for real access time measurement and operating method for the same TWI320184B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020040088601A KR100614200B1 (ko) 2004-11-03 2004-11-03 리얼 억세스 타임 측정을 위한 의사 스태틱 램의 셀프리프레쉬 회로 및 이를 위한 셀프 리프레쉬 회로의 동작방법

Publications (2)

Publication Number Publication Date
TW200625327A true TW200625327A (en) 2006-07-16
TWI320184B TWI320184B (en) 2010-02-01

Family

ID=36261652

Family Applications (1)

Application Number Title Priority Date Filing Date
TW094138533A TWI320184B (en) 2004-11-03 2005-11-03 Self refresh circuit of psram for real access time measurement and operating method for the same

Country Status (3)

Country Link
US (1) US7187609B2 (zh)
KR (1) KR100614200B1 (zh)
TW (1) TWI320184B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI653635B (zh) 2014-10-14 2019-03-11 韓商愛思開海力士有限公司 修復電路及包含該修復電路的半導體記憶體裝置

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100810612B1 (ko) * 2006-06-16 2008-03-06 삼성전자주식회사 반도체 메모리 장치 및 이 장치의 리플레시 동작 시 추가기능 수행 방법
US20090172246A1 (en) * 2007-12-26 2009-07-02 Sandisk Il Ltd. Device and method for managing initialization thereof
KR101046241B1 (ko) * 2009-05-22 2011-07-04 주식회사 하이닉스반도체 리프레시 주기 신호 생성 회로 및 이를 이용한 반도체 집적회로
US8854344B2 (en) * 2010-12-13 2014-10-07 Ati Technologies Ulc Self-refresh panel time synchronization
WO2012115839A1 (en) 2011-02-23 2012-08-30 Rambus Inc. Protocol for memory power-mode control
KR20130097574A (ko) * 2012-02-24 2013-09-03 에스케이하이닉스 주식회사 커맨드디코더
KR101974108B1 (ko) * 2012-07-30 2019-08-23 삼성전자주식회사 리프레쉬 어드레스 생성기, 이를 포함하는 휘발성 메모리 장치 및 휘발성 메모리 장치의 리프레쉬 방법
KR20160138616A (ko) 2015-05-26 2016-12-06 에스케이하이닉스 주식회사 셀프 리프레쉬 장치
KR20170008083A (ko) * 2015-07-13 2017-01-23 에스케이하이닉스 주식회사 리프레쉬 검증 회로, 반도체 장치 및 반도체 시스템
KR102399475B1 (ko) * 2015-12-28 2022-05-18 삼성전자주식회사 리프레쉬 콘트롤러 및 이를 포함하는 메모리 장치
JP6709825B2 (ja) 2018-06-14 2020-06-17 華邦電子股▲ふん▼有限公司Ｗｉｎｂｏｎｄ Ｅｌｅｃｔｒｏｎｉｃｓ Ｃｏｒｐ． Ｄｒａｍ及びその操作方法
TWI676180B (zh) * 2018-09-04 2019-11-01 華邦電子股份有限公司 記憶體裝置以及虛擬靜態隨機存取記憶體之刷新方法
TWI767267B (zh) * 2020-07-03 2022-06-11 華邦電子股份有限公司 記憶體控制器

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3832218B2 (ja) 2000-09-20 2006-10-11 セイコーエプソン株式会社 半導体メモリ装置のリフレッシュを考慮した制御
JP2002304885A (ja) 2001-04-05 2002-10-18 Fujitsu Ltd 半導体集積回路
JP2002373489A (ja) * 2001-06-15 2002-12-26 Mitsubishi Electric Corp 半導体記憶装置
KR100455393B1 (ko) 2002-08-12 2004-11-06 삼성전자주식회사 리프레시 플래그를 발생시키는 반도체 메모리 장치 및반도체 메모리 시스템.

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI653635B (zh) 2014-10-14 2019-03-11 韓商愛思開海力士有限公司 修復電路及包含該修復電路的半導體記憶體裝置

Also Published As

Publication number Publication date
KR20060039498A (ko) 2006-05-09
US20060092741A1 (en) 2006-05-04
US7187609B2 (en) 2007-03-06
KR100614200B1 (ko) 2006-08-21
TWI320184B (en) 2010-02-01

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees