TW200617973A - Memory device capable of changing data output mode - Google Patents

Memory device capable of changing data output mode

Info

Publication number
TW200617973A
TW200617973A TW094117269A TW94117269A TW200617973A TW 200617973 A TW200617973 A TW 200617973A TW 094117269 A TW094117269 A TW 094117269A TW 94117269 A TW94117269 A TW 94117269A TW 200617973 A TW200617973 A TW 200617973A
Authority
TW
Taiwan
Prior art keywords
output mode
memory device
device capable
data output
changing data
Prior art date
Application number
TW094117269A
Other languages
English (en)
Other versions
TWI268513B (en
Inventor
Jun-Seop Chung
Original Assignee
Hynix Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hynix Semiconductor Inc filed Critical Hynix Semiconductor Inc
Publication of TW200617973A publication Critical patent/TW200617973A/zh
Application granted granted Critical
Publication of TWI268513B publication Critical patent/TWI268513B/zh

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1045—Read-write mode select circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/1201—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising I/O circuitry
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/48—Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/84—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability
    • G11C29/846—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability by choosing redundant lines at an output stage
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/06—Address interface arrangements, e.g. address buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C2029/1804—Manipulation of word size
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/10—Aspects relating to interfaces of memory device to external buses
    • G11C2207/105—Aspects related to pads, pins or terminals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/785—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Read Only Memory (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Dram (AREA)
TW094117269A 2004-11-19 2005-05-26 Memory device capable of changing data output mode TWI268513B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020040095368A KR100558050B1 (ko) 2004-11-19 2004-11-19 데이터 출력 모드를 변경할 수 있는 메모리 장치

Publications (2)

Publication Number Publication Date
TW200617973A true TW200617973A (en) 2006-06-01
TWI268513B TWI268513B (en) 2006-12-11

Family

ID=36460794

Family Applications (1)

Application Number Title Priority Date Filing Date
TW094117269A TWI268513B (en) 2004-11-19 2005-05-26 Memory device capable of changing data output mode

Country Status (6)

Country Link
US (1) US7126864B2 (zh)
JP (1) JP4544122B2 (zh)
KR (1) KR100558050B1 (zh)
CN (1) CN1776820B (zh)
DE (1) DE102005022768A1 (zh)
TW (1) TWI268513B (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100757925B1 (ko) * 2006-04-05 2007-09-11 주식회사 하이닉스반도체 반도체 메모리의 데이터 출력 장치 및 제어방법
KR100813627B1 (ko) * 2007-01-04 2008-03-14 삼성전자주식회사 멀티-비트 데이터를 저장할 수 있는 플래시 메모리 장치를제어하는 메모리 제어기와 그것을 포함한 메모리 시스템
FR2997511B1 (fr) * 2012-10-31 2015-01-02 Marc Guian Dispositif de transmission de donnees de geolocalisation et de mesure, procede associe.

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6264967A (ja) 1985-09-17 1987-03-24 Oki Electric Ind Co Ltd 集積回路試験装置のテストパタ−ン信号発生回路
JPH02232578A (ja) * 1989-03-07 1990-09-14 Mitsubishi Electric Corp 半導体評価装置
KR920006117B1 (ko) * 1989-12-27 1992-07-27 삼성전자 주식회사 Mhs시스템과 퍼스널 컴퓨터간의 동기인터페이스회로
US5519657A (en) * 1993-09-30 1996-05-21 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device having a redundant memory array and a testing method thereof
KR0145888B1 (ko) * 1995-04-13 1998-11-02 김광호 반도체 메모리장치의 동작 모드 전환회로
KR0172372B1 (ko) * 1995-12-22 1999-03-30 김광호 반도체 메모리 장치의 병합 데이타 출력 모드 선택 방법
US6122206A (en) * 1998-03-16 2000-09-19 Nec Corporation Semiconductor memory device having means for outputting redundancy replacement selection signal for each bank
US5978297A (en) * 1998-04-28 1999-11-02 Micron Technology, Inc. Method and apparatus for strobing antifuse circuits in a memory device
KR100304709B1 (ko) * 1999-07-23 2001-11-01 윤종용 외부에서 데이터 입출력 모드를 제어할 수 있는 반도체 메모리장치
JP2001126470A (ja) * 1999-10-26 2001-05-11 Mitsubishi Electric Corp 半導体記憶装置
JP2001273788A (ja) * 2000-03-29 2001-10-05 Hitachi Ltd 半導体記憶装置
JP2002140895A (ja) * 2000-08-21 2002-05-17 Mitsubishi Electric Corp 半導体記憶装置
JP2002093192A (ja) * 2000-09-18 2002-03-29 Mitsubishi Electric Corp 半導体記憶装置の試験方法
KR100380346B1 (ko) * 2000-10-16 2003-04-11 삼성전자주식회사 리던던시 로직셀을 갖는 반도체 메모리 장치 및 리페어 방법
KR100383259B1 (ko) * 2000-11-23 2003-05-09 삼성전자주식회사 반도체 메모리 장치 및 이 장치의 프로그램된 불량어드레스 확인 방법
JP2002237198A (ja) * 2001-02-09 2002-08-23 Mitsubishi Electric Corp 半導体記憶回路装置並びにその検査方法及びセル不良救済方法
KR100462877B1 (ko) * 2002-02-04 2004-12-17 삼성전자주식회사 반도체 메모리 장치, 및 이 장치의 불량 셀 어드레스프로그램 회로 및 방법

Also Published As

Publication number Publication date
CN1776820B (zh) 2011-06-22
CN1776820A (zh) 2006-05-24
JP2006147127A (ja) 2006-06-08
JP4544122B2 (ja) 2010-09-15
US7126864B2 (en) 2006-10-24
DE102005022768A1 (de) 2006-07-27
US20060109724A1 (en) 2006-05-25
TWI268513B (en) 2006-12-11
KR100558050B1 (ko) 2006-03-07

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees