TW200610014A - Method for designing semiconductor device and semiconductor device - Google Patents

Method for designing semiconductor device and semiconductor device

Info

Publication number
TW200610014A
TW200610014A TW094131509A TW94131509A TW200610014A TW 200610014 A TW200610014 A TW 200610014A TW 094131509 A TW094131509 A TW 094131509A TW 94131509 A TW94131509 A TW 94131509A TW 200610014 A TW200610014 A TW 200610014A
Authority
TW
Taiwan
Prior art keywords
semiconductor device
designing
present
power supply
area ratio
Prior art date
Application number
TW094131509A
Other languages
English (en)
Inventor
Takayuki Araki
Fumihiro Kimura
Junichi Shimada
Kazuhisa Fujita
Original Assignee
Matsushita Electric Ind Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Ind Co Ltd filed Critical Matsushita Electric Ind Co Ltd
Publication of TW200610014A publication Critical patent/TW200610014A/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5286—Arrangements of power or ground buses
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
TW094131509A 2004-09-15 2005-09-13 Method for designing semiconductor device and semiconductor device TW200610014A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2004268769A JP4164056B2 (ja) 2004-09-15 2004-09-15 半導体装置の設計方法及び半導体装置

Publications (1)

Publication Number Publication Date
TW200610014A true TW200610014A (en) 2006-03-16

Family

ID=35427959

Family Applications (1)

Application Number Title Priority Date Filing Date
TW094131509A TW200610014A (en) 2004-09-15 2005-09-13 Method for designing semiconductor device and semiconductor device

Country Status (5)

Country Link
US (3) US20060056219A1 (zh)
EP (1) EP1638144A3 (zh)
JP (1) JP4164056B2 (zh)
CN (2) CN1750251A (zh)
TW (1) TW200610014A (zh)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4144892B2 (ja) * 2006-08-28 2008-09-03 キヤノン株式会社 光電変換装置及び撮像装置
JP2008270276A (ja) * 2007-04-16 2008-11-06 Nec Electronics Corp ダミーパターン配置装置、ダミーパターンの配置方法、及び半導体装置
JP5292005B2 (ja) * 2008-07-14 2013-09-18 ルネサスエレクトロニクス株式会社 半導体集積回路
US8566776B2 (en) * 2008-11-13 2013-10-22 Qualcomm Incorporated Method to automatically add power line in channel between macros
US8129095B2 (en) * 2009-04-08 2012-03-06 International Business Machines Corporation Methods, photomasks and methods of fabricating photomasks for improving damascene wire uniformity without reducing performance
JP2010278189A (ja) * 2009-05-28 2010-12-09 Renesas Electronics Corp 半導体集積回路の設計方法及び設計システム
US8659126B2 (en) * 2011-12-07 2014-02-25 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit ground shielding structure
US8610247B2 (en) 2011-12-30 2013-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for a transformer with magnetic features
JP2015079848A (ja) * 2013-10-17 2015-04-23 シナプティクス・ディスプレイ・デバイス株式会社 表示装置駆動用半導体集積回路装置
US9330224B2 (en) * 2014-04-30 2016-05-03 Oracle International Corporation Method and apparatus for dummy cell placement management
US9570388B2 (en) 2015-06-26 2017-02-14 International Business Machines Corporation FinFET power supply decoupling
US10580734B2 (en) * 2015-12-26 2020-03-03 Intel Corporation Ground plane vertical isolation of, ground line coaxial isolation of, and impedance tuning of horizontal data signal transmission lines routed through package devices
US10002222B2 (en) * 2016-07-14 2018-06-19 Arm Limited System and method for perforating redundant metal in self-aligned multiple patterning
US11139241B2 (en) * 2016-12-07 2021-10-05 Intel Corporation Integrated circuit device with crenellated metal trace layout
US10423752B2 (en) 2017-09-29 2019-09-24 International Business Machines Corporation Semiconductor package metal shadowing checks
US10423751B2 (en) 2017-09-29 2019-09-24 International Business Machines Corporation Semiconductor package floating metal checks
US10468090B1 (en) * 2018-09-10 2019-11-05 Micron Technology, Inc. Multilayered network of power supply lines
JP2022051365A (ja) * 2020-09-18 2022-03-31 キオクシア株式会社 半導体記憶装置

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5441915A (en) * 1992-09-01 1995-08-15 Taiwan Semiconductor Manufacturing Company Ltd. Process of fabrication planarized metallurgy structure for a semiconductor device
US5981384A (en) * 1995-08-14 1999-11-09 Micron Technology, Inc. Method of intermetal dielectric planarization by metal features layout modification
US5959320A (en) * 1997-03-18 1999-09-28 Lsi Logic Corporation Semiconductor die having on-die de-coupling capacitance
JPH1174523A (ja) * 1997-06-19 1999-03-16 Toshiba Corp 半導体装置及びその製造方法
JP2001077543A (ja) * 1999-09-03 2001-03-23 Fujitsu Ltd 多層配線基板
JP2001118988A (ja) * 1999-10-15 2001-04-27 Mitsubishi Electric Corp 半導体装置
JP2001339047A (ja) * 2000-05-29 2001-12-07 Matsushita Electric Ind Co Ltd 半導体装置
JP2002118235A (ja) * 2000-10-10 2002-04-19 Mitsubishi Electric Corp 半導体装置、半導体製造方法、および半導体製造用マスク
JP3806016B2 (ja) * 2000-11-30 2006-08-09 富士通株式会社 半導体集積回路
JP3621354B2 (ja) * 2001-04-04 2005-02-16 Ｎｅｃエレクトロニクス株式会社 半導体集積回路の配線方法及び構造
JP3768433B2 (ja) * 2001-11-19 2006-04-19 株式会社ルネサステクノロジ 半導体装置の設計方法
US7171645B2 (en) * 2002-08-06 2007-01-30 Matsushita Electric Industrial Co., Ltd. Semiconductor device, method of generating pattern for semiconductor device, method of manufacturing semiconductor device and device of generating pattern used for semiconductor device
JP2004139181A (ja) * 2002-10-15 2004-05-13 Renesas Technology Corp レイアウト装置及びプログラム
JP3799021B2 (ja) * 2003-02-14 2006-07-19 株式会社半導体エネルギー研究所 液晶表示装置

Also Published As

Publication number Publication date
EP1638144A2 (en) 2006-03-22
JP2006086299A (ja) 2006-03-30
US20060056219A1 (en) 2006-03-16
JP4164056B2 (ja) 2008-10-08
CN101355077A (zh) 2009-01-28
CN1750251A (zh) 2006-03-22
EP1638144A3 (en) 2007-10-10
US20080203562A1 (en) 2008-08-28
US20090020784A1 (en) 2009-01-22

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